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Subversion Repositories epc_rfid_transponder

[/] [epc_rfid_transponder/] [trunk/] [symbdec.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------     
--
--     Title          : EPC Class1 Gen2 RFID Tag - Symbol Decoder   
--
--     File name      : symbdec.vhd 
--
--     Description    : Tag symbol decoder detects valid frames decoding command 
--                      preambles and frame-syncs.    
--
--     Authors        : Erwing R. Sanchez <erwing.sanchezs@polito.it>
--                                 
-------------------------------------------------------------------------------            
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.numeric_std.all;
library work;
use work.epc_tag.all;
 
 
entity SymbolDecoder is
  generic (
    LOG2_10_TARI_CK_CYC        : integer := 9;  -- Log2(clock cycles for 10 maximum TARI value) (def:
-- Log2(490) = 9 @TCk=520ns)
    DELIMITIER_TIME_CK_CYC_MIN : integer := 22;  -- Min Clock cycles for 12,5 us delimitier
    DELIMITIER_TIME_CK_CYC_MAX : integer := 24);  -- Max Clock cycles for 12,5 us delimitier
 
  port (
    clk      : in  std_logic;
    rst_n    : in  std_logic;
    tdi      : in  std_logic;
    en       : in  std_logic;
    start    : in  std_logic;
    sserror  : out std_logic;
    ssovalid : out std_logic;
    sso      : out std_logic);          -- serial symbol output
 
end SymbolDecoder;
 
 
architecture symbdec1 of SymbolDecoder is
 
  component COUNTERCLR
    generic (
      width : integer);
    port (
      clk    : in  std_logic;
      rst_n  : in  std_logic;
      en     : in  std_logic;
      clear  : in  std_logic;
      outcnt : out std_logic_vector(width-1 downto 0));
  end component;
 
  type RecFSM_t is (st0_Start, st0b_Delimitier, st1_Dat0H, st2_Dat0L, st3_RTcalH, st4_RTcalL, st5_Sym0H, st6_Sym0L, st6b_Sym0L_TR, st7_SymH, st8_SymL, st9_SymH_TR, st10_SymL_TR);
 
  signal StRec, NextStRec                      : RecFSM_t;
  signal CntEn, CntClr                         : std_logic;
  signal CntEn_i, CntClr_i                     : std_logic;
  signal TRCalEn, RTCalEn                      : std_logic;
  signal TRCalEn_i, RTCalEn_i                  : std_logic;
  signal TARI4En, TARI4En_i                    : std_logic;
  signal CntReg, RTCalReg, TRCalReg            : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);
  signal RTCaldiv2Reg, TARI4Reg                : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);
  signal RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2 : std_logic;
  signal Symb_GRTH_TARI4                       : std_logic;
  signal ssovalid_i, sso_i, sserror_i          : std_logic;
  signal DelimitierComparisoOK                 : std_logic;
 
begin  -- Receiver1
 
  RTCaldiv2Reg <= '0' & RTCalReg(LOG2_10_TARI_CK_CYC-1 downto 1);
 
  SYNCRO : process(clk, rst_n)
  begin  -- process
    if clk'event and clk = '1' then
      if rst_n = '0' then
        CntEn    <= '0';
        TRCalEn  <= '0';
        RTCalEn  <= '0';
        TARI4En  <= '0';
        sserror  <= '0';
        ssovalid <= '0';
        sso      <= '0';
        StRec    <= st0_start;
      else
        if en = '1' then
          StRec    <= NextStRec;
          CntEn    <= CntEn_i;
          TRCalEn  <= TRCalEn_i;
          RTCalEn  <= RTCalEn_i;
          TARI4En  <= TARI4En_i;
          CntClr   <= CntClr_i;
          sserror  <= sserror_i;
          ssovalid <= ssovalid_i;
          sso      <= sso_i;
        end if;
      end if;
    end if;
  end process;
 
 
  NEXT_ST : process (StRec, tdi, start, TRCalEn, Symb_GRTH_TARI4, DelimitierComparisoOK)
  begin  -- process NEXT_ST
    NextStRec <= StRec;
    case StRec is
      when st0_Start =>
        if tdi = '0' then
          NextStRec <= st0b_Delimitier;
        end if;
      when st0b_Delimitier =>
        if tdi = '1' then
          if DelimitierComparisoOK = '1' then
            NextStRec <= st1_Dat0H;
          else
            NextStRec <= st0_Start;
          end if;
        end if;
      when st1_Dat0H =>
        if tdi = '0' then
          NextStRec <= st2_Dat0L;
        end if;
      when st2_Dat0L =>
        if tdi = '1' then
          NextStRec <= st3_RTcalH;
        end if;
      when st3_RTcalH =>
        if tdi = '0' then
          NextStRec <= st4_RTcalL;
        end if;
      when st4_RTcalL =>
        if tdi = '1' then
          NextStRec <= st5_Sym0H;
        end if;
      when st5_Sym0H =>
        if tdi = '0' then
          NextStRec <= st6_Sym0L;
        end if;
      when st6_Sym0L =>
        if TRCalEn = '1' then
          NextStRec <= st6b_Sym0L_TR;
        elsif tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when st6b_Sym0L_TR =>
        if tdi = '1' then
          NextStRec <= st9_SymH_TR;
        end if;
      when st9_SymH_TR =>
        if tdi = '0' then
          NextStRec <= st10_SymL_TR;
        end if;
      when st10_SymL_TR =>
        if tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when st7_SymH =>
        if Symb_GRTH_TARI4 = '1' then
          NextStRec <= st0_Start;
        elsif start = '1'then
          NextStRec <= st0_Start;
        elsif tdi = '0' then
          NextStRec <= st8_SymL;
        end if;
      when st8_SymL =>
        if Symb_GRTH_TARI4 = '1' then
          NextStRec <= st0_Start;
        elsif start = '1' then
          NextStRec <= st0_Start;
        elsif tdi = '1' then
          NextStRec <= st7_SymH;
        end if;
      when others =>
        NextStRec <= st0_start;
    end case;
  end process NEXT_ST;
 
 
  OUTPUT_DEC : process (StRec, tdi, RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2, Symb_GRTH_TARI4)
  begin  -- process OUTPUT_DEC
    CntEn_i    <= '0';
    TRCalEn_i  <= '0';
    RTCalEn_i  <= '0';
    TARI4En_i  <= '0';
    CntClr_i   <= '0';
    sserror_i  <= '0';
    ssovalid_i <= '0';
    sso_i      <= '0';
 
    case StRec is
      when st0_Start =>
        CntClr_i <= '1';
      when st0b_Delimitier =>
        if tdi = '0' then
          CntEn_i <= '1';
        else
          CntClr_i <= '1';
        end if;
      when st1_Dat0H =>
        CntEn_i <= '1';
      when st2_Dat0L =>
        if tdi = '0' then
          CntEn_i <= '1';
        else
          CntClr_i  <= '1';
          TARI4En_i <= '1';
        end if;
      when st3_RTcalH =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          -- Load RTCal value
          CntClr_i  <= '1';
          RTCalEn_i <= '1';
        end if;
      when st4_RTcalL =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st5_Sym0H =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          CntClr_i <= '1';
          if RTCal_GRTH_TRCal = '1' then
            -- Send valid Symbol
            ssovalid_i <= '1';
            if Symb_GRTH_RTCaldiv2 = '1' then
              sso_i <= '1';
            else
              sso_i <= '0';
            end if;
          else
            -- Load TRCal value (Preamble detected ("Query" comm.))
            TRCalEn_i <= '1';
          end if;
        end if;
      when st6_Sym0L =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st6b_Sym0L_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when st7_SymH =>
        if Symb_GRTH_TARI4 = '1' then
          sserror_i <= '1';
        elsif tdi = '1' then
          CntEn_i <= '1';
        else
          -- Send valid Symbol
          -- CntClr_i   <= '1';
          ssovalid_i <= '1';
          if Symb_GRTH_RTCaldiv2 = '1' then
            sso_i <= '1';
          else
            sso_i <= '0';
          end if;
        end if;
      when st8_SymL =>
        if Symb_GRTH_TARI4 = '1' then
          sserror_i <= '1';
        elsif tdi = '1' then
          CntClr_i <= '1';
        end if;
      when st9_SymH_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        else
          -- Send valid Symbol
          CntClr_i   <= '1';
          ssovalid_i <= '1';
          if Symb_GRTH_RTCaldiv2 = '1' then
            sso_i <= '1';
          else
            sso_i <= '0';
          end if;
        end if;
      when st10_SymL_TR =>
        if tdi = '1' then
          CntEn_i <= '1';
        end if;
      when others => null;
    end case;
  end process OUTPUT_DEC;
 
 
  GRTH1 : process (RTCalReg, CntReg)
  begin  -- process EQUAL
    if RTCalReg > CntReg then
      RTCal_GRTH_TRCal <= '1';
    else
      RTCal_GRTH_TRCal <= '0';
    end if;
  end process GRTH1;
 
  GRTH2 : process (CntReg, RTCaldiv2Reg)
  begin  -- process EQUAL
    if CntReg > RTCaldiv2Reg then
      Symb_GRTH_RTCaldiv2 <= '1';
    else
      Symb_GRTH_RTCaldiv2 <= '0';
    end if;
  end process GRTH2;
 
  GRTH3 : process (CntReg, TARI4Reg)
  begin  -- process EQUAL
    if CntReg > TARI4Reg then
      Symb_GRTH_TARI4 <= '1';
    else
      Symb_GRTH_TARI4 <= '0';
    end if;
  end process GRTH3;
 
  DELIMITIER_COMPARISON : process (CntReg)
  begin  -- process DELIMITIER_COMPARISON
    if conv_integer(CntReg) > DELIMITIER_TIME_CK_CYC_MIN or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MIN then
      if conv_integer(CntReg) < DELIMITIER_TIME_CK_CYC_MAX or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MAX then
        DelimitierComparisoOK <= '1';
      else
        DelimitierComparisoOK <= '0';
      end if;
    else
      DelimitierComparisoOK <= '0';
    end if;
  end process DELIMITIER_COMPARISON;
 
  RTCALR : process (clk, rst_n)
  begin  -- process RTCALREG
    if rst_n = '0' then                 -- asynchronous reset (active low)
      RTCalReg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if RTCalEn = '1' then
        RTCalReg <= CntReg;
      end if;
    end if;
  end process RTCALR;
 
  TRCALR : process (clk, rst_n)
  begin  -- process RTCALREG
    if rst_n = '0' then                 -- asynchronous reset (active low)
      TRCalReg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if TRCalEn = '1' then
        TRCalReg <= CntReg;
      end if;
    end if;
  end process TRCALR;
 
  TARI4R : process (clk, rst_n)
  begin  -- process TARI4R
    if rst_n = '0' then                 -- asynchronous reset (active low)
      TARI4Reg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if TARI4En = '1' then
        TARI4Reg <= CntReg(LOG2_10_TARI_CK_CYC-3 downto 0) & "00";  --Multiplied by 4
      end if;
    end if;
  end process TARI4R;
 
  COUNTERCLR_1 : COUNTERCLR
    generic map (
      width => LOG2_10_TARI_CK_CYC)
    port map (
      clk    => clk,
      rst_n  => rst_n,
      en     => CntEn,
      clear  => CntClr,
      outcnt => CntReg);
 
end symbdec1;

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Subversion Repositories epc_rfid_transponder

[/] [epc_rfid_transponder/] [trunk/] [symbdec.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	erwing	`-------------------------------------------------------------------------------`
2			`-------------------------------------------------------------------------------`
3			`--`
4			`-- Title : EPC Class1 Gen2 RFID Tag - Symbol Decoder`
5			`--`
6			`-- File name : symbdec.vhd`
7			`--`
8			`-- Description : Tag symbol decoder detects valid frames decoding command`
9			`-- preambles and frame-syncs.`
10			`--`
11	3	erwing	`-- Authors : Erwing R. Sanchez <erwing.sanchezs@polito.it>`
12	2	erwing	`--`
13			`-------------------------------------------------------------------------------`
14			`-------------------------------------------------------------------------------`
15
16			`library IEEE;`
17			`use IEEE.STD_LOGIC_1164.all;`
18			`use IEEE.std_logic_unsigned.all;`
19			`use IEEE.STD_LOGIC_ARITH.all;`
20			`use ieee.numeric_std.all;`
21			`library work;`
22			`use work.epc_tag.all;`
23
24
25			`entity SymbolDecoder is`
26			`generic (`
27			`LOG2_10_TARI_CK_CYC : integer := 9; -- Log2(clock cycles for 10 maximum TARI value) (def:`
28			`-- Log2(490) = 9 @TCk=520ns)`
29			`DELIMITIER_TIME_CK_CYC_MIN : integer := 22; -- Min Clock cycles for 12,5 us delimitier`
30			`DELIMITIER_TIME_CK_CYC_MAX : integer := 24); -- Max Clock cycles for 12,5 us delimitier`
31
32			`port (`
33			`clk : in std_logic;`
34			`rst_n : in std_logic;`
35			`tdi : in std_logic;`
36			`en : in std_logic;`
37			`start : in std_logic;`
38			`sserror : out std_logic;`
39			`ssovalid : out std_logic;`
40			`sso : out std_logic); -- serial symbol output`
41
42			`end SymbolDecoder;`
43
44
45			`architecture symbdec1 of SymbolDecoder is`
46
47			`component COUNTERCLR`
48			`generic (`
49			`width : integer);`
50			`port (`
51			`clk : in std_logic;`
52			`rst_n : in std_logic;`
53			`en : in std_logic;`
54			`clear : in std_logic;`
55			`outcnt : out std_logic_vector(width-1 downto 0));`
56			`end component;`
57
58			`type RecFSM_t is (st0_Start, st0b_Delimitier, st1_Dat0H, st2_Dat0L, st3_RTcalH, st4_RTcalL, st5_Sym0H, st6_Sym0L, st6b_Sym0L_TR, st7_SymH, st8_SymL, st9_SymH_TR, st10_SymL_TR);`
59
60			`signal StRec, NextStRec : RecFSM_t;`
61			`signal CntEn, CntClr : std_logic;`
62			`signal CntEn_i, CntClr_i : std_logic;`
63			`signal TRCalEn, RTCalEn : std_logic;`
64			`signal TRCalEn_i, RTCalEn_i : std_logic;`
65			`signal TARI4En, TARI4En_i : std_logic;`
66			`signal CntReg, RTCalReg, TRCalReg : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);`
67			`signal RTCaldiv2Reg, TARI4Reg : std_logic_vector(LOG2_10_TARI_CK_CYC-1 downto 0);`
68			`signal RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2 : std_logic;`
69			`signal Symb_GRTH_TARI4 : std_logic;`
70			`signal ssovalid_i, sso_i, sserror_i : std_logic;`
71			`signal DelimitierComparisoOK : std_logic;`
72
73			`begin -- Receiver1`
74
75			`RTCaldiv2Reg <= '0' & RTCalReg(LOG2_10_TARI_CK_CYC-1 downto 1);`
76
77			`SYNCRO : process(clk, rst_n)`
78			`begin -- process`
79			`if clk'event and clk = '1' then`
80			`if rst_n = '0' then`
81			`CntEn <= '0';`
82			`TRCalEn <= '0';`
83			`RTCalEn <= '0';`
84			`TARI4En <= '0';`
85			`sserror <= '0';`
86			`ssovalid <= '0';`
87			`sso <= '0';`
88			`StRec <= st0_start;`
89			`else`
90			`if en = '1' then`
91			`StRec <= NextStRec;`
92			`CntEn <= CntEn_i;`
93			`TRCalEn <= TRCalEn_i;`
94			`RTCalEn <= RTCalEn_i;`
95			`TARI4En <= TARI4En_i;`
96			`CntClr <= CntClr_i;`
97			`sserror <= sserror_i;`
98			`ssovalid <= ssovalid_i;`
99			`sso <= sso_i;`
100			`end if;`
101			`end if;`
102			`end if;`
103			`end process;`
104
105
106			`NEXT_ST : process (StRec, tdi, start, TRCalEn, Symb_GRTH_TARI4, DelimitierComparisoOK)`
107			`begin -- process NEXT_ST`
108			`NextStRec <= StRec;`
109			`case StRec is`
110			`when st0_Start =>`
111			`if tdi = '0' then`
112			`NextStRec <= st0b_Delimitier;`
113			`end if;`
114			`when st0b_Delimitier =>`
115			`if tdi = '1' then`
116			`if DelimitierComparisoOK = '1' then`
117			`NextStRec <= st1_Dat0H;`
118			`else`
119			`NextStRec <= st0_Start;`
120			`end if;`
121			`end if;`
122			`when st1_Dat0H =>`
123			`if tdi = '0' then`
124			`NextStRec <= st2_Dat0L;`
125			`end if;`
126			`when st2_Dat0L =>`
127			`if tdi = '1' then`
128			`NextStRec <= st3_RTcalH;`
129			`end if;`
130			`when st3_RTcalH =>`
131			`if tdi = '0' then`
132			`NextStRec <= st4_RTcalL;`
133			`end if;`
134			`when st4_RTcalL =>`
135			`if tdi = '1' then`
136			`NextStRec <= st5_Sym0H;`
137			`end if;`
138			`when st5_Sym0H =>`
139			`if tdi = '0' then`
140			`NextStRec <= st6_Sym0L;`
141			`end if;`
142			`when st6_Sym0L =>`
143			`if TRCalEn = '1' then`
144			`NextStRec <= st6b_Sym0L_TR;`
145			`elsif tdi = '1' then`
146			`NextStRec <= st7_SymH;`
147			`end if;`
148			`when st6b_Sym0L_TR =>`
149			`if tdi = '1' then`
150			`NextStRec <= st9_SymH_TR;`
151			`end if;`
152			`when st9_SymH_TR =>`
153			`if tdi = '0' then`
154			`NextStRec <= st10_SymL_TR;`
155			`end if;`
156			`when st10_SymL_TR =>`
157			`if tdi = '1' then`
158			`NextStRec <= st7_SymH;`
159			`end if;`
160			`when st7_SymH =>`
161			`if Symb_GRTH_TARI4 = '1' then`
162			`NextStRec <= st0_Start;`
163			`elsif start = '1'then`
164			`NextStRec <= st0_Start;`
165			`elsif tdi = '0' then`
166			`NextStRec <= st8_SymL;`
167			`end if;`
168			`when st8_SymL =>`
169			`if Symb_GRTH_TARI4 = '1' then`
170			`NextStRec <= st0_Start;`
171			`elsif start = '1' then`
172			`NextStRec <= st0_Start;`
173			`elsif tdi = '1' then`
174			`NextStRec <= st7_SymH;`
175			`end if;`
176			`when others =>`
177			`NextStRec <= st0_start;`
178			`end case;`
179			`end process NEXT_ST;`
180
181
182			`OUTPUT_DEC : process (StRec, tdi, RTCal_GRTH_TRCal, Symb_GRTH_RTCaldiv2, Symb_GRTH_TARI4)`
183			`begin -- process OUTPUT_DEC`
184			`CntEn_i <= '0';`
185			`TRCalEn_i <= '0';`
186			`RTCalEn_i <= '0';`
187			`TARI4En_i <= '0';`
188			`CntClr_i <= '0';`
189			`sserror_i <= '0';`
190			`ssovalid_i <= '0';`
191			`sso_i <= '0';`
192
193			`case StRec is`
194			`when st0_Start =>`
195			`CntClr_i <= '1';`
196			`when st0b_Delimitier =>`
197			`if tdi = '0' then`
198			`CntEn_i <= '1';`
199			`else`
200			`CntClr_i <= '1';`
201			`end if;`
202			`when st1_Dat0H =>`
203			`CntEn_i <= '1';`
204			`when st2_Dat0L =>`
205			`if tdi = '0' then`
206			`CntEn_i <= '1';`
207			`else`
208			`CntClr_i <= '1';`
209			`TARI4En_i <= '1';`
210			`end if;`
211			`when st3_RTcalH =>`
212			`if tdi = '1' then`
213			`CntEn_i <= '1';`
214			`else`
215			`-- Load RTCal value`
216			`CntClr_i <= '1';`
217			`RTCalEn_i <= '1';`
218			`end if;`
219			`when st4_RTcalL =>`
220			`if tdi = '1' then`
221			`CntEn_i <= '1';`
222			`end if;`
223			`when st5_Sym0H =>`
224			`if tdi = '1' then`
225			`CntEn_i <= '1';`
226			`else`
227			`CntClr_i <= '1';`
228			`if RTCal_GRTH_TRCal = '1' then`
229			`-- Send valid Symbol`
230			`ssovalid_i <= '1';`
231			`if Symb_GRTH_RTCaldiv2 = '1' then`
232			`sso_i <= '1';`
233			`else`
234			`sso_i <= '0';`
235			`end if;`
236			`else`
237			`-- Load TRCal value (Preamble detected ("Query" comm.))`
238			`TRCalEn_i <= '1';`
239			`end if;`
240			`end if;`
241			`when st6_Sym0L =>`
242			`if tdi = '1' then`
243			`CntEn_i <= '1';`
244			`end if;`
245			`when st6b_Sym0L_TR =>`
246			`if tdi = '1' then`
247			`CntEn_i <= '1';`
248			`end if;`
249			`when st7_SymH =>`
250			`if Symb_GRTH_TARI4 = '1' then`
251			`sserror_i <= '1';`
252			`elsif tdi = '1' then`
253			`CntEn_i <= '1';`
254			`else`
255			`-- Send valid Symbol`
256			`-- CntClr_i <= '1';`
257			`ssovalid_i <= '1';`
258			`if Symb_GRTH_RTCaldiv2 = '1' then`
259			`sso_i <= '1';`
260			`else`
261			`sso_i <= '0';`
262			`end if;`
263			`end if;`
264			`when st8_SymL =>`
265			`if Symb_GRTH_TARI4 = '1' then`
266			`sserror_i <= '1';`
267			`elsif tdi = '1' then`
268			`CntClr_i <= '1';`
269			`end if;`
270			`when st9_SymH_TR =>`
271			`if tdi = '1' then`
272			`CntEn_i <= '1';`
273			`else`
274			`-- Send valid Symbol`
275			`CntClr_i <= '1';`
276			`ssovalid_i <= '1';`
277			`if Symb_GRTH_RTCaldiv2 = '1' then`
278			`sso_i <= '1';`
279			`else`
280			`sso_i <= '0';`
281			`end if;`
282			`end if;`
283			`when st10_SymL_TR =>`
284			`if tdi = '1' then`
285			`CntEn_i <= '1';`
286			`end if;`
287			`when others => null;`
288			`end case;`
289			`end process OUTPUT_DEC;`
290
291
292			`GRTH1 : process (RTCalReg, CntReg)`
293			`begin -- process EQUAL`
294			`if RTCalReg > CntReg then`
295			`RTCal_GRTH_TRCal <= '1';`
296			`else`
297			`RTCal_GRTH_TRCal <= '0';`
298			`end if;`
299			`end process GRTH1;`
300
301			`GRTH2 : process (CntReg, RTCaldiv2Reg)`
302			`begin -- process EQUAL`
303			`if CntReg > RTCaldiv2Reg then`
304			`Symb_GRTH_RTCaldiv2 <= '1';`
305			`else`
306			`Symb_GRTH_RTCaldiv2 <= '0';`
307			`end if;`
308			`end process GRTH2;`
309
310			`GRTH3 : process (CntReg, TARI4Reg)`
311			`begin -- process EQUAL`
312			`if CntReg > TARI4Reg then`
313			`Symb_GRTH_TARI4 <= '1';`
314			`else`
315			`Symb_GRTH_TARI4 <= '0';`
316			`end if;`
317			`end process GRTH3;`
318
319			`DELIMITIER_COMPARISON : process (CntReg)`
320			`begin -- process DELIMITIER_COMPARISON`
321			`if conv_integer(CntReg) > DELIMITIER_TIME_CK_CYC_MIN or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MIN then`
322			`if conv_integer(CntReg) < DELIMITIER_TIME_CK_CYC_MAX or conv_integer(CntReg) = DELIMITIER_TIME_CK_CYC_MAX then`
323			`DelimitierComparisoOK <= '1';`
324			`else`
325			`DelimitierComparisoOK <= '0';`
326			`end if;`
327			`else`
328			`DelimitierComparisoOK <= '0';`
329			`end if;`
330			`end process DELIMITIER_COMPARISON;`
331
332			`RTCALR : process (clk, rst_n)`
333			`begin -- process RTCALREG`
334			`if rst_n = '0' then -- asynchronous reset (active low)`
335			`RTCalReg <= (others => '0');`
336			`elsif clk'event and clk = '1' then -- rising clock edge`
337			`if RTCalEn = '1' then`
338			`RTCalReg <= CntReg;`
339			`end if;`
340			`end if;`
341			`end process RTCALR;`
342
343			`TRCALR : process (clk, rst_n)`
344			`begin -- process RTCALREG`
345			`if rst_n = '0' then -- asynchronous reset (active low)`
346			`TRCalReg <= (others => '0');`
347			`elsif clk'event and clk = '1' then -- rising clock edge`
348			`if TRCalEn = '1' then`
349			`TRCalReg <= CntReg;`
350			`end if;`
351			`end if;`
352			`end process TRCALR;`
353
354			`TARI4R : process (clk, rst_n)`
355			`begin -- process TARI4R`
356			`if rst_n = '0' then -- asynchronous reset (active low)`
357			`TARI4Reg <= (others => '0');`
358			`elsif clk'event and clk = '1' then -- rising clock edge`
359			`if TARI4En = '1' then`
360			`TARI4Reg <= CntReg(LOG2_10_TARI_CK_CYC-3 downto 0) & "00"; --Multiplied by 4`
361			`end if;`
362			`end if;`
363			`end process TARI4R;`
364
365			`COUNTERCLR_1 : COUNTERCLR`
366			`generic map (`
367			`width => LOG2_10_TARI_CK_CYC)`
368			`port map (`
369			`clk => clk,`
370			`rst_n => rst_n,`
371			`en => CntEn,`
372			`clear => CntClr,`
373			`outcnt => CntReg);`
374
375			`end symbdec1;`