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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [model/] [altera_ethmodels_pack.vhd] - Blame information for rev 42

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1 42 lmaarsen
-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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--
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-- Revision Control Information
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--
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-- $RCSfile: altera_ethmodels_pack.vhd,v $
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-- $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/vhdl/ethernet_model/package/altera_ethmodels_pack.vhd,v $
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--
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-- $Revision: #1 $
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-- $Date: 2008/08/09 $
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-- Check in by : $Author: sc-build $
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-- Author      : SKNg/TTChong
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--
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-- Project     : Triple Speed Ethernet - 10/100/1000 MAC
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--
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-- Description : (Simulation only)
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--
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-- Package defining components and features of Ethernet Models
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--
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-- 
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all ;
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use std.textio.all ;
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package altera_ethmodels_pack is
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    constant GENCNTMODULO  : integer := 256;    -- modulo used for the start counter
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                                                -- (informative, not for change)
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    -- --------------------------------------
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    -- Procedures to help generation Messages
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    -- --------------------------------------
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    -- convert vector to HEX digits (assumes multiples of nibbles (4-bit) )
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    --
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    procedure WRITE_HEX(L : inout LINE; val : in std_logic_vector );
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    -- write timestamp and message
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    --
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    procedure WRITETM(L: inout LINE; theMessage : in string );
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    -- write to logfile and to stdout
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    --
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    procedure WRITELINE_LOG( file theLog: TEXT; L: inout LINE );
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end altera_ethmodels_pack;
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package body altera_ethmodels_pack is
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    --
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    -- Convert vector to hex digit (assumes 4-bit nibbles)
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    --
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    procedure WRITE_HEX(L: inout LINE; val: in std_logic_vector ) is
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        variable i, ix : integer;
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        variable nib   : integer;
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        begin
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            for i in ((val'left)+1)/4 downto 1 loop  -- start with MSNibble
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                ix := i*4;
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                nib := conv_integer( '0' & val( ix-1 downto ix-4 ) ); -- convert to unsigned always
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                if( nib < 10 ) then
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                    write( L, character'val(character'pos('0') + nib));
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                else
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                    write( L, character'val(character'pos('a') + nib-10 ));
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                end if;
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            end loop;
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        end;
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    --
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    -- Write line in logfile and stdout with time stamp
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    --
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    procedure WRITETM( L: inout LINE; theMessage: in string  ) is
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        variable ln: line;
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        begin
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            write(L, string'("Time: "));
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            write(L, NOW, RIGHT, 10 );
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            write(L, string'(" - "));
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            write(L, theMessage );
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        end;
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    -- write line in logfile and to output
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    --
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    procedure WRITELINE_LOG( file theLog: TEXT; L: inout LINE ) is
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        variable ln1 : line;
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        variable ln2 : line;
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        variable tmp : string(1 to L'length);
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        begin
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                -- copy the string in two destinations as writeline deallocates them
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               read(L, tmp);
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               write( ln1, tmp);
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               write( ln2, tmp);
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               writeline( theLog, ln1);
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               writeline( OUTPUT, ln2);
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        end;
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end; -- body        
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