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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_interface.vhd] - Blame information for rev 42

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--------------------------------------------------------------------------------
----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_port_interface
-- Last modified : Mon Apr 14 12:51:18 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_port_interface is
  generic(
    esoc_port_nr : integer := 0);
  port(
    clk_control          : in     std_logic;
    clk_rgmii_125m       : in     STD_LOGIC;
    clk_rgmii_25m        : in     STD_LOGIC;
    clk_rgmii_2m5        : in     STD_LOGIC;
    ctrl_address         : in     std_logic_vector(15 downto 0);
    ctrl_rd              : in     std_logic := '0';
    ctrl_rddata          : out    std_logic_vector(31 downto 0);
    ctrl_wait            : out    std_logic;
    ctrl_wr              : in     std_logic;
    ctrl_wrdata          : in     std_logic_vector(31 downto 0);
    inbound_data         : out    std_logic_vector(31 downto 0);
    inbound_data_full    : in     std_logic;
    inbound_data_write   : out    std_logic;
    inbound_header       : out    std_logic_vector(111 downto 0);
    inbound_header_write : out    std_logic;
    inbound_info         : out    std_logic_vector(31 downto 0);
    inbound_info_write   : out    std_logic;
    mac_mdc              : out    std_logic;
    mac_mdio             : inout  std_logic;
    outbound_data        : in     std_logic_vector(31 downto 0);
    outbound_data_read   : out    std_logic;
    outbound_info        : in     std_logic_vector(15 downto 0);
    outbound_info_empty  : in     std_logic;
    outbound_info_read   : out    std_logic;
    reset                : in     std_logic;
    rgmii_rxc            : in     std_logic;
    rgmii_rxctl          : in     std_logic;
    rgmii_rxd            : in     std_logic_vector(3 downto 0);
    rgmii_txc            : out    std_logic;
    rgmii_txctl          : out    std_logic;
    rgmii_txd            : out    std_logic_vector(3 downto 0));
end entity esoc_port_interface;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_port_interface.structure
-- Last modified : Mon Apr 14 12:51:18 2014.
--------------------------------------------------------------------------------
 
architecture structure of esoc_port_interface is
 
  signal ctrl_bus_enable : STD_LOGIC;
  signal clk_rgmii       : STD_LOGIC;
  signal mac_rd          : STD_LOGIC;
  signal mac_address     : STD_LOGIC_VECTOR(7 downto 0);
  signal mdc             : STD_LOGIC;
  signal mdio_out        : STD_LOGIC;
  signal mdio_in         : STD_LOGIC;
  signal mdio_oen        : STD_LOGIC;
  signal mac_wait        : STD_LOGIC;
  signal mac_rddata      : STD_LOGIC_VECTOR(31 downto 0);
  signal mac_wrdata      : STD_LOGIC_VECTOR(31 downto 0);
  signal mac_wr          : STD_LOGIC;
  signal xon_gen         : STD_LOGIC;
  signal xoff_gen        : STD_LOGIC;
  signal magic_wakeup    : STD_LOGIC;
  signal magic_sleep_n   : STD_LOGIC := '1';
  signal set_1000        : STD_LOGIC := '0';
  signal set_10          : STD_LOGIC := '0'; -- '0'
  signal eth_mode        : STD_LOGIC;
  signal ena_10          : STD_LOGIC;
  signal ff_tx_sop       : STD_LOGIC;
  signal ff_tx_eop       : STD_LOGIC;
  signal ff_tx_rdy       : STD_LOGIC;
  signal ff_tx_wren      : STD_LOGIC;
  signal ff_tx_data      : STD_LOGIC_VECTOR(31 downto 0);
  signal ff_tx_mod       : STD_LOGIC_VECTOR(1 downto 0);
  signal ff_tx_err       : STD_LOGIC;
  signal ff_tx_crc_fwd   : STD_LOGIC;
  signal tx_ff_uflow     : STD_LOGIC;
  signal ff_tx_a_full    : STD_LOGIC;
  signal ff_tx_a_empty   : STD_LOGIC;
  signal ff_tx_septy     : STD_LOGIC;
  signal ff_rx_sop       : STD_LOGIC;
  signal ff_rx_eop       : STD_LOGIC;
  signal ff_rx_rdy       : STD_LOGIC;
  signal ff_rx_dval      : STD_LOGIC;
  signal ff_rx_data      : STD_LOGIC_VECTOR(31 downto 0);
  signal ff_rx_mod       : STD_LOGIC_VECTOR(1 downto 0);
  signal rx_frm_type     : STD_LOGIC_VECTOR(3 downto 0);
  signal ff_rx_dsav      : STD_LOGIC;
  signal rx_err_stat     : STD_LOGIC_VECTOR(17 downto 0);
  signal ff_rx_a_full    : STD_LOGIC;
  signal ff_rx_a_empty   : STD_LOGIC;
 
  component esoc_port_mal
    generic(
      esoc_port_nr : integer := 0);
    port(
      clk_control          : in     STD_LOGIC;
      clk_rgmii            : out    std_logic;
      clk_rgmii_125m       : in     std_logic;
      clk_rgmii_25m        : in     std_logic;
      clk_rgmii_2m5        : in     std_logic;
      ctrl_address         : in     std_logic_vector(15 downto 0);
      ctrl_rd              : in     std_logic := '0';
      ctrl_rddata          : out    std_logic_vector(31 downto 0);
      ctrl_wait            : out    std_logic;
      ctrl_wr              : in     std_logic;
      ctrl_wrdata          : in     std_logic_vector(31 downto 0);
      ena_10               : in     STD_LOGIC;
      eth_mode             : in     STD_LOGIC;
      ff_rx_a_empty        : in     STD_LOGIC;
      ff_rx_a_full         : in     STD_LOGIC;
      ff_rx_data           : in     STD_LOGIC_VECTOR(31 downto 0);
      ff_rx_dsav           : in     STD_LOGIC;
      ff_rx_dval           : in     STD_LOGIC;
      ff_rx_eop            : in     STD_LOGIC;
      ff_rx_mod            : in     STD_LOGIC_VECTOR(1 downto 0);
      ff_rx_rdy            : out    STD_LOGIC;
      ff_rx_sop            : in     STD_LOGIC;
      ff_tx_a_empty        : in     STD_LOGIC;
      ff_tx_a_full         : in     STD_LOGIC;
      ff_tx_crc_fwd        : out    STD_LOGIC;
      ff_tx_data           : out    STD_LOGIC_VECTOR(31 downto 0);
      ff_tx_eop            : out    STD_LOGIC;
      ff_tx_err            : out    STD_LOGIC;
      ff_tx_mod            : out    STD_LOGIC_VECTOR(1 downto 0);
      ff_tx_rdy            : in     STD_LOGIC;
      ff_tx_septy          : in     STD_LOGIC;
      ff_tx_sop            : out    STD_LOGIC;
      ff_tx_wren           : out    STD_LOGIC;
      inbound_data         : out    std_logic_vector(31 downto 0);
      inbound_data_full    : in     std_logic;
      inbound_data_write   : out    std_logic;
      inbound_header       : out    std_logic_vector(111 downto 0);
      inbound_header_write : out    std_logic;
      inbound_info         : out    std_logic_vector(31 downto 0);
      inbound_info_write   : out    std_logic;
      magic_sleep_n        : out    STD_LOGIC := '1';
      magic_wakeup         : in     STD_LOGIC;
      outbound_data        : in     std_logic_vector(31 downto 0);
      outbound_data_read   : out    std_logic;
      outbound_info        : in     std_logic_vector(15 downto 0);
      outbound_info_empty  : in     std_logic;
      outbound_info_read   : out    std_logic;
      reset                : in     STD_LOGIC;
      rx_err_stat          : in     STD_LOGIC_VECTOR(17 downto 0);
      rx_frm_type          : in     STD_LOGIC_VECTOR(3 downto 0);
      set_10               : out    STD_LOGIC := '0'; -- '0'
      set_1000             : out    STD_LOGIC := '0';
      tx_ff_uflow          : in     STD_LOGIC;
      xoff_gen             : out    STD_LOGIC;
      xon_gen              : out    STD_LOGIC);
  end component esoc_port_mal;
 
  component esoc_port_mac
    port(
      ff_tx_crc_fwd : in     STD_LOGIC;
      ff_tx_data    : in     STD_LOGIC_VECTOR(31 downto 0);
      ff_tx_eop     : in     STD_LOGIC;
      ff_tx_err     : in     STD_LOGIC;
      ff_tx_mod     : in     STD_LOGIC_VECTOR(1 downto 0);
      ff_tx_sop     : in     STD_LOGIC;
      ff_tx_wren    : in     STD_LOGIC;
      ff_tx_clk     : in     STD_LOGIC;
      ff_rx_rdy     : in     STD_LOGIC;
      ff_rx_clk     : in     STD_LOGIC;
      address       : in     STD_LOGIC_VECTOR(7 downto 0);
      read          : in     STD_LOGIC;
      writedata     : in     STD_LOGIC_VECTOR(31 downto 0);
      write         : in     STD_LOGIC;
      clk           : in     STD_LOGIC;
      reset         : in     STD_LOGIC;
      rgmii_in      : in     STD_LOGIC_VECTOR(3 downto 0);
      rx_control    : in     STD_LOGIC;
      tx_clk        : in     STD_LOGIC;
      rx_clk        : in     STD_LOGIC;
      set_10        : in     STD_LOGIC;
      set_1000      : in     STD_LOGIC;
      xon_gen       : in     STD_LOGIC;
      xoff_gen      : in     STD_LOGIC;
      magic_sleep_n : in     STD_LOGIC;
      mdio_in       : in     STD_LOGIC;
      ff_tx_rdy     : out    STD_LOGIC;
      ff_rx_data    : out    STD_LOGIC_VECTOR(31 downto 0);
      ff_rx_dval    : out    STD_LOGIC;
      ff_rx_eop     : out    STD_LOGIC;
      ff_rx_mod     : out    STD_LOGIC_VECTOR(1 downto 0);
      ff_rx_sop     : out    STD_LOGIC;
      rx_err        : out    STD_LOGIC_VECTOR(5 downto 0);
      rx_err_stat   : out    STD_LOGIC_VECTOR(17 downto 0);
      rx_frm_type   : out    STD_LOGIC_VECTOR(3 downto 0);
      ff_rx_dsav    : out    STD_LOGIC;
      readdata      : out    STD_LOGIC_VECTOR(31 downto 0);
      waitrequest   : out    STD_LOGIC;
      rgmii_out     : out    STD_LOGIC_VECTOR(3 downto 0);
      tx_control    : out    STD_LOGIC;
      ena_10        : out    STD_LOGIC;
      eth_mode      : out    STD_LOGIC;
      ff_tx_septy   : out    STD_LOGIC;
      tx_ff_uflow   : out    STD_LOGIC;
      ff_rx_a_full  : out    STD_LOGIC;
      ff_rx_a_empty : out    STD_LOGIC;
      ff_tx_a_full  : out    STD_LOGIC;
      ff_tx_a_empty : out    STD_LOGIC;
      magic_wakeup  : out    STD_LOGIC;
      mdio_out      : out    STD_LOGIC;
      mdio_oen      : out    STD_LOGIC;
      mdc           : out    STD_LOGIC);
  end component esoc_port_mac;
 
begin
  rgmii_txc <= clk_rgmii;
  u1: esoc_port_mal
    generic map(
      esoc_port_nr => esoc_port_nr)
    port map(
      clk_control          => clk_control,
      clk_rgmii            => clk_rgmii,
      clk_rgmii_125m       => clk_rgmii_125m,
      clk_rgmii_25m        => clk_rgmii_25m,
      clk_rgmii_2m5        => clk_rgmii_2m5,
      ctrl_address         => ctrl_address,
      ctrl_rd              => ctrl_rd,
      ctrl_rddata          => ctrl_rddata,
      ctrl_wait            => ctrl_wait,
      ctrl_wr              => ctrl_wr,
      ctrl_wrdata          => ctrl_wrdata,
      ena_10               => ena_10,
      eth_mode             => eth_mode,
      ff_rx_a_empty        => ff_rx_a_empty,
      ff_rx_a_full         => ff_rx_a_full,
      ff_rx_data           => ff_rx_data,
      ff_rx_dsav           => ff_rx_dsav,
      ff_rx_dval           => ff_rx_dval,
      ff_rx_eop            => ff_rx_eop,
      ff_rx_mod            => ff_rx_mod,
      ff_rx_rdy            => ff_rx_rdy,
      ff_rx_sop            => ff_rx_sop,
      ff_tx_a_empty        => ff_tx_a_empty,
      ff_tx_a_full         => ff_tx_a_full,
      ff_tx_crc_fwd        => ff_tx_crc_fwd,
      ff_tx_data           => ff_tx_data,
      ff_tx_eop            => ff_tx_eop,
      ff_tx_err            => ff_tx_err,
      ff_tx_mod            => ff_tx_mod,
      ff_tx_rdy            => ff_tx_rdy,
      ff_tx_septy          => ff_tx_septy,
      ff_tx_sop            => ff_tx_sop,
      ff_tx_wren           => ff_tx_wren,
      inbound_data         => inbound_data,
      inbound_data_full    => inbound_data_full,
      inbound_data_write   => inbound_data_write,
      inbound_header       => inbound_header,
      inbound_header_write => inbound_header_write,
      inbound_info         => inbound_info,
      inbound_info_write   => inbound_info_write,
      magic_sleep_n        => magic_sleep_n,
      magic_wakeup         => magic_wakeup,
      outbound_data        => outbound_data,
      outbound_data_read   => outbound_data_read,
      outbound_info        => outbound_info,
      outbound_info_empty  => outbound_info_empty,
      outbound_info_read   => outbound_info_read,
      reset                => reset,
      rx_err_stat          => rx_err_stat,
      rx_frm_type          => rx_frm_type,
      set_10               => set_10,
      set_1000             => set_1000,
      tx_ff_uflow          => tx_ff_uflow,
      xoff_gen             => xoff_gen,
      xon_gen              => xon_gen);
 
  u0: esoc_port_mac
    port map(
      ff_tx_crc_fwd => ff_tx_crc_fwd,
      ff_tx_data    => ff_tx_data,
      ff_tx_eop     => ff_tx_eop,
      ff_tx_err     => ff_tx_err,
      ff_tx_mod     => ff_tx_mod,
      ff_tx_sop     => ff_tx_sop,
      ff_tx_wren    => ff_tx_wren,
      ff_tx_clk     => clk_control,
      ff_rx_rdy     => ff_rx_rdy,
      ff_rx_clk     => clk_control,
      address       => mac_address,
      read          => mac_rd,
      writedata     => mac_wrdata,
      write         => mac_wr,
      clk           => clk_control,
      reset         => reset,
      rgmii_in      => rgmii_rxd,
      rx_control    => rgmii_rxctl,
      tx_clk        => clk_rgmii,
      rx_clk        => rgmii_rxc,
      set_10        => set_10,
      set_1000      => set_1000,
      xon_gen       => xon_gen,
      xoff_gen      => xoff_gen,
      magic_sleep_n => magic_sleep_n,
      mdio_in       => mdio_in,
      ff_tx_rdy     => ff_tx_rdy,
      ff_rx_data    => ff_rx_data,
      ff_rx_dval    => ff_rx_dval,
      ff_rx_eop     => ff_rx_eop,
      ff_rx_mod     => ff_rx_mod,
      ff_rx_sop     => ff_rx_sop,
      rx_err        => open,
      rx_err_stat   => rx_err_stat,
      rx_frm_type   => rx_frm_type,
      ff_rx_dsav    => ff_rx_dsav,
      readdata      => mac_rddata,
      waitrequest   => mac_wait,
      rgmii_out     => rgmii_txd,
      tx_control    => rgmii_txctl,
      ena_10        => ena_10,
      eth_mode      => eth_mode,
      ff_tx_septy   => ff_tx_septy,
      tx_ff_uflow   => tx_ff_uflow,
      ff_rx_a_full  => ff_rx_a_full,
      ff_rx_a_empty => ff_rx_a_empty,
      ff_tx_a_full  => ff_tx_a_full,
      ff_tx_a_empty => ff_tx_a_empty,
      magic_wakeup  => magic_wakeup,
      mdio_out      => mdio_out,
      mdio_oen      => mdio_oen,
      mdc           => mdc);
 
 
  mac_mdc   <= mdc;
  mac_mdio  <= mdio_out when mdio_oen = '0' else 'Z';
  mdio_in   <= mac_mdio when mdio_oen = '1'  else '0';
 
 
  mac_address   <= ctrl_address(mac_address'high downto 0);
 
  mac_wrdata    <= ctrl_wrdata;
 
  mac_wr        <= ctrl_wr when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  mac_rd        <= ctrl_rd when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  ctrl_bus_enable <= '1' when to_integer(unsigned(ctrl_address))   >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and
                                to_integer(unsigned(ctrl_address)) <  esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size
                                else '0';
 
  ctrl_wait     <= mac_wait when ctrl_bus_enable = '1' else 'Z';
 
  ctrl_rddata   <= mac_rddata when ctrl_bus_enable = '1' else (others => 'Z');
end architecture structure ; -- of esoc_port_interface
 

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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_port_interface.vhd] - Blame information for rev 42

Line No.	Rev	Author	Line
1	42	lmaarsen	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- Ethernet Switch on Configurable Logic IP Core ----`
4			`---- ----`
5			`---- This file is part of the ESoCL project ----`
6			`---- http://www.opencores.org/cores/esoc/ ----`
7			`---- ----`
8			`---- Description: see design description ESoCL_dd_71022001.pdf ----`
9			`---- ----`
10			`---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----`
11			`---- and/or release bulleting ESoCL_rb_71022001.pdf ----`
12			`---- ----`
13			`---- Author(s): L.Maarsen ----`
14			`---- Bert Maarsen, lmaarsen@opencores.org ----`
15			`---- ----`
16			`--------------------------------------------------------------------------------`
17			`---- ----`
18			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
19			`---- ----`
20			`---- This source file may be used and distributed without ----`
21			`---- restriction provided that this copyright statement is not ----`
22			`---- removed from the file and that any derivative work contains ----`
23			`---- the original copyright notice and the associated disclaimer. ----`
24			`---- ----`
25			`---- This source file is free software; you can redistribute it ----`
26			`---- and/or modify it under the terms of the GNU Lesser General ----`
27			`---- Public License as published by the Free Software Foundation; ----`
28			`---- either version 2.1 of the License, or (at your option) any ----`
29			`---- later version. ----`
30			`---- ----`
31			`---- This source is distributed in the hope that it will be ----`
32			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
33			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
34			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
35			`---- details. ----`
36			`---- ----`
37			`---- You should have received a copy of the GNU Lesser General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.opencores.org/lgpl.shtml ----`
40			`---- ----`
41			`--------------------------------------------------------------------------------`
42			`-- Object : Entity work.esoc_port_interface`
43			`-- Last modified : Mon Apr 14 12:51:18 2014.`
44			`--------------------------------------------------------------------------------`
45
46
47
48			`library ieee, std, work;`
49			`use ieee.std_logic_1164.all;`
50			`use std.textio.all;`
51			`use ieee.numeric_std.all;`
52			`use work.package_esoc_configuration.all;`
53
54			`entity esoc_port_interface is`
55			`generic(`
56			`esoc_port_nr : integer := 0);`
57			`port(`
58			`clk_control : in std_logic;`
59			`clk_rgmii_125m : in STD_LOGIC;`
60			`clk_rgmii_25m : in STD_LOGIC;`
61			`clk_rgmii_2m5 : in STD_LOGIC;`
62			`ctrl_address : in std_logic_vector(15 downto 0);`
63			`ctrl_rd : in std_logic := '0';`
64			`ctrl_rddata : out std_logic_vector(31 downto 0);`
65			`ctrl_wait : out std_logic;`
66			`ctrl_wr : in std_logic;`
67			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
68			`inbound_data : out std_logic_vector(31 downto 0);`
69			`inbound_data_full : in std_logic;`
70			`inbound_data_write : out std_logic;`
71			`inbound_header : out std_logic_vector(111 downto 0);`
72			`inbound_header_write : out std_logic;`
73			`inbound_info : out std_logic_vector(31 downto 0);`
74			`inbound_info_write : out std_logic;`
75			`mac_mdc : out std_logic;`
76			`mac_mdio : inout std_logic;`
77			`outbound_data : in std_logic_vector(31 downto 0);`
78			`outbound_data_read : out std_logic;`
79			`outbound_info : in std_logic_vector(15 downto 0);`
80			`outbound_info_empty : in std_logic;`
81			`outbound_info_read : out std_logic;`
82			`reset : in std_logic;`
83			`rgmii_rxc : in std_logic;`
84			`rgmii_rxctl : in std_logic;`
85			`rgmii_rxd : in std_logic_vector(3 downto 0);`
86			`rgmii_txc : out std_logic;`
87			`rgmii_txctl : out std_logic;`
88			`rgmii_txd : out std_logic_vector(3 downto 0));`
89			`end entity esoc_port_interface;`
90
91			`--------------------------------------------------------------------------------`
92			`-- Object : Architecture work.esoc_port_interface.structure`
93			`-- Last modified : Mon Apr 14 12:51:18 2014.`
94			`--------------------------------------------------------------------------------`
95
96			`architecture structure of esoc_port_interface is`
97
98			`signal ctrl_bus_enable : STD_LOGIC;`
99			`signal clk_rgmii : STD_LOGIC;`
100			`signal mac_rd : STD_LOGIC;`
101			`signal mac_address : STD_LOGIC_VECTOR(7 downto 0);`
102			`signal mdc : STD_LOGIC;`
103			`signal mdio_out : STD_LOGIC;`
104			`signal mdio_in : STD_LOGIC;`
105			`signal mdio_oen : STD_LOGIC;`
106			`signal mac_wait : STD_LOGIC;`
107			`signal mac_rddata : STD_LOGIC_VECTOR(31 downto 0);`
108			`signal mac_wrdata : STD_LOGIC_VECTOR(31 downto 0);`
109			`signal mac_wr : STD_LOGIC;`
110			`signal xon_gen : STD_LOGIC;`
111			`signal xoff_gen : STD_LOGIC;`
112			`signal magic_wakeup : STD_LOGIC;`
113			`signal magic_sleep_n : STD_LOGIC := '1';`
114			`signal set_1000 : STD_LOGIC := '0';`
115			`signal set_10 : STD_LOGIC := '0'; -- '0'`
116			`signal eth_mode : STD_LOGIC;`
117			`signal ena_10 : STD_LOGIC;`
118			`signal ff_tx_sop : STD_LOGIC;`
119			`signal ff_tx_eop : STD_LOGIC;`
120			`signal ff_tx_rdy : STD_LOGIC;`
121			`signal ff_tx_wren : STD_LOGIC;`
122			`signal ff_tx_data : STD_LOGIC_VECTOR(31 downto 0);`
123			`signal ff_tx_mod : STD_LOGIC_VECTOR(1 downto 0);`
124			`signal ff_tx_err : STD_LOGIC;`
125			`signal ff_tx_crc_fwd : STD_LOGIC;`
126			`signal tx_ff_uflow : STD_LOGIC;`
127			`signal ff_tx_a_full : STD_LOGIC;`
128			`signal ff_tx_a_empty : STD_LOGIC;`
129			`signal ff_tx_septy : STD_LOGIC;`
130			`signal ff_rx_sop : STD_LOGIC;`
131			`signal ff_rx_eop : STD_LOGIC;`
132			`signal ff_rx_rdy : STD_LOGIC;`
133			`signal ff_rx_dval : STD_LOGIC;`
134			`signal ff_rx_data : STD_LOGIC_VECTOR(31 downto 0);`
135			`signal ff_rx_mod : STD_LOGIC_VECTOR(1 downto 0);`
136			`signal rx_frm_type : STD_LOGIC_VECTOR(3 downto 0);`
137			`signal ff_rx_dsav : STD_LOGIC;`
138			`signal rx_err_stat : STD_LOGIC_VECTOR(17 downto 0);`
139			`signal ff_rx_a_full : STD_LOGIC;`
140			`signal ff_rx_a_empty : STD_LOGIC;`
141
142			`component esoc_port_mal`
143			`generic(`
144			`esoc_port_nr : integer := 0);`
145			`port(`
146			`clk_control : in STD_LOGIC;`
147			`clk_rgmii : out std_logic;`
148			`clk_rgmii_125m : in std_logic;`
149			`clk_rgmii_25m : in std_logic;`
150			`clk_rgmii_2m5 : in std_logic;`
151			`ctrl_address : in std_logic_vector(15 downto 0);`
152			`ctrl_rd : in std_logic := '0';`
153			`ctrl_rddata : out std_logic_vector(31 downto 0);`
154			`ctrl_wait : out std_logic;`
155			`ctrl_wr : in std_logic;`
156			`ctrl_wrdata : in std_logic_vector(31 downto 0);`
157			`ena_10 : in STD_LOGIC;`
158			`eth_mode : in STD_LOGIC;`
159			`ff_rx_a_empty : in STD_LOGIC;`
160			`ff_rx_a_full : in STD_LOGIC;`
161			`ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);`
162			`ff_rx_dsav : in STD_LOGIC;`
163			`ff_rx_dval : in STD_LOGIC;`
164			`ff_rx_eop : in STD_LOGIC;`
165			`ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
166			`ff_rx_rdy : out STD_LOGIC;`
167			`ff_rx_sop : in STD_LOGIC;`
168			`ff_tx_a_empty : in STD_LOGIC;`
169			`ff_tx_a_full : in STD_LOGIC;`
170			`ff_tx_crc_fwd : out STD_LOGIC;`
171			`ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);`
172			`ff_tx_eop : out STD_LOGIC;`
173			`ff_tx_err : out STD_LOGIC;`
174			`ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
175			`ff_tx_rdy : in STD_LOGIC;`
176			`ff_tx_septy : in STD_LOGIC;`
177			`ff_tx_sop : out STD_LOGIC;`
178			`ff_tx_wren : out STD_LOGIC;`
179			`inbound_data : out std_logic_vector(31 downto 0);`
180			`inbound_data_full : in std_logic;`
181			`inbound_data_write : out std_logic;`
182			`inbound_header : out std_logic_vector(111 downto 0);`
183			`inbound_header_write : out std_logic;`
184			`inbound_info : out std_logic_vector(31 downto 0);`
185			`inbound_info_write : out std_logic;`
186			`magic_sleep_n : out STD_LOGIC := '1';`
187			`magic_wakeup : in STD_LOGIC;`
188			`outbound_data : in std_logic_vector(31 downto 0);`
189			`outbound_data_read : out std_logic;`
190			`outbound_info : in std_logic_vector(15 downto 0);`
191			`outbound_info_empty : in std_logic;`
192			`outbound_info_read : out std_logic;`
193			`reset : in STD_LOGIC;`
194			`rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);`
195			`rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0);`
196			`set_10 : out STD_LOGIC := '0'; -- '0'`
197			`set_1000 : out STD_LOGIC := '0';`
198			`tx_ff_uflow : in STD_LOGIC;`
199			`xoff_gen : out STD_LOGIC;`
200			`xon_gen : out STD_LOGIC);`
201			`end component esoc_port_mal;`
202
203			`component esoc_port_mac`
204			`port(`
205			`ff_tx_crc_fwd : in STD_LOGIC;`
206			`ff_tx_data : in STD_LOGIC_VECTOR(31 downto 0);`
207			`ff_tx_eop : in STD_LOGIC;`
208			`ff_tx_err : in STD_LOGIC;`
209			`ff_tx_mod : in STD_LOGIC_VECTOR(1 downto 0);`
210			`ff_tx_sop : in STD_LOGIC;`
211			`ff_tx_wren : in STD_LOGIC;`
212			`ff_tx_clk : in STD_LOGIC;`
213			`ff_rx_rdy : in STD_LOGIC;`
214			`ff_rx_clk : in STD_LOGIC;`
215			`address : in STD_LOGIC_VECTOR(7 downto 0);`
216			`read : in STD_LOGIC;`
217			`writedata : in STD_LOGIC_VECTOR(31 downto 0);`
218			`write : in STD_LOGIC;`
219			`clk : in STD_LOGIC;`
220			`reset : in STD_LOGIC;`
221			`rgmii_in : in STD_LOGIC_VECTOR(3 downto 0);`
222			`rx_control : in STD_LOGIC;`
223			`tx_clk : in STD_LOGIC;`
224			`rx_clk : in STD_LOGIC;`
225			`set_10 : in STD_LOGIC;`
226			`set_1000 : in STD_LOGIC;`
227			`xon_gen : in STD_LOGIC;`
228			`xoff_gen : in STD_LOGIC;`
229			`magic_sleep_n : in STD_LOGIC;`
230			`mdio_in : in STD_LOGIC;`
231			`ff_tx_rdy : out STD_LOGIC;`
232			`ff_rx_data : out STD_LOGIC_VECTOR(31 downto 0);`
233			`ff_rx_dval : out STD_LOGIC;`
234			`ff_rx_eop : out STD_LOGIC;`
235			`ff_rx_mod : out STD_LOGIC_VECTOR(1 downto 0);`
236			`ff_rx_sop : out STD_LOGIC;`
237			`rx_err : out STD_LOGIC_VECTOR(5 downto 0);`
238			`rx_err_stat : out STD_LOGIC_VECTOR(17 downto 0);`
239			`rx_frm_type : out STD_LOGIC_VECTOR(3 downto 0);`
240			`ff_rx_dsav : out STD_LOGIC;`
241			`readdata : out STD_LOGIC_VECTOR(31 downto 0);`
242			`waitrequest : out STD_LOGIC;`
243			`rgmii_out : out STD_LOGIC_VECTOR(3 downto 0);`
244			`tx_control : out STD_LOGIC;`
245			`ena_10 : out STD_LOGIC;`
246			`eth_mode : out STD_LOGIC;`
247			`ff_tx_septy : out STD_LOGIC;`
248			`tx_ff_uflow : out STD_LOGIC;`
249			`ff_rx_a_full : out STD_LOGIC;`
250			`ff_rx_a_empty : out STD_LOGIC;`
251			`ff_tx_a_full : out STD_LOGIC;`
252			`ff_tx_a_empty : out STD_LOGIC;`
253			`magic_wakeup : out STD_LOGIC;`
254			`mdio_out : out STD_LOGIC;`
255			`mdio_oen : out STD_LOGIC;`
256			`mdc : out STD_LOGIC);`
257			`end component esoc_port_mac;`
258
259			`begin`
260			`rgmii_txc <= clk_rgmii;`
261			`u1: esoc_port_mal`
262			`generic map(`
263			`esoc_port_nr => esoc_port_nr)`
264			`port map(`
265			`clk_control => clk_control,`
266			`clk_rgmii => clk_rgmii,`
267			`clk_rgmii_125m => clk_rgmii_125m,`
268			`clk_rgmii_25m => clk_rgmii_25m,`
269			`clk_rgmii_2m5 => clk_rgmii_2m5,`
270			`ctrl_address => ctrl_address,`
271			`ctrl_rd => ctrl_rd,`
272			`ctrl_rddata => ctrl_rddata,`
273			`ctrl_wait => ctrl_wait,`
274			`ctrl_wr => ctrl_wr,`
275			`ctrl_wrdata => ctrl_wrdata,`
276			`ena_10 => ena_10,`
277			`eth_mode => eth_mode,`
278			`ff_rx_a_empty => ff_rx_a_empty,`
279			`ff_rx_a_full => ff_rx_a_full,`
280			`ff_rx_data => ff_rx_data,`
281			`ff_rx_dsav => ff_rx_dsav,`
282			`ff_rx_dval => ff_rx_dval,`
283			`ff_rx_eop => ff_rx_eop,`
284			`ff_rx_mod => ff_rx_mod,`
285			`ff_rx_rdy => ff_rx_rdy,`
286			`ff_rx_sop => ff_rx_sop,`
287			`ff_tx_a_empty => ff_tx_a_empty,`
288			`ff_tx_a_full => ff_tx_a_full,`
289			`ff_tx_crc_fwd => ff_tx_crc_fwd,`
290			`ff_tx_data => ff_tx_data,`
291			`ff_tx_eop => ff_tx_eop,`
292			`ff_tx_err => ff_tx_err,`
293			`ff_tx_mod => ff_tx_mod,`
294			`ff_tx_rdy => ff_tx_rdy,`
295			`ff_tx_septy => ff_tx_septy,`
296			`ff_tx_sop => ff_tx_sop,`
297			`ff_tx_wren => ff_tx_wren,`
298			`inbound_data => inbound_data,`
299			`inbound_data_full => inbound_data_full,`
300			`inbound_data_write => inbound_data_write,`
301			`inbound_header => inbound_header,`
302			`inbound_header_write => inbound_header_write,`
303			`inbound_info => inbound_info,`
304			`inbound_info_write => inbound_info_write,`
305			`magic_sleep_n => magic_sleep_n,`
306			`magic_wakeup => magic_wakeup,`
307			`outbound_data => outbound_data,`
308			`outbound_data_read => outbound_data_read,`
309			`outbound_info => outbound_info,`
310			`outbound_info_empty => outbound_info_empty,`
311			`outbound_info_read => outbound_info_read,`
312			`reset => reset,`
313			`rx_err_stat => rx_err_stat,`
314			`rx_frm_type => rx_frm_type,`
315			`set_10 => set_10,`
316			`set_1000 => set_1000,`
317			`tx_ff_uflow => tx_ff_uflow,`
318			`xoff_gen => xoff_gen,`
319			`xon_gen => xon_gen);`
320
321			`u0: esoc_port_mac`
322			`port map(`
323			`ff_tx_crc_fwd => ff_tx_crc_fwd,`
324			`ff_tx_data => ff_tx_data,`
325			`ff_tx_eop => ff_tx_eop,`
326			`ff_tx_err => ff_tx_err,`
327			`ff_tx_mod => ff_tx_mod,`
328			`ff_tx_sop => ff_tx_sop,`
329			`ff_tx_wren => ff_tx_wren,`
330			`ff_tx_clk => clk_control,`
331			`ff_rx_rdy => ff_rx_rdy,`
332			`ff_rx_clk => clk_control,`
333			`address => mac_address,`
334			`read => mac_rd,`
335			`writedata => mac_wrdata,`
336			`write => mac_wr,`
337			`clk => clk_control,`
338			`reset => reset,`
339			`rgmii_in => rgmii_rxd,`
340			`rx_control => rgmii_rxctl,`
341			`tx_clk => clk_rgmii,`
342			`rx_clk => rgmii_rxc,`
343			`set_10 => set_10,`
344			`set_1000 => set_1000,`
345			`xon_gen => xon_gen,`
346			`xoff_gen => xoff_gen,`
347			`magic_sleep_n => magic_sleep_n,`
348			`mdio_in => mdio_in,`
349			`ff_tx_rdy => ff_tx_rdy,`
350			`ff_rx_data => ff_rx_data,`
351			`ff_rx_dval => ff_rx_dval,`
352			`ff_rx_eop => ff_rx_eop,`
353			`ff_rx_mod => ff_rx_mod,`
354			`ff_rx_sop => ff_rx_sop,`
355			`rx_err => open,`
356			`rx_err_stat => rx_err_stat,`
357			`rx_frm_type => rx_frm_type,`
358			`ff_rx_dsav => ff_rx_dsav,`
359			`readdata => mac_rddata,`
360			`waitrequest => mac_wait,`
361			`rgmii_out => rgmii_txd,`
362			`tx_control => rgmii_txctl,`
363			`ena_10 => ena_10,`
364			`eth_mode => eth_mode,`
365			`ff_tx_septy => ff_tx_septy,`
366			`tx_ff_uflow => tx_ff_uflow,`
367			`ff_rx_a_full => ff_rx_a_full,`
368			`ff_rx_a_empty => ff_rx_a_empty,`
369			`ff_tx_a_full => ff_tx_a_full,`
370			`ff_tx_a_empty => ff_tx_a_empty,`
371			`magic_wakeup => magic_wakeup,`
372			`mdio_out => mdio_out,`
373			`mdio_oen => mdio_oen,`
374			`mdc => mdc);`
375
376
377			`mac_mdc <= mdc;`
378			`mac_mdio <= mdio_out when mdio_oen = '0' else 'Z';`
379			`mdio_in <= mac_mdio when mdio_oen = '1' else '0';`
380
381
382			`mac_address <= ctrl_address(mac_address'high downto 0);`
383
384			`mac_wrdata <= ctrl_wrdata;`
385
386			`mac_wr <= ctrl_wr when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
387			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
388			`else '0';`
389
390			`mac_rd <= ctrl_rd when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
391			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
392			`else '0';`
393
394			`ctrl_bus_enable <= '1' when to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base and`
395			`to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mac_base + esoc_port_mac_size`
396			`else '0';`
397
398			`ctrl_wait <= mac_wait when ctrl_bus_enable = '1' else 'Z';`
399
400			`ctrl_rddata <= mac_rddata when ctrl_bus_enable = '1' else (others => 'Z');`
401			`end architecture structure ; -- of esoc_port_interface`
402