| 1 |
42 |
lmaarsen |
--------------------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- Ethernet Switch on Configurable Logic IP Core ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the ESoCL project ----
|
| 6 |
|
|
---- http://www.opencores.org/cores/esoc/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description: see design description ESoCL_dd_71022001.pdf ----
|
| 9 |
|
|
---- ----
|
| 10 |
|
|
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
|
| 11 |
|
|
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
|
| 12 |
|
|
---- ----
|
| 13 |
|
|
---- Author(s): L.Maarsen ----
|
| 14 |
|
|
---- Bert Maarsen, lmaarsen@opencores.org ----
|
| 15 |
|
|
---- ----
|
| 16 |
|
|
--------------------------------------------------------------------------------
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
---- This source file may be used and distributed without ----
|
| 21 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 22 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 23 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 24 |
|
|
---- ----
|
| 25 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 26 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 27 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 28 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 29 |
|
|
---- later version. ----
|
| 30 |
|
|
---- ----
|
| 31 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 32 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 33 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 34 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 35 |
|
|
---- details. ----
|
| 36 |
|
|
---- ----
|
| 37 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 38 |
|
|
---- Public License along with this source; if not, download it ----
|
| 39 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 40 |
|
|
---- ----
|
| 41 |
|
|
--------------------------------------------------------------------------------
|
| 42 |
|
|
-- Object : Entity work.esoc_port_mal_outbound
|
| 43 |
|
|
-- Last modified : Mon Apr 14 12:49:17 2014.
|
| 44 |
|
|
--------------------------------------------------------------------------------
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
|
|
|
| 48 |
|
|
library ieee, std, work;
|
| 49 |
|
|
use ieee.std_logic_1164.all;
|
| 50 |
|
|
use std.textio.all;
|
| 51 |
|
|
use ieee.numeric_std.all;
|
| 52 |
|
|
use work.package_esoc_configuration.all;
|
| 53 |
|
|
|
| 54 |
|
|
entity esoc_port_mal_outbound is
|
| 55 |
|
|
port(
|
| 56 |
|
|
clk_control : in STD_LOGIC;
|
| 57 |
|
|
ff_tx_a_empty : in STD_LOGIC;
|
| 58 |
|
|
ff_tx_a_full : in STD_LOGIC;
|
| 59 |
|
|
ff_tx_crc_fwd : out STD_LOGIC;
|
| 60 |
|
|
ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);
|
| 61 |
|
|
ff_tx_eop : out STD_LOGIC;
|
| 62 |
|
|
ff_tx_err : out STD_LOGIC;
|
| 63 |
|
|
ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);
|
| 64 |
|
|
ff_tx_rdy : in STD_LOGIC;
|
| 65 |
|
|
ff_tx_septy : in STD_LOGIC;
|
| 66 |
|
|
ff_tx_sop : out STD_LOGIC;
|
| 67 |
|
|
ff_tx_wren : out STD_LOGIC;
|
| 68 |
|
|
force_vlan_default_out : in std_logic;
|
| 69 |
|
|
outbound_data : in std_logic_vector(31 downto 0);
|
| 70 |
|
|
outbound_data_read : out std_logic;
|
| 71 |
|
|
outbound_info : in std_logic_vector(15 downto 0);
|
| 72 |
|
|
outbound_info_empty : in std_logic;
|
| 73 |
|
|
outbound_info_read : out std_logic;
|
| 74 |
|
|
port_vlan_default : in std_logic_vector(15 downto 0);
|
| 75 |
|
|
reset : in STD_LOGIC;
|
| 76 |
|
|
tx_ff_uflow : in STD_LOGIC);
|
| 77 |
|
|
end entity esoc_port_mal_outbound;
|
| 78 |
|
|
|
| 79 |
|
|
--------------------------------------------------------------------------------
|
| 80 |
|
|
-- Object : Architecture work.esoc_port_mal_outbound.esoc_port_mal_outbound
|
| 81 |
|
|
-- Last modified : Mon Apr 14 12:49:17 2014.
|
| 82 |
|
|
--------------------------------------------------------------------------------
|
| 83 |
|
|
|
| 84 |
|
|
|
| 85 |
|
|
architecture esoc_port_mal_outbound of esoc_port_mal_outbound is
|
| 86 |
|
|
|
| 87 |
|
|
---------------------------------------------------------------------------------------------------------------
|
| 88 |
|
|
-- registers
|
| 89 |
|
|
---------------------------------------------------------------------------------------------------------------
|
| 90 |
|
|
|
| 91 |
|
|
---------------------------------------------------------------------------------------------------------------
|
| 92 |
|
|
-- signals
|
| 93 |
|
|
---------------------------------------------------------------------------------------------------------------
|
| 94 |
|
|
type ff_tx_states is (idle, running, drop);
|
| 95 |
|
|
signal ff_tx_state: ff_tx_states;
|
| 96 |
|
|
|
| 97 |
|
|
signal ff_tx_byte_counter: integer range 2**esoc_outbound_info_length_size-1 downto 0;
|
| 98 |
|
|
signal ff_tx_word_counter: integer range ((2**esoc_outbound_info_length_size)/4)-1 downto 0;
|
| 99 |
|
|
|
| 100 |
|
|
signal outbound_data_read_enable: std_logic;
|
| 101 |
|
|
signal outbound_data_read_dummy: std_logic;
|
| 102 |
|
|
signal outbound_data_modify_enable: std_logic;
|
| 103 |
|
|
signal outbound_data_modify: std_logic_vector(outbound_data'high downto 0);
|
| 104 |
|
|
|
| 105 |
|
|
signal outbound_info_vlan_flag: std_logic;
|
| 106 |
|
|
|
| 107 |
|
|
signal boundary64: std_logic;
|
| 108 |
|
|
|
| 109 |
|
|
begin
|
| 110 |
|
|
|
| 111 |
|
|
|
| 112 |
|
|
--=============================================================================================================
|
| 113 |
|
|
-- Process : capture and store data when ready acycle occurs
|
| 114 |
|
|
-- Description :
|
| 115 |
|
|
--=============================================================================================================
|
| 116 |
|
|
capture: process(clk_control, reset)
|
| 117 |
|
|
begin
|
| 118 |
|
|
if reset = '1' then
|
| 119 |
|
|
ff_tx_sop <= '0';
|
| 120 |
|
|
ff_tx_eop <= '0';
|
| 121 |
|
|
ff_tx_wren <= '0';
|
| 122 |
|
|
ff_tx_mod <= (others => '0');
|
| 123 |
|
|
ff_tx_byte_counter <= 0;
|
| 124 |
|
|
ff_tx_word_counter <= 0;
|
| 125 |
|
|
|
| 126 |
|
|
outbound_info_vlan_flag <= '0';
|
| 127 |
|
|
|
| 128 |
|
|
outbound_data_modify_enable <= '0';
|
| 129 |
|
|
outbound_data_modify <= (others => '0');
|
| 130 |
|
|
|
| 131 |
|
|
outbound_info_read <= '0';
|
| 132 |
|
|
outbound_data_read_dummy <= '0';
|
| 133 |
|
|
outbound_data_read_enable <= '0';
|
| 134 |
|
|
|
| 135 |
|
|
boundary64 <= '0';
|
| 136 |
|
|
|
| 137 |
|
|
elsif clk_control'event and clk_control = '1' then
|
| 138 |
|
|
-- clear one-clock active signals
|
| 139 |
|
|
outbound_info_read <= '0';
|
| 140 |
|
|
outbound_data_read_dummy <= '0';
|
| 141 |
|
|
outbound_data_modify_enable <= '0';
|
| 142 |
|
|
|
| 143 |
|
|
case ff_tx_state is
|
| 144 |
|
|
when idle => -- create dummy read if the previous transaction does not end on a 64 bit boundary
|
| 145 |
|
|
if boundary64 = '1' then
|
| 146 |
|
|
boundary64 <= '0';
|
| 147 |
|
|
outbound_data_read_dummy <= '1';
|
| 148 |
|
|
|
| 149 |
|
|
-- Info fifo not empty? Get length from info fifo and acknowledge info fifo read! Start packet transmission.
|
| 150 |
|
|
elsif outbound_info_empty = '0' then
|
| 151 |
|
|
-- get the length, subtract 4 byes because first word is provided on ST interface immediately, acknowledge info from fifo
|
| 152 |
|
|
outbound_info_read <= '1';
|
| 153 |
|
|
ff_tx_word_counter <= 0;
|
| 154 |
|
|
ff_tx_byte_counter <= to_integer(unsigned(outbound_info(esoc_outbound_info_length+esoc_outbound_info_length_size-1 downto esoc_outbound_info_length)))-4;
|
| 155 |
|
|
outbound_info_vlan_flag <= outbound_info(esoc_outbound_info_vlan_flag);
|
| 156 |
|
|
|
| 157 |
|
|
-- send packet to MAC or drop packet if an error is indicated, error can be packet in data FIFO not complete due to overrun
|
| 158 |
|
|
if outbound_info(esoc_outbound_info_error_flag) = '0' then
|
| 159 |
|
|
outbound_data_read_enable <= '1';
|
| 160 |
|
|
ff_tx_sop <= '1';
|
| 161 |
|
|
ff_tx_wren <= '1';
|
| 162 |
|
|
ff_tx_state <= running;
|
| 163 |
|
|
|
| 164 |
|
|
-- receive data has an error, drop it!
|
| 165 |
|
|
else
|
| 166 |
|
|
outbound_data_read_dummy <= '1';
|
| 167 |
|
|
ff_tx_state <= drop;
|
| 168 |
|
|
end if;
|
| 169 |
|
|
end if;
|
| 170 |
|
|
|
| 171 |
|
|
when running => -- provide next data when ready is asserted (=acknowledge of current data)
|
| 172 |
|
|
if ff_tx_rdy = '1' then
|
| 173 |
|
|
--
|
| 174 |
|
|
-- CONTROL THE ST INTERFACE TO MAC
|
| 175 |
|
|
--
|
| 176 |
|
|
-- deassert the start of packet
|
| 177 |
|
|
ff_tx_sop <= '0';
|
| 178 |
|
|
|
| 179 |
|
|
-- last word of transaction read by ST Sink port, stop transfer
|
| 180 |
|
|
if ff_tx_byte_counter = 0 then
|
| 181 |
|
|
outbound_data_read_enable <= '0';
|
| 182 |
|
|
ff_tx_eop <= '0';
|
| 183 |
|
|
ff_tx_wren <= '0';
|
| 184 |
|
|
ff_tx_state <= idle;
|
| 185 |
|
|
|
| 186 |
|
|
-- last word of transaction to be read by ST Sink port?
|
| 187 |
|
|
elsif ff_tx_byte_counter <= 4 then
|
| 188 |
|
|
ff_tx_eop <= '1';
|
| 189 |
|
|
ff_tx_byte_counter <= 0;
|
| 190 |
|
|
ff_tx_mod <= std_logic_vector(to_unsigned(4-ff_tx_byte_counter,ff_tx_mod'length));
|
| 191 |
|
|
|
| 192 |
|
|
-- transaction not finished, update counter
|
| 193 |
|
|
else
|
| 194 |
|
|
ff_tx_byte_counter <= ff_tx_byte_counter - 4;
|
| 195 |
|
|
end if;
|
| 196 |
|
|
|
| 197 |
|
|
-- toggle to know from which boundary is read, 32b or 64b
|
| 198 |
|
|
boundary64 <= not(boundary64);
|
| 199 |
|
|
|
| 200 |
|
|
--
|
| 201 |
|
|
-- MANIPULATE DATA
|
| 202 |
|
|
--
|
| 203 |
|
|
-- modify vlan id with default vlan id if packet is tagged and force default vlan is enabled
|
| 204 |
|
|
if ff_tx_word_counter = 2 then
|
| 205 |
|
|
if outbound_info_vlan_flag = '1' and force_vlan_default_out = '1' then
|
| 206 |
|
|
outbound_data_modify_enable <= '1';
|
| 207 |
|
|
outbound_data_modify <= esoc_ethernet_vlan_type & port_vlan_default;
|
| 208 |
|
|
end if;
|
| 209 |
|
|
end if;
|
| 210 |
|
|
|
| 211 |
|
|
ff_tx_word_counter <= ff_tx_word_counter + 1;
|
| 212 |
|
|
|
| 213 |
|
|
end if;
|
| 214 |
|
|
|
| 215 |
|
|
when drop => -- read erroneous packet from FIFO and drop!
|
| 216 |
|
|
-- size of packet always multiple of 8 bytes, no boundary64 mechanism required
|
| 217 |
|
|
if ff_tx_byte_counter <= 4 then
|
| 218 |
|
|
ff_tx_state <= idle;
|
| 219 |
|
|
|
| 220 |
|
|
else
|
| 221 |
|
|
ff_tx_byte_counter <= ff_tx_byte_counter - 4;
|
| 222 |
|
|
end if;
|
| 223 |
|
|
|
| 224 |
|
|
outbound_data_read_dummy <= '1';
|
| 225 |
|
|
|
| 226 |
|
|
when others => ff_tx_state <= idle;
|
| 227 |
|
|
end case;
|
| 228 |
|
|
end if;
|
| 229 |
|
|
end process;
|
| 230 |
|
|
|
| 231 |
|
|
ff_tx_err <= '0';
|
| 232 |
|
|
ff_tx_crc_fwd <= '0';
|
| 233 |
|
|
ff_tx_data <= outbound_data when outbound_data_modify_enable = '0' else outbound_data_modify;
|
| 234 |
|
|
outbound_data_read <= (ff_tx_rdy and outbound_data_read_enable) or outbound_data_read_dummy;
|
| 235 |
|
|
|
| 236 |
|
|
end architecture esoc_port_mal_outbound ; -- of esoc_port_mal_outbound
|
