1 |
2 |
idiolatrie |
--------------------------------------------------------------------------------
|
2 |
|
|
-- ETHERLAB - FPGA To C# To LABVIEW Bridge --
|
3 |
|
|
--------------------------------------------------------------------------------
|
4 |
|
|
-- Copyright (C)2012 Mathias Hörtnagl <mathias.hoertnagl@gmail.com> --
|
5 |
|
|
-- --
|
6 |
|
|
-- This program is free software: you can redistribute it and/or modify --
|
7 |
|
|
-- it under the terms of the GNU General Public License as published by --
|
8 |
|
|
-- the Free Software Foundation, either version 3 of the License, or --
|
9 |
|
|
-- (at your option) any later version. --
|
10 |
|
|
-- --
|
11 |
|
|
-- This program is distributed in the hope that it will be useful, --
|
12 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
13 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
14 |
|
|
-- GNU General Public License for more details. --
|
15 |
|
|
-- --
|
16 |
|
|
-- You should have received a copy of the GNU General Public License --
|
17 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
18 |
|
|
--------------------------------------------------------------------------------
|
19 |
|
|
library ieee;
|
20 |
|
|
use ieee.std_logic_1164.all;
|
21 |
|
|
use ieee.numeric_std.all;
|
22 |
|
|
|
23 |
|
|
library work;
|
24 |
|
|
use work.common.all;
|
25 |
|
|
|
26 |
|
|
entity etherlab is
|
27 |
|
|
port(
|
28 |
|
|
clk : in std_logic;
|
29 |
|
|
|
30 |
|
|
E_COL : in std_logic; -- Collision Detect.
|
31 |
|
|
E_CRS : in std_logic; -- Carrier Sense.
|
32 |
|
|
E_MDC : out std_logic;
|
33 |
|
|
E_MDIO : in std_logic;
|
34 |
|
|
E_RX_CLK : in std_logic; -- Receiver Clock.
|
35 |
|
|
E_RX_DV : in std_logic; -- Received Data Valid.
|
36 |
|
|
E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble.
|
37 |
|
|
E_RX_ER : in std_logic; -- Received Data Error.
|
38 |
|
|
E_TX_CLK : in std_logic; -- Sender Clock.
|
39 |
|
|
E_TX_EN : out std_logic; -- Sender Enable.
|
40 |
|
|
E_TXD : out std_logic_vector(3 downto 0); -- Sent Data.
|
41 |
|
|
E_TX_ER : out std_logic; -- sent Data Error.
|
42 |
|
|
|
43 |
|
|
SPI_MISO : in std_logic; -- Serial data in.
|
44 |
|
|
SPI_MOSI : out std_logic; -- Serial data out.
|
45 |
|
|
SPI_SCK : out std_logic; -- Serial Interface clock.
|
46 |
|
|
DAC_CS : out std_logic; -- D/A Converter chip sel.
|
47 |
|
|
DAC_CLR : out std_logic; -- D/A Converter reset.
|
48 |
|
|
|
49 |
|
|
SF_OE : out std_logic; -- StrataFlash.
|
50 |
|
|
SF_CE : out std_logic;
|
51 |
|
|
SF_WE : out std_logic;
|
52 |
|
|
FPGA_INIT_B : out std_logic;
|
53 |
|
|
AD_CONV : out std_logic; -- A/D Converter chip sel.
|
54 |
|
|
SPI_SS_B : out std_logic;
|
55 |
|
|
AMP_CS : out std_logic; -- Pre-Amplifier chip sel.
|
56 |
|
|
|
57 |
|
|
DI : in std_logic_vector(3 downto 0); -- 6-pin header J1.
|
58 |
|
|
DO : out std_logic_vector(3 downto 0); -- 6-pin header J2.
|
59 |
|
|
SW : in std_logic_vector(3 downto 0); -- SWITCHES.
|
60 |
|
|
BTN : in std_logic_vector(3 downto 0); -- BUTTONS.
|
61 |
|
|
LED : out std_logic_vector(7 downto 0) -- LEDs.
|
62 |
|
|
);
|
63 |
|
|
end etherlab;
|
64 |
|
|
|
65 |
|
|
architecture rtl of etherlab is
|
66 |
|
|
|
67 |
|
|
component clock
|
68 |
|
|
port(
|
69 |
|
|
clkin_in : in std_logic;
|
70 |
|
|
rst_in : in std_logic;
|
71 |
|
|
clkin_ibufg_out : out std_logic;
|
72 |
|
|
clk0_out : out std_logic;
|
73 |
|
|
clk90_out : out std_logic
|
74 |
|
|
);
|
75 |
|
|
end component;
|
76 |
|
|
|
77 |
|
|
component mac_rcv is
|
78 |
|
|
port(
|
79 |
|
|
E_RX_CLK : in std_logic; -- Receiver Clock.
|
80 |
|
|
E_RX_DV : in std_logic; -- Received Data Valid.
|
81 |
|
|
E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble.
|
82 |
|
|
el_chnl : out std_logic_vector(7 downto 0); -- EtherLab channels.
|
83 |
|
|
el_data : out data_t; -- EtherLab channel data.
|
84 |
|
|
el_dv : out std_logic; -- EtherLab data valid.
|
85 |
|
|
el_ack : in std_logic -- Packet reception ACK.
|
86 |
|
|
);
|
87 |
|
|
end component;
|
88 |
|
|
|
89 |
|
|
component mac_snd is
|
90 |
|
|
port(
|
91 |
|
|
E_TX_CLK : in std_logic; -- Sender Clock.
|
92 |
|
|
E_TX_EN : out std_logic; -- Sender Enable.
|
93 |
|
|
E_TXD : out std_logic_vector(3 downto 0); -- Sent Data.
|
94 |
|
|
E_TX_ER : out std_logic; -- Sent Data Error.
|
95 |
|
|
el_chnl : in std_logic_vector(7 downto 0); -- EtherLab channels.
|
96 |
|
|
el_data : in data_t; -- EtherLab data.
|
97 |
|
|
en : in std_logic -- User Start Send.
|
98 |
|
|
);
|
99 |
|
|
end component;
|
100 |
|
|
|
101 |
|
|
component io is
|
102 |
|
|
port(
|
103 |
|
|
clk : in std_logic;
|
104 |
|
|
clk90 : in std_logic;
|
105 |
|
|
-- EtherLab data received.
|
106 |
|
|
el_chnl : in std_logic_vector(7 downto 0);
|
107 |
|
|
el_data : in data_t;
|
108 |
|
|
el_dv : in std_logic;
|
109 |
|
|
el_ack : out std_logic;
|
110 |
|
|
-- EtherLab data to send.
|
111 |
|
|
el_snd_chnl : out std_logic_vector(7 downto 0);
|
112 |
|
|
el_snd_data : out data_t;
|
113 |
|
|
el_snd_en : out std_logic;
|
114 |
|
|
-- DAC/ADC Connections.
|
115 |
|
|
SPI_MISO : in std_logic;
|
116 |
|
|
SPI_MOSI : out std_logic;
|
117 |
|
|
SPI_SCK : out std_logic;
|
118 |
|
|
DAC_CS : out std_logic;
|
119 |
|
|
DAC_CLR : out std_logic;
|
120 |
|
|
AD_CONV : out std_logic;
|
121 |
|
|
AMP_CS : out std_logic;
|
122 |
|
|
-- Digital lines.
|
123 |
|
|
DI : in std_logic_vector(3 downto 0);
|
124 |
|
|
DO : out std_logic_vector(3 downto 0);
|
125 |
|
|
-- SWITCHES.
|
126 |
|
|
SW : in std_logic_vector(3 downto 0);
|
127 |
|
|
-- BUTTONS.
|
128 |
|
|
BTN : in std_logic_vector(3 downto 0);
|
129 |
|
|
-- LEDs.
|
130 |
|
|
LED : out std_logic_vector(7 downto 0)
|
131 |
|
|
);
|
132 |
|
|
end component;
|
133 |
|
|
|
134 |
|
|
signal el_chnl : std_logic_vector(7 downto 0); -- EtherLab channels.
|
135 |
|
|
signal el_data : data_t; -- EtherLab data.
|
136 |
|
|
signal el_dv : std_logic; -- Received data valid.
|
137 |
|
|
signal el_ack : std_logic; -- Packet reception ACK.
|
138 |
|
|
|
139 |
|
|
signal el_snd_chnl : std_logic_vector(7 downto 0); -- EtherLab Send channels.
|
140 |
|
|
signal el_snd_data : data_t; -- EhterLab Send data.
|
141 |
|
|
signal el_snd_en : std_logic; -- Enable sending.
|
142 |
|
|
|
143 |
|
|
signal clk90 : std_logic; -- Clock shiftet 90 degree.
|
144 |
|
|
signal clk0 : std_logic;
|
145 |
|
|
begin
|
146 |
|
|
|
147 |
|
|
SF_OE <= '1'; -- Turn off Strata Flash.
|
148 |
|
|
SF_WE <= '1';
|
149 |
|
|
SF_CE <= '1';
|
150 |
|
|
FPGA_INIT_B <= '1'; -- Turn off Platform Flash.
|
151 |
|
|
SPI_SS_B <= '1'; -- Turn off Serial Flash.
|
152 |
|
|
|
153 |
|
|
E_MDC <= '0';
|
154 |
|
|
|
155 |
|
|
inst_clock: clock port map(
|
156 |
|
|
clkin_in => clk,
|
157 |
|
|
rst_in => '0',
|
158 |
|
|
clkin_ibufg_out => open,
|
159 |
|
|
clk0_out => clk0,
|
160 |
|
|
clk90_out => clk90
|
161 |
|
|
);
|
162 |
|
|
|
163 |
|
|
mac_receive : mac_rcv port map(
|
164 |
|
|
E_RX_CLK => E_RX_CLK,
|
165 |
|
|
E_RX_DV => E_RX_DV,
|
166 |
|
|
E_RXD => E_RXD,
|
167 |
|
|
el_chnl => el_chnl,
|
168 |
|
|
el_data => el_data,
|
169 |
|
|
el_dv => el_dv,
|
170 |
|
|
el_ack => el_ack
|
171 |
|
|
);
|
172 |
|
|
|
173 |
|
|
mac_send : mac_snd port map(
|
174 |
|
|
E_TX_CLK => E_TX_CLK,
|
175 |
|
|
E_TX_EN => E_TX_EN,
|
176 |
|
|
E_TXD => E_TXD,
|
177 |
|
|
E_TX_ER => E_TX_ER,
|
178 |
|
|
en => el_snd_en,
|
179 |
|
|
el_chnl => el_snd_chnl,
|
180 |
|
|
el_data => el_snd_data
|
181 |
|
|
);
|
182 |
|
|
|
183 |
|
|
ioio : io port map(
|
184 |
|
|
clk => clk0,
|
185 |
|
|
clk90 => clk90,
|
186 |
|
|
-- EtherLab data received.
|
187 |
|
|
el_chnl => el_chnl,
|
188 |
|
|
el_data => el_data,
|
189 |
|
|
el_dv => el_dv,
|
190 |
|
|
el_ack => el_ack,
|
191 |
|
|
-- EtherLab data to send.
|
192 |
|
|
el_snd_chnl => el_snd_chnl,
|
193 |
|
|
el_snd_data => el_snd_data,
|
194 |
|
|
el_snd_en => el_snd_en,
|
195 |
|
|
-- DAC/ADC Connections.
|
196 |
|
|
SPI_MISO => SPI_MISO,
|
197 |
|
|
SPI_MOSI => SPI_MOSI,
|
198 |
|
|
SPI_SCK => SPI_SCK,
|
199 |
|
|
DAC_CS => DAC_CS,
|
200 |
|
|
DAC_CLR => DAC_CLR,
|
201 |
|
|
AD_CONV => AD_CONV,
|
202 |
|
|
AMP_CS => AMP_CS,
|
203 |
|
|
-- Digital lines.
|
204 |
|
|
DI => DI,
|
205 |
|
|
DO => DO,
|
206 |
|
|
-- SWITCHES.
|
207 |
|
|
SW => SW,
|
208 |
|
|
-- BUTTONS.
|
209 |
|
|
BTN => BTN,
|
210 |
|
|
-- LEDs.
|
211 |
|
|
LED => LED
|
212 |
|
|
);
|
213 |
|
|
end rtl;
|