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idiolatrie |
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-- ETHERLAB - FPGA To C# To LABVIEW Bridge --
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--------------------------------------------------------------------------------
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-- REFERENCES --
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-- [1] http://tools.ietf.org/html/rfc2460 --
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-- [2] https://en.wikipedia.org/wiki/Ethernet_frame --
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-- [5] http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf --
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-- [6] OPB Ethernet Lite Media Access Controller (v1.01b) --
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-- [7] LAN83C185 - 10/100 Ethernet PHY --
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-- [8] Xilinx UG230 --
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--------------------------------------------------------------------------------
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-- Copyright (C)2012 Mathias Hörtnagl <mathias.hoertnagl@gmail.com> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity mac_rcv is
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port(
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E_RX_CLK : in std_logic; -- Receiver Clock.
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E_RX_DV : in std_logic; -- Received Data Valid.
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E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble.
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el_chnl : out std_logic_vector(7 downto 0); -- EtherLab channels.
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el_data : out data_t; -- EtherLab channel data.
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el_dv : out std_logic; -- EtherLab data valid.
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el_ack : in std_logic -- Packet reception ACK.
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);
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end mac_rcv;
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architecture rtl of mac_rcv is
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type state_t is (
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Preamble, StartOfFrame, -- 7 Bytes 0x55, 1 Byte 0x5d.
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MACS, -- 12 Byte MAC addresses.
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EtherTypeCheck, -- Next Protocol EtherLab?
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Version, -- EtherLab - Version.
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Channel, -- EtherLab - Channel.
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DataU, DataL, -- EtherLab - Channel data.
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Notify -- Inform other hardware components.
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);
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type rcv_t is record
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s : state_t;
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chnl : std_logic_vector(7 downto 0); -- EtherLab channel field.
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d : data_t; -- Channel data.
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c : natural range 0 to 23;
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a : natural range 0 to 7;
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end record;
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signal r, rin : rcv_t
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:= rcv_t'(Preamble, x"00", (others => (others => '0')), 0, 0);
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begin
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rcv_nsl : process(r, E_RX_DV, E_RXD, el_ack)
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begin
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rin <= r;
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el_dv <= '0';
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if E_RX_DV = '1' then
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case r.s is
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--------------------------------------------------------------------
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-- Ethernet II - Preamble and Start Of Frame. --
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--------------------------------------------------------------------
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when Preamble =>
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if E_RXD = x"5" then
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if r.c = 14 then
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rin.c <= 0;
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rin.s <= StartOfFrame;
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else
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rin.c <= r.c + 1;
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end if;
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else
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rin.c <= 0;
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end if;
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when StartOfFrame =>
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if E_RXD = x"d" then
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rin.s <= MACS;
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else
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rin.s <= Preamble;
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end if;
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--------------------------------------------------------------------
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-- Ethernet II - 12 Byte MAC addresses. --
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--------------------------------------------------------------------
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when MACS =>
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if r.c = 23 then
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rin.c <= 0;
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rin.s <= EtherTypeCheck;
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else
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rin.c <= r.c + 1;
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end if;
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--------------------------------------------------------------------
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-- Ethernet II - Next Layer EtherLab? --
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--------------------------------------------------------------------
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when EtherTypeCheck =>
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if E_RXD = x"0" then
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if r.c = 3 then
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rin.c <= 0;
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rin.s <= Version;
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else
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rin.c <= r.c + 1;
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end if;
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else
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rin.c <= 0;
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rin.s <= Preamble;
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end if;
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--------------------------------------------------------------------
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-- EtherLab - Version --
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--------------------------------------------------------------------
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when Version =>
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if r.c = 1 then
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rin.c <= 0;
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rin.s <= Channel;
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else
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rin.c <= r.c + 1;
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end if;
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--------------------------------------------------------------------
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-- EtherLab - Channel Flags. --
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--------------------------------------------------------------------
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when Channel =>
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rin.chnl(7 downto 0) <= E_RXD & r.chnl(7 downto 4);
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if r.c = 1 then
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rin.c <= 0;
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rin.a <= 0;
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rin.s <= DataU;
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else
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rin.c <= r.c + 1;
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end if;
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--------------------------------------------------------------------
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-- EtherLab - Data. 8 channels á 16 bit. --
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--------------------------------------------------------------------
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when DataU =>
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rin.d(r.a)(15 downto 8) <= E_RXD & r.d(r.a)(15 downto 12);
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if r.c = 1 then
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rin.c <= 0;
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rin.s <= DataL;
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else
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rin.c <= r.c + 1;
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end if;
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when DataL =>
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rin.d(r.a)(7 downto 0) <= E_RXD & r.d(r.a)(7 downto 4);
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if r.c = 1 then
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rin.c <= 0;
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if r.a = 7 then
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rin.a <= 0;
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rin.s <= Notify;
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else
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rin.a <= r.a + 1;
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rin.s <= DataU;
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end if;
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else
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rin.c <= r.c + 1;
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end if;
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--------------------------------------------------------------------
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-- Notification --
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--------------------------------------------------------------------
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when Notify =>
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el_dv <= '1';
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rin.s <= Preamble;
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end case;
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end if;
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end process;
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snd_reg : process(E_RX_CLK)
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begin
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if rising_edge(E_RX_CLK) then
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r <= rin;
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end if;
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end process;
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el_chnl <= r.chnl;
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el_data <= r.d;
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end rtl;
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