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-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

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--   ____  ____ 

--  /   /\/   / 

-- /___/  \  /    Vendor: Xilinx 

-- \   \   \/     Version : 13.1

--  \   \         Application : xaw2vhdl

--  /   /         Filename : clock.vhd

-- /___/   /\     Timestamp : 02/27/2012 13:36:57

-- \   \  /  \ 

--  \___\/\___\ 

--

--Command: xaw2vhdl-st C:\Mathias\smole\etherlab\xilinx\ipcore_dir\.\clock.xaw C:\Mathias\smole\etherlab\xilinx\ipcore_dir\.\clock

--Design Name: clock

--Device: xc3s500e-4fg320

--

-- Module clock

-- Generated by Xilinx Architecture Wizard

-- Written for synthesis tool: XST

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity clock is

   port ( CLKIN_IN        : in    std_logic;

          RST_IN          : in    std_logic;

          CLKIN_IBUFG_OUT : out   std_logic;

          CLK0_OUT        : out   std_logic;

          CLK90_OUT       : out   std_logic);

end clock;

architecture BEHAVIORAL of clock is

   signal CLKFB_IN        : std_logic;

   signal CLKIN_IBUFG     : std_logic;

   signal CLK0_BUF        : std_logic;

   signal CLK90_BUF       : std_logic;

   signal GND_BIT         : std_logic;

begin

   GND_BIT <= '0';

   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;

   CLK0_OUT <= CLKFB_IN;

   CLKIN_IBUFG_INST : IBUFG

      port map (I=>CLKIN_IN,

                O=>CLKIN_IBUFG);

   CLK0_BUFG_INST : BUFG

      port map (I=>CLK0_BUF,

                O=>CLKFB_IN);

   CLK90_BUFG_INST : BUFG

      port map (I=>CLK90_BUF,

                O=>CLK90_OUT);

   DCM_SP_INST : DCM_SP

   generic map( CLK_FEEDBACK => "1X",

            CLKDV_DIVIDE => 2.0,

            CLKFX_DIVIDE => 1,

            CLKFX_MULTIPLY => 4,

            CLKIN_DIVIDE_BY_2 => FALSE,

            CLKIN_PERIOD => 20.000,

            CLKOUT_PHASE_SHIFT => "NONE",

            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",

            DFS_FREQUENCY_MODE => "LOW",

            DLL_FREQUENCY_MODE => "LOW",

            DUTY_CYCLE_CORRECTION => TRUE,

            FACTORY_JF => x"C080",

            PHASE_SHIFT => 0,

            STARTUP_WAIT => FALSE)

      port map (CLKFB=>CLKFB_IN,

                CLKIN=>CLKIN_IBUFG,

                DSSEN=>GND_BIT,

                PSCLK=>GND_BIT,

                PSEN=>GND_BIT,

                PSINCDEC=>GND_BIT,

                RST=>RST_IN,

                CLKDV=>open,

                CLKFX=>open,

                CLKFX180=>open,

                CLK0=>CLK0_BUF,

                CLK2X=>open,

                CLK2X180=>open,

                CLK90=>CLK90_BUF,

                CLK180=>open,

                CLK270=>open,

                LOCKED=>open,

                PSDONE=>open,

                STATUS=>open);

end BEHAVIORAL;