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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [bench/] [fft_filter2_tb.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT-based FIR Filter IP core                               ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--
-- File        : fft_filter2_TB.vhd
-- Generated   : 08.08.05, 13:25
---------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
 
 
entity fft_filter2_tb is
        generic(
                iwidth : INTEGER := 16;
                owidth : INTEGER := 18;
                wwidth : INTEGER := 16;
                n : INTEGER := 10;
                v2 : INTEGER := 1;
                reall : INTEGER := 1;
                filtre:std_logic_vector(1 downto 0):="01");
end fft_filter2_tb;
 
architecture TB_ARCHITECTURE of fft_filter2_tb is
        constant tc:time:=12.5 ns;      -- clock period =1/Fclk   
        constant fs:real:=2500.0 ; --sampling frequency Fs in kHz
        constant nd:natural:=32; -- Fclk=nd*Fs, nd>29      
        constant df:real:=5.0;--19.5*4.0;  -- step of frequency in kHz to show the freq. characteristic
        constant f00:real:=00.0;        -- init frequency in kHz
        constant magn:real:=30000.0; -- input signal magnitude    
        constant Fl1:real:=100.0;        -- low pass band
        constant Fh1:real:=200.0;       -- high pass band
        constant Fl2:real:=100.0;        -- low pass band
        constant Fh2:real:=200.0;       -- high pass band
 
 
 
        component fft_filter2
                generic(
                        iwidth : INTEGER := 8;
                        owidth : INTEGER := 8;
                        wwidth : INTEGER := 8;
                        n : INTEGER := 7;
                        v2 : INTEGER := 1;
                        reall : INTEGER := 0 );
                port(
                        CLK : in std_logic;
                        RST : in std_logic;
                        CE : in std_logic;
                        START : in std_logic;
                        DATAE : in std_logic;
                        FILTER : in std_logic_vector(1 downto 0);
                        L1 : in std_logic_vector((n-1) downto 0);
                        H1 : in std_logic_vector((n-1) downto 0);
                        L2 : in std_logic_vector((n-1) downto 0);
                        H2 : in std_logic_vector((n-1) downto 0);
                        DATAIRE : in std_logic_vector((iwidth-1) downto 0);
                        DATAIIM : in std_logic_vector((iwidth-1) downto 0);
                        READY : out std_logic;
                        DATAORE : out std_logic_vector((owidth-1) downto 0);
                        DATAOIM : out std_logic_vector((owidth-1) downto 0);
                        SPRDY: out STD_LOGIC;
                        WESP: out STD_LOGIC;
                        SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                        SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                        FREQ:out STD_LOGIC_VECTOR (n-1 downto 0);
                        SPEXP:out STD_LOGIC_VECTOR (3 downto 0)   ) ;
 
        end component;
 
        signal CLK : std_logic:='1';
        signal RST : std_logic:='1';
        signal CE : std_logic;
        signal START : std_logic;
        signal DATAE,rdyd : std_logic;
        signal FILTER : std_logic_vector(1 downto 0);
        signal L1 : std_logic_vector((n-1) downto 0);
        signal H1 : std_logic_vector((n-1) downto 0);
        signal L2 : std_logic_vector((n-1) downto 0);
        signal H2 : std_logic_vector((n-1) downto 0);
        signal DATAIRE : std_logic_vector((iwidth-1) downto 0);
        signal DATAIIM : std_logic_vector((iwidth-1) downto 0);
        --      signal READY : std_logic;
        signal DATAORE : std_logic_vector((owidth-1) downto 0);
        signal DATAOIM : std_logic_vector((owidth-1) downto 0);
        signal clk_ce : std_logic  := '1';
        signal DATA_IN,DATA_OUT,DATA_IN1,DATA_OUT1 : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
        signal rs,rc,f0,res,reslog,f1,frequ:real:=0.0;
        signal p,p1,p2,p3,p4,ENA,RDY : std_logic:='0';
        signal cnt,ct2:natural;
        signal ssc,scc,coun,freque:integer;
        constant a1:std_logic_vector((iwidth-1) downto 0):=
        CONV_STD_LOGIC_VECTOR(integer(0.99 * magn),iwidth);
        constant a0:std_logic_vector((iwidth-1) downto 0):=(others=>'0');
        constant nn:real:=real(2**n);
 
begin
        FILTER<=filtre; --01 prosto filter, 10 filter+differenc-r
        CE<='1'; -- bez zamedlenija
 
        l1<=conv_std_logic_vector(integer(1.0*Fl1*nn/fs),n);
        h1<=conv_std_logic_vector(integer(1.0*Fh1*nn/fs),n);
        l2<=conv_std_logic_vector(integer(1.0*Fl2*nn/fs),n);
        h2<=conv_std_logic_vector(integer(1.0*Fh2*nn/fs),n);
 
        rst <= '1','0' after 103 ns;
        clk <= not clk after 0.5*tc; --Generator sinchroserii
        start<='0', '1' after 104 ns,'0' after 104 ns + 2*tc;
        QUANT:process(rst,CLK)
        begin
                if rst='1' then cnt<=0;
                elsif rising_edge(CLK) then
                        if cnt= nd-1 then
                                cnt<=0; ENA<='1' ;
                        else
                                cnt<=cnt+1;ENA<='0' ;
                        end if;
                end if;
 
        end process;
 
        -- Unit Under Test port map
        UUT : fft_filter2
        generic map (
                iwidth => iwidth,
                owidth => owidth,
                wwidth => wwidth,
                n => n,
                v2 => v2,
                reall => reall
                )
 
        port map (CLK,RST,CE,
                START => START,
                DATAE => ENA,
                FILTER => FILTER,
                L1 => L1,
                H1 => H1,
                L2 => L2,
                H2 => H2,
                DATAIRE => DATA_In,
                DATAIIM => DATA_in1,
                READY => RDY,
                DATAORE =>DATAORE,
                DATAOIM =>DATAOIM
                );
 
        DATA_Out<=DATAORE(owidth-1 downto owidth-iwidth);
        DATA_Out1<=DATAOIM(owidth-1 downto owidth-iwidth);
 
        EPOCH:process   begin
                --wait for 1500*tc*nd;
                loop
                        p <= '0'; wait for (1024*nd-1)*tc;-- 0.25*1000 us;  p <= '1';   wait for 4*12.5 ns;
                        p<='1'; wait for tc;
                end loop;
        end process;
 
        SINE_GEN:process(clk,rst)
                variable i : real;
                variable j : integer;
        begin
                if rst = '1' then
                        ct2<=0;
                        rs <= 0.0;
                        i := 0.0; j := 0;
                        f0 <= f00;
                        rdyd<='0';
                elsif clk = '1' and clk'event then
                        rdyd<=rdy;
                        if RDY='1' and rdyd='0' then
                                if ct2=1 then
                                        ct2<=0;
                                        f0 <= f0 + df;  f1 <= f0*2.5;
                                else
                                        ct2<= ct2+1;            -- counter of even/odd FFT
                                end if;
 
                        end if;
                        --      if p = '1' then f0 <= f0 + df;  f1 <= f0*2.5; end if;   
 
                        rc <=  cos(f0 * 2.0 * math_pi * i/Fs); --0.0;----
                        rs <=  sin(f0 * 2.0 * math_pi * i/Fs);
                        if ENA='1' then i:=i+1.0; end if;
                end if;
        end process;
 
        data_in1 <=(CONV_STD_LOGIC_VECTOR(integer(rs * magn),16));--others=>'0');-- ----
        data_in  <= CONV_STD_LOGIC_VECTOR(integer(rc * magn),16); -- when p = '1' else x"0000";
        --      data_in  <= CONV_STD_LOGIC_VECTOR(integer(0.9 * magn),16); -- when p = '1' else x"0000";
--              data_in<=a0, a1 after 0.01 us, a0 after 14 us, a1 after 30 us,a0 after 35 us,
--              a1 after 70 us, a0 after 74 us, a1 after 91 us,a0 after 105 us,
--              a1 after 120 us, a0 after 123 us, a1 after 141 us,a0 after 155 us;
        --              p1 <= transport p after 10 us;
 
 
 
        process(clk,rst)
                variable couni : integer := 0;
                variable ss,sc,sm0,r,rsum : real;
        begin
                if rst = '1' then
                        reslog <= -100.0;
                        res<=0.0;
                elsif clk = '1' and clk'event  then
 
                        if RDY='1' and rdyd='0'and ct2=1 then
                                coun <= 0;
                                rsum:=0.0;
                        end if;
 
                        if coun /= 32 and ENA='1' then
                                coun <= coun + 1;
                        end if;
 
                        if ENA='1' then
 
                                if coun >= 0 and coun < 30 then
 
                                        ss := real(conv_integer(signed(data_out)))/magn;
                                        sc := real(conv_integer(signed(data_out1)))/magn;
                                        sm0 := ss*ss + sc*sc + 0.00000000000001;        --; --   
                                        r := 20.0 * log10(sqrt(sm0));
                                        rsum := rsum + sm0;
                                end if;
 
                                if coun = 31 then
                                        res<= sqrt(rsum/30.0)  ;
                                        reslog <= 20.0 * log10(sqrt(rsum/30.0));
                                        freque<=integer(f0-df);
                                end if;
                        end if;
                end if;
        end process;
 
        ssc <= (conv_integer(signed(data_out)));
        scc <= (conv_integer(signed(data_out1)));
end TB_ARCHITECTURE;
 

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [bench/] [fft_filter2_tb.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT-based FIR Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`--`
40			`-- File : fft_filter2_TB.vhd`
41			`-- Generated : 08.08.05, 13:25`
42			`---------------------------------------------------------------------------------------------------`
43
44			`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use IEEE.std_logic_unsigned.all;`
47			`use IEEE.math_real.all;`
48			`use IEEE.std_logic_arith.all;`
49
50
51			`entity fft_filter2_tb is`
52			`generic(`
53			`iwidth : INTEGER := 16;`
54			`owidth : INTEGER := 18;`
55			`wwidth : INTEGER := 16;`
56			`n : INTEGER := 10;`
57			`v2 : INTEGER := 1;`
58			`reall : INTEGER := 1;`
59			`filtre:std_logic_vector(1 downto 0):="01");`
60			`end fft_filter2_tb;`
61
62			`architecture TB_ARCHITECTURE of fft_filter2_tb is`
63			`constant tc:time:=12.5 ns; -- clock period =1/Fclk`
64			`constant fs:real:=2500.0 ; --sampling frequency Fs in kHz`
65			`constant nd:natural:=32; -- Fclk=nd*Fs, nd>29`
66			`constant df:real:=5.0;--19.5*4.0; -- step of frequency in kHz to show the freq. characteristic`
67			`constant f00:real:=00.0; -- init frequency in kHz`
68			`constant magn:real:=30000.0; -- input signal magnitude`
69			`constant Fl1:real:=100.0; -- low pass band`
70			`constant Fh1:real:=200.0; -- high pass band`
71			`constant Fl2:real:=100.0; -- low pass band`
72			`constant Fh2:real:=200.0; -- high pass band`
73
74
75
76			`component fft_filter2`
77			`generic(`
78			`iwidth : INTEGER := 8;`
79			`owidth : INTEGER := 8;`
80			`wwidth : INTEGER := 8;`
81			`n : INTEGER := 7;`
82			`v2 : INTEGER := 1;`
83			`reall : INTEGER := 0 );`
84			`port(`
85			`CLK : in std_logic;`
86			`RST : in std_logic;`
87			`CE : in std_logic;`
88			`START : in std_logic;`
89			`DATAE : in std_logic;`
90			`FILTER : in std_logic_vector(1 downto 0);`
91			`L1 : in std_logic_vector((n-1) downto 0);`
92			`H1 : in std_logic_vector((n-1) downto 0);`
93			`L2 : in std_logic_vector((n-1) downto 0);`
94			`H2 : in std_logic_vector((n-1) downto 0);`
95			`DATAIRE : in std_logic_vector((iwidth-1) downto 0);`
96			`DATAIIM : in std_logic_vector((iwidth-1) downto 0);`
97			`READY : out std_logic;`
98			`DATAORE : out std_logic_vector((owidth-1) downto 0);`
99			`DATAOIM : out std_logic_vector((owidth-1) downto 0);`
100			`SPRDY: out STD_LOGIC;`
101			`WESP: out STD_LOGIC;`
102			`SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
103			`SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
104			`FREQ:out STD_LOGIC_VECTOR (n-1 downto 0);`
105			`SPEXP:out STD_LOGIC_VECTOR (3 downto 0) ) ;`
106
107			`end component;`
108
109			`signal CLK : std_logic:='1';`
110			`signal RST : std_logic:='1';`
111			`signal CE : std_logic;`
112			`signal START : std_logic;`
113			`signal DATAE,rdyd : std_logic;`
114			`signal FILTER : std_logic_vector(1 downto 0);`
115			`signal L1 : std_logic_vector((n-1) downto 0);`
116			`signal H1 : std_logic_vector((n-1) downto 0);`
117			`signal L2 : std_logic_vector((n-1) downto 0);`
118			`signal H2 : std_logic_vector((n-1) downto 0);`
119			`signal DATAIRE : std_logic_vector((iwidth-1) downto 0);`
120			`signal DATAIIM : std_logic_vector((iwidth-1) downto 0);`
121			`-- signal READY : std_logic;`
122			`signal DATAORE : std_logic_vector((owidth-1) downto 0);`
123			`signal DATAOIM : std_logic_vector((owidth-1) downto 0);`
124			`signal clk_ce : std_logic := '1';`
125			`signal DATA_IN,DATA_OUT,DATA_IN1,DATA_OUT1 : STD_LOGIC_VECTOR(15 downto 0) := x"0000";`
126			`signal rs,rc,f0,res,reslog,f1,frequ:real:=0.0;`
127			`signal p,p1,p2,p3,p4,ENA,RDY : std_logic:='0';`
128			`signal cnt,ct2:natural;`
129			`signal ssc,scc,coun,freque:integer;`
130			`constant a1:std_logic_vector((iwidth-1) downto 0):=`
131			`CONV_STD_LOGIC_VECTOR(integer(0.99 * magn),iwidth);`
132			`constant a0:std_logic_vector((iwidth-1) downto 0):=(others=>'0');`
133			`constant nn:real:=real(2**n);`
134
135			`begin`
136			`FILTER<=filtre; --01 prosto filter, 10 filter+differenc-r`
137			`CE<='1'; -- bez zamedlenija`
138
139			`l1<=conv_std_logic_vector(integer(1.0Fl1nn/fs),n);`
140			`h1<=conv_std_logic_vector(integer(1.0Fh1nn/fs),n);`
141			`l2<=conv_std_logic_vector(integer(1.0Fl2nn/fs),n);`
142			`h2<=conv_std_logic_vector(integer(1.0Fh2nn/fs),n);`
143
144			`rst <= '1','0' after 103 ns;`
145			`clk <= not clk after 0.5*tc; --Generator sinchroserii`
146			`start<='0', '1' after 104 ns,'0' after 104 ns + 2*tc;`
147			`QUANT:process(rst,CLK)`
148			`begin`
149			`if rst='1' then cnt<=0;`
150			`elsif rising_edge(CLK) then`
151			`if cnt= nd-1 then`
152			`cnt<=0; ENA<='1' ;`
153			`else`
154			`cnt<=cnt+1;ENA<='0' ;`
155			`end if;`
156			`end if;`
157
158			`end process;`
159
160			`-- Unit Under Test port map`
161			`UUT : fft_filter2`
162			`generic map (`
163			`iwidth => iwidth,`
164			`owidth => owidth,`
165			`wwidth => wwidth,`
166			`n => n,`
167			`v2 => v2,`
168			`reall => reall`
169			`)`
170
171			`port map (CLK,RST,CE,`
172			`START => START,`
173			`DATAE => ENA,`
174			`FILTER => FILTER,`
175			`L1 => L1,`
176			`H1 => H1,`
177			`L2 => L2,`
178			`H2 => H2,`
179			`DATAIRE => DATA_In,`
180			`DATAIIM => DATA_in1,`
181			`READY => RDY,`
182			`DATAORE =>DATAORE,`
183			`DATAOIM =>DATAOIM`
184			`);`
185
186			`DATA_Out<=DATAORE(owidth-1 downto owidth-iwidth);`
187			`DATA_Out1<=DATAOIM(owidth-1 downto owidth-iwidth);`
188
189			`EPOCH:process begin`
190			`--wait for 1500tcnd;`
191			`loop`
192			`p <= '0'; wait for (1024nd-1)tc;-- 0.251000 us; p <= '1'; wait for 412.5 ns;`
193			`p<='1'; wait for tc;`
194			`end loop;`
195			`end process;`
196
197			`SINE_GEN:process(clk,rst)`
198			`variable i : real;`
199			`variable j : integer;`
200			`begin`
201			`if rst = '1' then`
202			`ct2<=0;`
203			`rs <= 0.0;`
204			`i := 0.0; j := 0;`
205			`f0 <= f00;`
206			`rdyd<='0';`
207			`elsif clk = '1' and clk'event then`
208			`rdyd<=rdy;`
209			`if RDY='1' and rdyd='0' then`
210			`if ct2=1 then`
211			`ct2<=0;`
212			`f0 <= f0 + df; f1 <= f0*2.5;`
213			`else`
214			`ct2<= ct2+1; -- counter of even/odd FFT`
215			`end if;`
216
217			`end if;`
218			`-- if p = '1' then f0 <= f0 + df; f1 <= f0*2.5; end if;`
219
220			`rc <= cos(f0 * 2.0 * math_pi * i/Fs); --0.0;----`
221			`rs <= sin(f0 * 2.0 * math_pi * i/Fs);`
222			`if ENA='1' then i:=i+1.0; end if;`
223			`end if;`
224			`end process;`
225
226			`data_in1 <=(CONV_STD_LOGIC_VECTOR(integer(rs * magn),16));--others=>'0');-- ----`
227			`data_in <= CONV_STD_LOGIC_VECTOR(integer(rc * magn),16); -- when p = '1' else x"0000";`
228			`-- data_in <= CONV_STD_LOGIC_VECTOR(integer(0.9 * magn),16); -- when p = '1' else x"0000";`
229			`-- data_in<=a0, a1 after 0.01 us, a0 after 14 us, a1 after 30 us,a0 after 35 us,`
230			`-- a1 after 70 us, a0 after 74 us, a1 after 91 us,a0 after 105 us,`
231			`-- a1 after 120 us, a0 after 123 us, a1 after 141 us,a0 after 155 us;`
232			`-- p1 <= transport p after 10 us;`
233
234
235
236			`process(clk,rst)`
237			`variable couni : integer := 0;`
238			`variable ss,sc,sm0,r,rsum : real;`
239			`begin`
240			`if rst = '1' then`
241			`reslog <= -100.0;`
242			`res<=0.0;`
243			`elsif clk = '1' and clk'event then`
244
245			`if RDY='1' and rdyd='0'and ct2=1 then`
246			`coun <= 0;`
247			`rsum:=0.0;`
248			`end if;`
249
250			`if coun /= 32 and ENA='1' then`
251			`coun <= coun + 1;`
252			`end if;`
253
254			`if ENA='1' then`
255
256			`if coun >= 0 and coun < 30 then`
257
258			`ss := real(conv_integer(signed(data_out)))/magn;`
259			`sc := real(conv_integer(signed(data_out1)))/magn;`
260			`sm0 := ssss + scsc + 0.00000000000001; --; --`
261			`r := 20.0 * log10(sqrt(sm0));`
262			`rsum := rsum + sm0;`
263			`end if;`
264
265			`if coun = 31 then`
266			`res<= sqrt(rsum/30.0) ;`
267			`reslog <= 20.0 * log10(sqrt(rsum/30.0));`
268			`freque<=integer(f0-df);`
269			`end if;`
270			`end if;`
271			`end if;`
272			`end process;`
273
274			`ssc <= (conv_integer(signed(data_out)));`
275			`scc <= (conv_integer(signed(data_out1)));`
276			`end TB_ARCHITECTURE;`
277