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[/] [fft_fir_filter/] [trunk/] [rtl/] [alfft_core_slip.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
--              DESCRIPTION:
--
--      FUNCTION         Fast Fourier Transform of
--                       N=16, 32, 64, 128, 256, 512, 1024, 2048 points,
--                       N= 2**n,
--                       ifft=0 forward FFT,
--                       rams=1 - single data RAM, =2 dual data RAM
--                       input data width: iwidth = 8,...,16 bit   signed 
--                                             output   data width: owidth = 8,...,16 bit   signed     
--                       coefficient width : wwidth = 8,...,16 bit
--                                  Synthesable for Virtex, SpartanII FPGAs. 
--              Slipping transform      with windowing
--      FILES:           ALFFT_Core_slip.vhd -this file
--               FFTDPATH.vhd   - data path of the FFT butterfly                 
--               CONTROL.vhd   - control unit       
--                                    ROM_COS.vhd   -   coefficient ROM
--                                   RAM2X_2.vhd   -  dual data RAM block                  
--                  When redesign data RAM blocks
--                     the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity ALFFT_Core is
        generic (       ifft: INTEGER:=0;            --  0- forward FFT
                rams:INTEGER:=2;   -- 1,2
                iwidth: INTEGER:=8      ;               --  input data width =8...16
                owidth: INTEGER:=8      ;       -- output data width =8...16
                wwidth: INTEGER:=8;                     --  coefficient width =8...16  
                n:INTEGER:=7 ;
                v2:INTEGER:=1 ; -- 1 - Virtex2
                slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2 
                wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija
                reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                );  --4,5, 6,7,8,9,10,11   - transform length factor
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                START: in STD_LOGIC;
                DATAE: in STD_LOGIC;
                DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                FFTRDY: out STD_LOGIC;
                READY: out STD_LOGIC;
                WERES: out STD_LOGIC;
                ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);
                DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                EXP: out STD_LOGIC_VECTOR (3 downto 0)
                );
end ALFFT_Core;
 
architecture ALFFT_CoreS of ALFFT_Core is
 
        component  FFTDPATH is
                generic (       ifft: integer:=0;
                        width: integer :=8      ;               --  word width =8...16
                        wwdth: integer:=7;                      --  coefficient width =7...15  
                        V2:integer
                        );
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        ODDC:     in STD_LOGIC;      --Odd cycle
                        DIV2: in STD_LOGIC;             --Scaling factor
                        ZWR: in STD_LOGIC;
                        ZWI: in STD_LOGIC;
                        SIGNRE:  in STD_LOGIC;
                        MODE: in STD_LOGIC_VECTOR (1 downto 0);
                        REDI: in STD_LOGIC_VECTOR (width downto 0);
                        IMDI: in STD_LOGIC_VECTOR (width downto 0);
                        WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
                        REDO: out STD_LOGIC_VECTOR (width downto 0);
                        IMDO: out STD_LOGIC_VECTOR (width downto 0)
                        );
        end  component;
 
        component  ROM_COS is
                generic(n: integer; --- FFT factor= 6,7,8,9,10,11
                        wwdth: integer:=15;-- output word width =8...15  , cos>0
                        wnd: integer);
                port  ( SELW:in STD_LOGIC;
                        ADDRROM :in std_logic_vector(n-2 downto 0);
                        COS : out std_logic_vector(wwdth-1 downto 0)
                        );
        end component ;
 
 
 
        component RAM2X is
                generic(        iwidth : INTEGER;
                        width : INTEGER;
                        n:INTEGER);  -- 6,7,8,9,10,11
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        WEI: in STD_LOGIC;          -- for input data
                        WEM: in STD_LOGIC;        -- for intermediate data
                        INITOVERF:    in STD_LOGIC;
                        ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        EVEN: in STD_LOGIC;                      --0- 0th bank 1- 1st bank -for DIRE,DIIM
                        DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                        OVERF:out  STD_LOGIC;
                        DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                        DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
                        );
        end component ;
        component RAM2X2 is
                generic(  iwidth : INTEGER:=16;
                        width : INTEGER:=16;
                        n:INTEGER:=8;     -- 6,7,8,9,10,11
                        v2:INTEGER);
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        WEI: in STD_LOGIC;          -- for input data
                        WEM: in STD_LOGIC;        -- for intermediate data    
                        INITOVERF:   in STD_LOGIC;
                        ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
                        EVEN: in STD_LOGIC;                      --0- 1th bank is read 1- 0tht bank -is read
                        DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                        OVERF:out  STD_LOGIC;
                        DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                        DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
                        );
        end component;
 
        component CONTROL is
                generic (       ifft:INTEGER;--:=0;        
                        rams:INTEGER;--:=1;
                        n:INTEGER;  -- 6,7,8,9,10,11
                        slip:INTEGER;
                        reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                        );
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        START: in STD_LOGIC;
                        DATAE: in STD_LOGIC;
                        OVERF: in STD_LOGIC;
                        FFTRDY: out STD_LOGIC;
                        READY: out STD_LOGIC;
                        WE: out STD_LOGIC;
                        WEI: out STD_LOGIC;
                        WEM: out STD_LOGIC;
                        WERES: out STD_LOGIC;
                        SEL: out STD_LOGIC;                                                                       -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                        ODDC:     out STD_LOGIC;
                        EVEN: out STD_LOGIC;                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                        DIV2: out STD_LOGIC;
                        ZWR: out STD_LOGIC;
                        ZWI: out STD_LOGIC;
                        SIGNRE:  out STD_LOGIC;
                        INITOVERF:   out STD_LOGIC;
                        SELW: out STD_LOGIC;      --0 -twiddle 1 - window  
                        MODE: out STD_LOGIC_VECTOR (1 downto 0);
                        EXP: out STD_LOGIC_VECTOR (3 downto 0);
                        ADDRW: out STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;
                        ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
                        ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
                        );
        end component ;
 
        --constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');
        signal  ODDC:   STD_LOGIC;      --Odd cycle
        signal  DIV2:  STD_LOGIC;             --Scaling factor
        signal          ZWR: STD_LOGIC;
        signal          ZWI:  STD_LOGIC;
        signal          SIGNRE:  STD_LOGIC;
        signal          REDI:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          IMDI:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          WF:  STD_LOGIC_VECTOR (wwidth-2 downto 0);
        signal          REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          IMDO:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal      OVERF: STD_LOGIC;
        signal          INITOVERF:     STD_LOGIC;
        signal          WE:  STD_LOGIC;
        signal          WEI: STD_LOGIC;
        signal          WEM: STD_LOGIC;
        signal          SEL,SELW:  STD_LOGIC;                                                                     -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
        signal          EVEN:  STD_LOGIC;                        --0- 0th bank 1- 1st bank -for DIRE,DIIM
        signal          ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
        signal          ADDRR:  STD_LOGIC_VECTOR (n - 1 downto 0);
        signal          ADDRWIN: STD_LOGIC_VECTOR (n - 1 downto 0);
        signal          ADDRWM: STD_LOGIC_VECTOR (n - 1 downto 0) ;
        signal          ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);
        signal      MODE: STD_LOGIC_VECTOR (1 downto 0);
        signal DIRE,DIIM:    STD_LOGIC_VECTOR (iwidth-1 downto 0);
        signal    sn01,sn02:integer;
 
begin
 
        DIRE<=DATAIRE;-- & zeros;
        DIIM<=DATAIIM;-- & zeros;
 
 
        U_PATH:  FFTDPATH
        generic map(    ifft=>ifft,
                width=>owidth-1,                --  word width =7...15
                wwdth=>wwidth-1,                        --  coefficient width =7...15  
                V2=>v2
                )
        port map(
                CLK=>  CLK,
                RST=> RST,
                CE=>  CE,
                MODE=>mode,
                ODDC=>ODDC,         --Odd cycle
                DIV2=>    DIV2,           --Scaling factor
                ZWR=>  ZWR,
                ZWI=>    ZWI,
                SIGNRE=>SIGNRE,
                REDI=>REDI,
                IMDI=> IMDI,
                WF=> WF,
                REDO=>REDO,
                IMDO=>IMDO
                );
 
 
        U_ROM:ROM_COS
        generic map(n=>n, --- FFT factor= 6,7,8,9,10,11
                wwdth=>wwidth-1, -- output word width =8...15  , cos>0
                wnd=>wnd)
        port map (
                SELW=>selw,
                ADDRROM =>ADDRROM,
                COS =>WF);
 
        --      CNTRL_SLIP0:if slip=0 generate  
        --              U_CNTRL:entity CONTROL(CONTROL) 
        --              generic map(    ifft=>ifft,   
        --                      rams=>rams,
        --                      n=>n ,                   -- 6,7,8,9,10,11
        --                      slip=>slip
        --                      )
        --              port map(
        --                      CLK=>CLK ,
        --                      RST=> RST,
        --                      CE=>CE ,          
        --                      START=>START ,
        --                      DATAE=> DATAE,
        --                      OVERF=> OVERF,  
        --                      FFTRDY=>        FFTRDY,
        --                      READY=> READY,
        --                      WE=> WE,
        --                      WEI=> WEI,
        --                      WEM=> WEM, 
        --                      INITOVERF=>INITOVERF,
        --                      WERES=>WERES,  
        --                      SEL=>SEL ,                                                                        -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
        --                      ODDC=>ODDC,
        --                      EVEN=> EVEN,                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
        --                      DIV2=> DIV2, 
        --                      ZWR=> ZWR,      
        --                      ZWI=> ZWI,        
        --                      SIGNRE=>SIGNRE ,         
        --                      EXP=>EXP,
        --                      ADDRW=> ADDRW,  
        --                      ADDRR=> ADDRR,  
        --                      ADDRWIN=>ADDRWIN,
        --                      ADDRWM=> ADDRWM,
        --                      ADDRRES=>ADDRRES,    
        --                      ADDRROM =>ADDRROM
        --                      );                                                  
        --      end generate;   
 
        --      CNTR_SLIP2: if slip=2 generate  
        U_CNTRL:entity CONTROL(CONTROL_SLIP)
        generic map(    ifft=>ifft,
                rams=>rams,
                n=>n ,                   -- 6,7,8,9,10,11
                slip=>slip,
                reall=>reall
                )
        port map(
                CLK=>CLK ,
                RST=> RST,
                CE=>CE ,
                START=>START ,
                DATAE=> DATAE,
                OVERF=> OVERF,
                FFTRDY=>        FFTRDY,
                READY=> READY,
                WE=> WE,
                WEI=> WEI,
                WEM=> WEM,
                INITOVERF=>INITOVERF,
                WERES=>WERES,
                --      SEL=>SEL ,      -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                ODDC=>ODDC,
                MODE=>mode,
                EVEN=> EVEN,                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                DIV2=> DIV2,
                ZWR=> ZWR,
                ZWI=> ZWI,
                SELW=>selw,
                SIGNRE=>SIGNRE ,
                EXP=>EXP,
                ADDRR=> ADDRR,
                ADDRWIN=>ADDRWIN,
                ADDRWM=> ADDRWM,
                ADDRRES=>ADDRRES,
                ADDRROM =>ADDRROM
                );
        --      end generate;
 
        --      RAM2: if rams=2 and slip=0 generate
        --              U_RAM:   RAM2X  
        --              generic map( iwidth=>iwidth, 
        --                      width =>owidth,
        --                      n=>n              -- 6,7,8,9,10,11
        --                      --              ,v2=>v2
        --                      )  
        --              port map(
        --                      CLK=>CLK ,
        --                      RST=> RST,    
        --                      CE=> CE,
        --                      WEI=> WEI,          -- for input data
        --                      WEM=> WEM,        -- for intermediate data
        --                      ADDRWIN=> ADDRWIN,  
        --                      ADDRWM=> ADDRWM,  
        --                      ADDRR=> ADDRR,  
        --                      EVEN=>EVEN ,                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
        --                      DIRE=>DIRE,
        --                      DIIM=> DIIM,
        --                      DMRE=> REDO,
        --                      DMIM=> IMDO,   
        --                      OVERF=> OVERF ,
        --                      INITOVERF=>INITOVERF,
        --                      DORE=>REDI,
        --                      DOIM=> IMDI
        --                      );
        --              
        --      end generate;      
 
        RAM2s: if rams=2 and slip=2 generate
                U_RAM:   RAM2X2
                generic map( iwidth=>iwidth,
                        width =>owidth,
                        n=>n              -- 6,7,8,9,10,11
                        ,v2=>v2
                        )
                port map(
                        CLK=>CLK ,
                        RST=> RST,
                        CE=> CE,
                        WEI=> WEI,          -- for input data
                        WEM=> WEM,        -- for intermediate data
                        ADDRWIN=> ADDRWIN,
                        ADDRWM=> ADDRWM,
                        ADDRR=> ADDRR,
                        EVEN=>EVEN ,                     --0- 0th bank (Input) 1- 1st bank -for DIRE,DIIM
                        DIRE=>DIRE,
                        DIIM=> DIIM,
                        DMRE=> REDO,
                        DMIM=> IMDO,
                        OVERF=> OVERF ,
                        INITOVERF=>INITOVERF,
                        DORE=>REDI,
                        DOIM=> IMDI
                        );
 
        end generate;
 
        DATAORE<=REDO ;
        DATAOIM<=IMDO ;
        sn01<=conv_integer(signed(redo));
        sn02<=conv_integer(signed(imdo));
 
 
end ALFFT_CoreS;

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [alfft_core_slip.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
40			`-- DESCRIPTION:`
41			`--`
42			`-- FUNCTION Fast Fourier Transform of`
43			`-- N=16, 32, 64, 128, 256, 512, 1024, 2048 points,`
44			`-- N= 2**n,`
45			`-- ifft=0 forward FFT,`
46			`-- rams=1 - single data RAM, =2 dual data RAM`
47			`-- input data width: iwidth = 8,...,16 bit signed`
48			`-- output data width: owidth = 8,...,16 bit signed`
49			`-- coefficient width : wwidth = 8,...,16 bit`
50			`-- Synthesable for Virtex, SpartanII FPGAs.`
51			`-- Slipping transform with windowing`
52			`-- FILES: ALFFT_Core_slip.vhd -this file`
53			`-- FFTDPATH.vhd - data path of the FFT butterfly`
54			`-- CONTROL.vhd - control unit`
55			`-- ROM_COS.vhd - coefficient ROM`
56			`-- RAM2X_2.vhd - dual data RAM block`
57			`-- When redesign data RAM blocks`
58			`-- the Core will fit another FPGA families`
59			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--`
60
61			`library IEEE;`
62			`use IEEE.std_logic_1164.all;`
63			`use IEEE.std_logic_arith.all;`
64
65			`entity ALFFT_Core is`
66			`generic ( ifft: INTEGER:=0; -- 0- forward FFT`
67			`rams:INTEGER:=2; -- 1,2`
68			`iwidth: INTEGER:=8 ; -- input data width =8...16`
69			`owidth: INTEGER:=8 ; -- output data width =8...16`
70			`wwidth: INTEGER:=8; -- coefficient width =8...16`
71			`n:INTEGER:=7 ;`
72			`v2:INTEGER:=1 ; -- 1 - Virtex2`
73			`slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2`
74			`wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija`
75			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
76			`); --4,5, 6,7,8,9,10,11 - transform length factor`
77			`port (`
78			`CLK: in STD_LOGIC;`
79			`RST: in STD_LOGIC;`
80			`CE: in STD_LOGIC;`
81			`START: in STD_LOGIC;`
82			`DATAE: in STD_LOGIC;`
83			`DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
84			`DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
85			`FFTRDY: out STD_LOGIC;`
86			`READY: out STD_LOGIC;`
87			`WERES: out STD_LOGIC;`
88			`ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);`
89			`DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
90			`DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
91			`EXP: out STD_LOGIC_VECTOR (3 downto 0)`
92			`);`
93			`end ALFFT_Core;`
94
95			`architecture ALFFT_CoreS of ALFFT_Core is`
96
97			`component FFTDPATH is`
98			`generic ( ifft: integer:=0;`
99			`width: integer :=8 ; -- word width =8...16`
100			`wwdth: integer:=7; -- coefficient width =7...15`
101			`V2:integer`
102			`);`
103			`port (`
104			`CLK: in STD_LOGIC;`
105			`RST: in STD_LOGIC;`
106			`CE: in STD_LOGIC;`
107			`ODDC: in STD_LOGIC; --Odd cycle`
108			`DIV2: in STD_LOGIC; --Scaling factor`
109			`ZWR: in STD_LOGIC;`
110			`ZWI: in STD_LOGIC;`
111			`SIGNRE: in STD_LOGIC;`
112			`MODE: in STD_LOGIC_VECTOR (1 downto 0);`
113			`REDI: in STD_LOGIC_VECTOR (width downto 0);`
114			`IMDI: in STD_LOGIC_VECTOR (width downto 0);`
115			`WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);`
116			`REDO: out STD_LOGIC_VECTOR (width downto 0);`
117			`IMDO: out STD_LOGIC_VECTOR (width downto 0)`
118			`);`
119			`end component;`
120
121			`component ROM_COS is`
122			`generic(n: integer; --- FFT factor= 6,7,8,9,10,11`
123			`wwdth: integer:=15;-- output word width =8...15 , cos>0`
124			`wnd: integer);`
125			`port ( SELW:in STD_LOGIC;`
126			`ADDRROM :in std_logic_vector(n-2 downto 0);`
127			`COS : out std_logic_vector(wwdth-1 downto 0)`
128			`);`
129			`end component ;`
130
131
132
133			`component RAM2X is`
134			`generic( iwidth : INTEGER;`
135			`width : INTEGER;`
136			`n:INTEGER); -- 6,7,8,9,10,11`
137			`port (`
138			`CLK: in STD_LOGIC;`
139			`RST: in STD_LOGIC;`
140			`CE: in STD_LOGIC;`
141			`WEI: in STD_LOGIC; -- for input data`
142			`WEM: in STD_LOGIC; -- for intermediate data`
143			`INITOVERF: in STD_LOGIC;`
144			`ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);`
145			`ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);`
146			`ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);`
147			`EVEN: in STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
148			`DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
149			`DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
150			`DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
151			`DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
152			`OVERF:out STD_LOGIC;`
153			`DORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
154			`DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)`
155			`);`
156			`end component ;`
157			`component RAM2X2 is`
158			`generic( iwidth : INTEGER:=16;`
159			`width : INTEGER:=16;`
160			`n:INTEGER:=8; -- 6,7,8,9,10,11`
161			`v2:INTEGER);`
162			`port (`
163			`CLK: in STD_LOGIC;`
164			`RST: in STD_LOGIC;`
165			`CE: in STD_LOGIC;`
166			`WEI: in STD_LOGIC; -- for input data`
167			`WEM: in STD_LOGIC; -- for intermediate data`
168			`INITOVERF: in STD_LOGIC;`
169			`ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);`
170			`ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);`
171			`ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);`
172			`EVEN: in STD_LOGIC; --0- 1th bank is read 1- 0tht bank -is read`
173			`DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
174			`DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
175			`DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
176			`DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
177			`OVERF:out STD_LOGIC;`
178			`DORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
179			`DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)`
180			`);`
181			`end component;`
182
183			`component CONTROL is`
184			`generic ( ifft:INTEGER;--:=0;`
185			`rams:INTEGER;--:=1;`
186			`n:INTEGER; -- 6,7,8,9,10,11`
187			`slip:INTEGER;`
188			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
189			`);`
190			`port (`
191			`CLK: in STD_LOGIC;`
192			`RST: in STD_LOGIC;`
193			`CE: in STD_LOGIC;`
194			`START: in STD_LOGIC;`
195			`DATAE: in STD_LOGIC;`
196			`OVERF: in STD_LOGIC;`
197			`FFTRDY: out STD_LOGIC;`
198			`READY: out STD_LOGIC;`
199			`WE: out STD_LOGIC;`
200			`WEI: out STD_LOGIC;`
201			`WEM: out STD_LOGIC;`
202			`WERES: out STD_LOGIC;`
203			`SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
204			`ODDC: out STD_LOGIC;`
205			`EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
206			`DIV2: out STD_LOGIC;`
207			`ZWR: out STD_LOGIC;`
208			`ZWI: out STD_LOGIC;`
209			`SIGNRE: out STD_LOGIC;`
210			`INITOVERF: out STD_LOGIC;`
211			`SELW: out STD_LOGIC; --0 -twiddle 1 - window`
212			`MODE: out STD_LOGIC_VECTOR (1 downto 0);`
213			`EXP: out STD_LOGIC_VECTOR (3 downto 0);`
214			`ADDRW: out STD_LOGIC_VECTOR (n - 1 downto 0);`
215			`ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0);`
216			`ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);`
217			`ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;`
218			`ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);`
219			`ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)`
220			`);`
221			`end component ;`
222
223			`--constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');`
224			`signal ODDC: STD_LOGIC; --Odd cycle`
225			`signal DIV2: STD_LOGIC; --Scaling factor`
226			`signal ZWR: STD_LOGIC;`
227			`signal ZWI: STD_LOGIC;`
228			`signal SIGNRE: STD_LOGIC;`
229			`signal REDI: STD_LOGIC_VECTOR (owidth-1 downto 0);`
230			`signal IMDI: STD_LOGIC_VECTOR (owidth-1 downto 0);`
231			`signal WF: STD_LOGIC_VECTOR (wwidth-2 downto 0);`
232			`signal REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);`
233			`signal IMDO: STD_LOGIC_VECTOR (owidth-1 downto 0);`
234			`signal OVERF: STD_LOGIC;`
235			`signal INITOVERF: STD_LOGIC;`
236			`signal WE: STD_LOGIC;`
237			`signal WEI: STD_LOGIC;`
238			`signal WEM: STD_LOGIC;`
239			`signal SEL,SELW: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
240			`signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
241			`signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);`
242			`signal ADDRR: STD_LOGIC_VECTOR (n - 1 downto 0);`
243			`signal ADDRWIN: STD_LOGIC_VECTOR (n - 1 downto 0);`
244			`signal ADDRWM: STD_LOGIC_VECTOR (n - 1 downto 0) ;`
245			`signal ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);`
246			`signal MODE: STD_LOGIC_VECTOR (1 downto 0);`
247			`signal DIRE,DIIM: STD_LOGIC_VECTOR (iwidth-1 downto 0);`
248			`signal sn01,sn02:integer;`
249
250			`begin`
251
252			`DIRE<=DATAIRE;-- & zeros;`
253			`DIIM<=DATAIIM;-- & zeros;`
254
255
256			`U_PATH: FFTDPATH`
257			`generic map( ifft=>ifft,`
258			`width=>owidth-1, -- word width =7...15`
259			`wwdth=>wwidth-1, -- coefficient width =7...15`
260			`V2=>v2`
261			`)`
262			`port map(`
263			`CLK=> CLK,`
264			`RST=> RST,`
265			`CE=> CE,`
266			`MODE=>mode,`
267			`ODDC=>ODDC, --Odd cycle`
268			`DIV2=> DIV2, --Scaling factor`
269			`ZWR=> ZWR,`
270			`ZWI=> ZWI,`
271			`SIGNRE=>SIGNRE,`
272			`REDI=>REDI,`
273			`IMDI=> IMDI,`
274			`WF=> WF,`
275			`REDO=>REDO,`
276			`IMDO=>IMDO`
277			`);`
278
279
280			`U_ROM:ROM_COS`
281			`generic map(n=>n, --- FFT factor= 6,7,8,9,10,11`
282			`wwdth=>wwidth-1, -- output word width =8...15 , cos>0`
283			`wnd=>wnd)`
284			`port map (`
285			`SELW=>selw,`
286			`ADDRROM =>ADDRROM,`
287			`COS =>WF);`
288
289			`-- CNTRL_SLIP0:if slip=0 generate`
290			`-- U_CNTRL:entity CONTROL(CONTROL)`
291			`-- generic map( ifft=>ifft,`
292			`-- rams=>rams,`
293			`-- n=>n , -- 6,7,8,9,10,11`
294			`-- slip=>slip`
295			`-- )`
296			`-- port map(`
297			`-- CLK=>CLK ,`
298			`-- RST=> RST,`
299			`-- CE=>CE ,`
300			`-- START=>START ,`
301			`-- DATAE=> DATAE,`
302			`-- OVERF=> OVERF,`
303			`-- FFTRDY=> FFTRDY,`
304			`-- READY=> READY,`
305			`-- WE=> WE,`
306			`-- WEI=> WEI,`
307			`-- WEM=> WEM,`
308			`-- INITOVERF=>INITOVERF,`
309			`-- WERES=>WERES,`
310			`-- SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
311			`-- ODDC=>ODDC,`
312			`-- EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM`
313			`-- DIV2=> DIV2,`
314			`-- ZWR=> ZWR,`
315			`-- ZWI=> ZWI,`
316			`-- SIGNRE=>SIGNRE ,`
317			`-- EXP=>EXP,`
318			`-- ADDRW=> ADDRW,`
319			`-- ADDRR=> ADDRR,`
320			`-- ADDRWIN=>ADDRWIN,`
321			`-- ADDRWM=> ADDRWM,`
322			`-- ADDRRES=>ADDRRES,`
323			`-- ADDRROM =>ADDRROM`
324			`-- );`
325			`-- end generate;`
326
327			`-- CNTR_SLIP2: if slip=2 generate`
328			`U_CNTRL:entity CONTROL(CONTROL_SLIP)`
329			`generic map( ifft=>ifft,`
330			`rams=>rams,`
331			`n=>n , -- 6,7,8,9,10,11`
332			`slip=>slip,`
333			`reall=>reall`
334			`)`
335			`port map(`
336			`CLK=>CLK ,`
337			`RST=> RST,`
338			`CE=>CE ,`
339			`START=>START ,`
340			`DATAE=> DATAE,`
341			`OVERF=> OVERF,`
342			`FFTRDY=> FFTRDY,`
343			`READY=> READY,`
344			`WE=> WE,`
345			`WEI=> WEI,`
346			`WEM=> WEM,`
347			`INITOVERF=>INITOVERF,`
348			`WERES=>WERES,`
349			`-- SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
350			`ODDC=>ODDC,`
351			`MODE=>mode,`
352			`EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM`
353			`DIV2=> DIV2,`
354			`ZWR=> ZWR,`
355			`ZWI=> ZWI,`
356			`SELW=>selw,`
357			`SIGNRE=>SIGNRE ,`
358			`EXP=>EXP,`
359			`ADDRR=> ADDRR,`
360			`ADDRWIN=>ADDRWIN,`
361			`ADDRWM=> ADDRWM,`
362			`ADDRRES=>ADDRRES,`
363			`ADDRROM =>ADDRROM`
364			`);`
365			`-- end generate;`
366
367			`-- RAM2: if rams=2 and slip=0 generate`
368			`-- U_RAM: RAM2X`
369			`-- generic map( iwidth=>iwidth,`
370			`-- width =>owidth,`
371			`-- n=>n -- 6,7,8,9,10,11`
372			`-- -- ,v2=>v2`
373			`-- )`
374			`-- port map(`
375			`-- CLK=>CLK ,`
376			`-- RST=> RST,`
377			`-- CE=> CE,`
378			`-- WEI=> WEI, -- for input data`
379			`-- WEM=> WEM, -- for intermediate data`
380			`-- ADDRWIN=> ADDRWIN,`
381			`-- ADDRWM=> ADDRWM,`
382			`-- ADDRR=> ADDRR,`
383			`-- EVEN=>EVEN , --0- 0th bank 1- 1st bank -for DIRE,DIIM`
384			`-- DIRE=>DIRE,`
385			`-- DIIM=> DIIM,`
386			`-- DMRE=> REDO,`
387			`-- DMIM=> IMDO,`
388			`-- OVERF=> OVERF ,`
389			`-- INITOVERF=>INITOVERF,`
390			`-- DORE=>REDI,`
391			`-- DOIM=> IMDI`
392			`-- );`
393			`--`
394			`-- end generate;`
395
396			`RAM2s: if rams=2 and slip=2 generate`
397			`U_RAM: RAM2X2`
398			`generic map( iwidth=>iwidth,`
399			`width =>owidth,`
400			`n=>n -- 6,7,8,9,10,11`
401			`,v2=>v2`
402			`)`
403			`port map(`
404			`CLK=>CLK ,`
405			`RST=> RST,`
406			`CE=> CE,`
407			`WEI=> WEI, -- for input data`
408			`WEM=> WEM, -- for intermediate data`
409			`ADDRWIN=> ADDRWIN,`
410			`ADDRWM=> ADDRWM,`
411			`ADDRR=> ADDRR,`
412			`EVEN=>EVEN , --0- 0th bank (Input) 1- 1st bank -for DIRE,DIIM`
413			`DIRE=>DIRE,`
414			`DIIM=> DIIM,`
415			`DMRE=> REDO,`
416			`DMIM=> IMDO,`
417			`OVERF=> OVERF ,`
418			`INITOVERF=>INITOVERF,`
419			`DORE=>REDI,`
420			`DOIM=> IMDI`
421			`);`
422
423			`end generate;`
424
425			`DATAORE<=REDO ;`
426			`DATAOIM<=IMDO ;`
427			`sn01<=conv_integer(signed(redo));`
428			`sn02<=conv_integer(signed(imdo));`
429
430
431			`end ALFFT_CoreS;`