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[/] [fft_fir_filter/] [trunk/] [rtl/] [control_slip.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity CONTROL is
        generic (       ifft:INTEGER:=0;
                rams:INTEGER:=2;
                n:INTEGER:=8;  -- 6,7,8,9,10,11
                slip:INTEGER;
                reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                );
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                START: in STD_LOGIC;
                DATAE: in STD_LOGIC;
                OVERF: in STD_LOGIC;
                FFTRDY: out STD_LOGIC;
                READY: out STD_LOGIC;
                WE: out STD_LOGIC;
                WEI: out STD_LOGIC;
                WEM: out STD_LOGIC;
                WERES: out STD_LOGIC;
                --HRES: out STD_LOGIC;    
                INITOVERF:   out STD_LOGIC;
                --              SEL: out STD_LOGIC;                                                                       -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
                ODDC:     out STD_LOGIC;
                EVEN: out STD_LOGIC;                     --0- 0th bank 1- 1st bank -for DIRE,DIIM
                DIV2: out STD_LOGIC;
                ZWR: out STD_LOGIC;
                ZWI: out STD_LOGIC;
                SELW: out STD_LOGIC;      --0 -twiddle 1 - window
                SIGNRE:  out STD_LOGIC;
                MODE: out STD_LOGIC_VECTOR (1 downto 0);
                EXP: out STD_LOGIC_VECTOR (3 downto 0);
                ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0); -- data reading address   
                ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);--input data writing address 
                ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;--working data writing address 
                ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);--result address    
                ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
                );
end CONTROL;
 
 
 
architecture CONTROL_slip of CONTROL is
 
        constant NN: INTEGER:=2**n;
        constant lat: INTEGER:=7; --latency
        constant lat2: INTEGER:=7; --latency in butterflies       
        constant one:INTEGER:=2**(n-1);
        constant onehalf:INTEGER:=2**(n-2);
        signal   strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;
        signal fftfly,infly,resfly:   STD_LOGIC; --FFT run flag,input flag,result fag
        signal resrdy, resrdy2,idatardy:   STD_LOGIC; --FFT result ready flag
        signal fftend,FFTRDYi:   STD_LOGIC; --FFT end flag
        signal enditera:STD_LOGIC; --end of iteration 
        signal incbfly:         STD_LOGIC; -- +1 to reading data address     
        signal incbflyw:         STD_LOGIC; -- +1 to writing data address     
        signal startitera: STD_LOGIC; -- iteration start
        signal startiterad1: STD_LOGIC; -- iteration start  
        signal startiterad0: STD_LOGIC; -- iteration start
        signal ODDCi:   STD_LOGIC; -- 1 when odd clock cycle         
        signal startiterad2: STD_LOGIC;     --delayed iteration start
        signal wefft: STD_LOGIC;     --we fft data
        signal addrwid, addrwidi        :STD_LOGIC_VECTOR(n-1 downto 0);  --I. data writing address
        signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address
        signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number           
        signal  ADDRRi:  STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
        signal  ADDRwosst,addrrwin:  STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
        signal  ADDRWi:  STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
        signal  addres0,addres1:        STD_LOGIC_VECTOR (n-1 downto 0);
        signal  resnum,resnumi:STD_LOGIC_VECTOR (n-1 downto 0);
        signal  ADDRWwin,ADDRwwini,ADDRwnd:  STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
        signal  ADDRF:  STD_LOGIC_VECTOR (n-2 downto 0); --data writing address
        signal  bflies:  STD_LOGIC_VECTOR (n downto 0); --butterfly counter
        signal startiterad:       STD_LOGIC_VECTOR (lat downto 1);
        signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0);    -- increment to the factor address
        signal  EXPi:  STD_LOGIC_VECTOR (3 downto 0);
        signal ADDRROMi :STD_LOGIC_VECTOR (n-2 downto 0);
        signal  WERESULTi,wed:  STD_LOGIC;
        signal irdy:STD_LOGIC_VECTOR (1 downto 0);
        signal ird,winend,wewin:  STD_LOGIC;
        signal inflyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);
        signal fwd,fwdd,resend,resfld,wereswosst:STD_LOGIC;
        constant nulls:STD_LOGIC_VECTOR (n-2 downto 0):=(others=>'0');
begin
 
 
        CTIDATA:process(CLK,RST)    -- data counter for input
        begin
                if RST='1' then
                        addrwidi<=(others=>'0');
                        addrwid<=(others=>'0');
                        irdy<="00";
                        ird<='0';
                        idatardy<= '0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if START='1' then       -- or FFTRDYi='1'
                                        addrwidi<=  (others=>'0');
                                elsif  DATAE='1' then     --(strt='1' ) and or go='1'  or god2='1' 
                                        irdy<="00";
                                        if UNSIGNED(addrwidi)=NN-1 then
                                                addrwidi<=  (others=>'0');
                                                irdy<="10";
                                        else
                                                addrwidi<=UNSIGNED(addrwidi)+1;
 
                                        end if;
 
                                        if UNSIGNED(addrwidi)=NN-1 then
                                                irdy<="10";
                                        elsif UNSIGNED(addrwidi)=NN/2-1 then
                                                irdy<="01";
                                        end if;
                                end if;
                        end if;
                        ird<= irdy(0)or irdy(1);
                        idatardy<= (irdy(0)or irdy(1)) and not ird;
                end if;
        end process;
 
        CTRIDAT_W:process(CLK,RST,addrwwini)    -- data counter for reading/writing to multiply by window
        begin
                if RST='1' then
                        addrrwin<=(others=>'0');
                        addrwnd<=(others=>'0');
                        addrwwini<=(others=>'0');
                        wewin<='0';
                        winend<='0';
                        EVEN<='1';
                        fwd<='1';
                        fwdd<='1';
                        winend<='0'; -- koniec umnozenia na okno
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                EVEN<=not infly;
                                fwdd<=fwd;
                                inflyd<=inflyd(14 downto 0)& infly;
                                winend<='0';
                                if iarrdy='1' then      -- or FFTRDYi='1' 
                                        fwd<='1';
                                        addrrwin<=  irdy(0)& nulls ;
                                        addrwwini<=(others=>'0');
                                        addrwnd<=(others=>'0');
                                elsif infly='1' then
                                        addrrwin<=UNSIGNED(addrrwin)+1;
                                        if UNSIGNED(addrrwin(n-2 downto 0))= nn/2-2  then
                                                fwd<='0';
                                        end if;
                                        if fwd='1' then
                                                addrwnd<=UNSIGNED(addrwnd)+1;--address okna   
                                        elsif fwdd='0' then
                                                addrwnd<=UNSIGNED(addrwnd)-1;
                                        end if;
                                        if      UNSIGNED(addrwnd)= nn-3 and fwd='0' then ---4
                                                winend<='1';      --konec umnozenia na okno
                                        end if;
                                end if;
                                if wewin='1' then        --  inflyd(4)='1' 
                                        addrwwini<=UNSIGNED(addrwwini)+1;
                                end if;
                                wewin<=inflyd(3);       --(4)
                        end if;
                end if;
                for i in 0 to n-1 loop
                        addrwwin(i)<=addrwwini(n-i-1); --addrwwini(i);--  --2-th inverse writing address
                end loop;
        end process;
 
 
 
        CTLAT:process(RST,CLK)      --delay on 1 LUT
        begin
                if RST='1' then
                        startiterad1<='0';
                        startiterad2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                startiterad1<=startitera;
                                startiterad2<=startiterad0;
                        end if;
                end if;
        end process;
 
        CTLATS:process(RST,CLK)      --delay on 1 LUT     
        begin
                if CLK='1' and CLK'event then
                        if CE='1' then
                                startiterad<=startiterad(lat-1 downto 1)&startitera;
                        end if;
                end if;
        end process;
        startiterad0<=   startiterad(lat);
 
 
        TODDC:process(CLK,RST)      --odd cycle for FFT
        begin
                if RST='1' then
                        ODDCi<='0';
                elsif CLK='1' and CLK'event    then
                        if CE='1' then
                                if startitera='1' or FFTend='1' or resend='1' then
                                        ODDCi<='0';
                                elsif fftfly='1' or resfly='1' then
                                        ODDCi<= not ODDCi;
                                end if;
                        end if;
                end if;
        end process;
 
        ODDC<= ODDCi;
 
        CTRADDR:process(CLK,RST,ADDRRi)  --FFT read counter        
                variable sum:STD_LOGIC_VECTOR (n downto 0);
                variable inc:STD_LOGIC;
        begin
                if RST='1' then
                        incbfly<='0';
                        ADDRRi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startitera='1' then
                                        ADDRRi<=( others=>'0');
                                elsif fftfly='1' then
                                        sum:=UNSIGNED('0'&ADDRRi)+UNSIGNED(itera);
                                        inc:= sum(n);
                                        ADDRRi<=UNSIGNED(sum(n-1 downto 0))+inc;
                                        incbfly<=inc;
                                end if;
                        end if;
                end if;
        end process;
 
        CTWADDR:process(CLK,RST,ADDRWi)  --FFT write counter       
                variable sum:STD_LOGIC_VECTOR (n downto 0);
                variable inc:STD_LOGIC;
        begin
                if RST='1' then
                        ADDRWi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startiterad2='1' then
                                        ADDRWi<=( others=>'0');
                                elsif fftfly='1' then
                                        sum:=UNSIGNED('0'&ADDRWi)+UNSIGNED(itera);
                                        inc:= sum(n);
                                        ADDRWi<=UNSIGNED(sum(n-1 downto 0))+inc;
                                end if;
                        end if;
                end if;
        end process;
 
        LINCADDRF:process(itera)
        begin
                for i in 0 to n-2 loop
                        incaddrf(i)<=itera(n-1-i);
                end loop;
        end process;
 
        CTADDRF: process(CLK,RST)  --iteration counter               
        begin
                if RST='1' then
                        ADDRF<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if startiterad1='1' then
                                        ADDRF<=( others=>'0');
                                elsif fftfly='1' and incbfly = '1' then
                                        ADDRF<=UNSIGNED(ADDRF)+UNSIGNED(incaddrf);
                                end if;
                        end if;
                end if;
        end process;
 
 
 
        FADDRROM:process(CLK,RST)
        begin
                if RST='1' then
                        SIGNRE<='0';
                        ZWR<='0';
                        ZWI<='0';
                        ADDRROMi<=( others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if UNSIGNED(ADDRF)=onehalf then
                                        ZWR<='1';
                                else
                                        ZWR<='0';
                                end if;
 
                                if UNSIGNED(ADDRF)=0 or resfly='1' then
                                        ZWI<='1';
                                else
                                        ZWI<='0';
                                end if;
 
                                if ODDCi='1' then      --cosine address
                                        if ADDRF(n-2)='0' then
                                                ADDRROMi<='0'&ADDRF(n-3 downto 0);
                                                SIGNRE<='0';
                                        else
                                                ADDRROMi<=onehalf-UNSIGNED('0'&ADDRF(n-3 downto 0));
                                                SIGNRE<='1';
                                        end if;
 
                                else                                 -- sine address
                                        if ADDRF(n-2)='0' then
                                                ADDRROMi<=onehalf -UNSIGNED('0'&ADDRF(n-3 downto 0));
                                        else
                                                ADDRROMi<='0'&ADDRF(n-3 downto 0);
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
 
        CTBFLIES:process(CLK,RST,bflies)  --butterfly counter               
        begin
                if RST='1' then
                        wefft<='0';
                        enditera<='0';
                        bflies<=( others=>'0');
                        WERESULTi<='0';
                        FFTRDYi<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
 
                                if startiterad2='1' then
                                        wefft<='1';
                                        if  itera(n-1)='1'then
                                                WERESULTi<='1';
                                        end if;
                                end if;
 
                                if startitera='1' then
                                        bflies<=( others=>'0');
                                elsif  fftfly='1'
                                        then
                                        bflies<=UNSIGNED(bflies)+1;
                                end if;
 
                                if idatardy ='1' and go ='0'   then
                                        FFTRDYi<='1';
                                elsif UNSIGNED(bflies)=nn + lat2 and enditera='0' then
                                        enditera<='1';
                                        wefft<='0';
                                        WERESULTi<='0';
                                        if itera(n-1)='1' then
                                                FFTRDYi<='1';
                                        end if;
                                else
                                        enditera<='0';
                                        FFTRDYi<='0';
                                end if;
                        end if;
                end if;
        end process;
 
        TIARRDY:process(CLK,RST)    --1st input data ready
        begin
                if RST='1' then
                        iarrdy<='0';
                        iarrdy1<='0';
                        go<='0';
                        god<='0';
                        god2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if START='1' then
                                        iarrdy<='0';
                                        iarrdy1<='0';
                                        go<='0';
                                elsif idatardy='1' then
                                        iarrdy<='1';
                                        go<='1';
                                        god<='0';
                                        if go='0'
                                                then
                                                iarrdy1<='1';
                                        end if;
 
                                else
                                        god2<=god;
                                        iarrdy<='0';
                                        iarrdy1<='0';
                                        if   FFTRDYi='1' then
                                                god<='1'    ;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        CTITERA:process(CLK,RST)  --iteration counter               
        begin
                if RST='1' then
                        itera<=CONV_STD_LOGIC_VECTOR(1,n);
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if  FFTRDYi='1' then
                                        itera<=CONV_STD_LOGIC_VECTOR(1,n);
                                elsif enditera='1' then
                                        itera<=itera(n-2 downto 0)&'0';
                                end if;
                        end if;
                end if;
        end process;
 
 
        CTWOSST:process(CLK,RST)  -- data counters for wosstanowlenija
        begin
                if RST='1' then
                        addres0<=(others=>'0');
                        addres1<=(others=>'0');
                        resnumi<=(others=>'0');
                        resend<='0';
                        resfld<='0';
                        --      WERESwosst<='0';
                elsif CLK='1' and CLK'event then
                        resend<='0';
                        if CE='1' then
                                resflyd<=resflyd(14 downto 0)& resfly;
                                resfld<=resflyd(6);
 
                                if fftend='1' then      -- or FFTRDYi='1'
                                        addres0<=  (others=>'0');
                                        addres1<= (others=>'0');  -- conv_std_logic_vector(NN,n+1);
                                        resnumi<=(others=>'0');
 
                                elsif resfly='1' then
 
                                        if oddci='1' then
                                                addres0<=UNSIGNED(addres0)+1;
                                                addres1<=UNSIGNED(addres1)-1;
                                        end if;
 
                                        if resfld='1' and resfly='1' then
                                                resnumi<=UNSIGNED(resnumi)+1;
                                        end if;
                                        if UNSIGNED(resnumi)=nn-2 then    ---1
                                                resend<='1';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        WERESwosst<=resfld and resfly;
        addrwosst<=addres0 when oddci='1' else addres1(n-1 downto 0);
        resnum<=resnumi(0)&resnumi(n-1 downto 1);
        resrdy2<=resflyd(6) and not     resfld;
 
        TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running
        begin
                if RST='1' then
                        infly<='0';
                        resfly<='0';
                        fftfly<='0';
                        resrdy<='0';
                        fftend<='0';
                        MODE<="00";
                elsif CLK='1' and CLK'event    then
                        if CE='1' then
                                if idatardy='1'then --iarrdy1='1'or FFTRDYi='1' then 
                                        infly<='1';
                                        MODE<="00";
                                elsif winend='1' then
                                        infly<='0';
                                        fftfly<='1';
                                        MODE<="01";
                                elsif FFTend='1' then
                                        fftfly<='0';
                                        if reall=1 then
                                                resfly<='1';
                                                MODE<="10";
                                        end if;
                                elsif resend='1' then
                                        resfly<='0';
                                        MODE<="00";
                                end if;
                                resrdy<=  startiterad0 and itera(n-1);
                        end if;
                end if;
                fftend<=  (enditera and itera(n-1)) ;
        end process;
 
        REXP:  process(CLK,RST)  --exponent counter               
        begin
                if RST='1' then
                        EXPi<=( others=>'0');
                        DIV2<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if winend='1' then
                                        EXPi<=( 0 =>OVERF, others=>'0');
                                        DIV2<= OVERF;
                                elsif enditera='1' or (fftend='1' and reall=1) then
                                        if OVERF = '1' then
                                                EXPi<=UNSIGNED(EXPi)+1;
                                                DIV2<='1';
                                        else
                                                DIV2<='0';
                                        end if;
                                elsif resend ='1' then
                                        DIV2<='0';
                                end if;
                        end if;
                end if;
        end process;
 
 
        WEI<=DATAE;
        WEd<=DATAE;
 
        ADDRWIN<=addrwidi;
 
 
 
        FFTRDY<=        FFTRDYi  after 3 ns;
        startitera<=   (enditera and not FFTRDYi) or winend;    --  idatardy;--
        WEM<=wewin when infly='1'
        else(wefft  and  fftfly);   --  and not itera(n-1)
 
 
 
        WERES<= WERESULTi when reall=0 else WERESwosst after 1 ns;
        ADDRRES<= ADDRWi when fftfly='1' and reall=0 else resnum ;
 
        ADDRR<=addrwosst  when resfly='1' else
        addrrwin when infly='1' else
        ADDRRi ;
 
        ADDRWM<=addrwwin  when infly='1'
        else ADDRWi;
 
        SELW<= not (FFTfly or resfly);
 
        INITOVERF<=startitera;-- and START;   
 
        ADDRROM<= addrwnd(n-2 downto 0) when infly='1'
        else ADDRROMi(n-2 downto 0) when fftfly='1'
        else (others=>'0');-- when oddci='1'     else '1'&nulls(n-3 downto 0);
 
        READY<=resrdy2 when reall=1 else resrdy  after 3 ns;
 
        EXP<=EXPi;
 
end CONTROL_slip;

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[/] [fft_fir_filter/] [trunk/] [rtl/] [control_slip.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`library IEEE;`
40			`use IEEE.std_logic_1164.all;`
41			`use IEEE.std_logic_arith.all;`
42
43			`entity CONTROL is`
44			`generic ( ifft:INTEGER:=0;`
45			`rams:INTEGER:=2;`
46			`n:INTEGER:=8; -- 6,7,8,9,10,11`
47			`slip:INTEGER;`
48			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
49			`);`
50			`port (`
51			`CLK: in STD_LOGIC;`
52			`RST: in STD_LOGIC;`
53			`CE: in STD_LOGIC;`
54			`START: in STD_LOGIC;`
55			`DATAE: in STD_LOGIC;`
56			`OVERF: in STD_LOGIC;`
57			`FFTRDY: out STD_LOGIC;`
58			`READY: out STD_LOGIC;`
59			`WE: out STD_LOGIC;`
60			`WEI: out STD_LOGIC;`
61			`WEM: out STD_LOGIC;`
62			`WERES: out STD_LOGIC;`
63			`--HRES: out STD_LOGIC;`
64			`INITOVERF: out STD_LOGIC;`
65			`-- SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
66			`ODDC: out STD_LOGIC;`
67			`EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
68			`DIV2: out STD_LOGIC;`
69			`ZWR: out STD_LOGIC;`
70			`ZWI: out STD_LOGIC;`
71			`SELW: out STD_LOGIC; --0 -twiddle 1 - window`
72			`SIGNRE: out STD_LOGIC;`
73			`MODE: out STD_LOGIC_VECTOR (1 downto 0);`
74			`EXP: out STD_LOGIC_VECTOR (3 downto 0);`
75			`ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0); -- data reading address`
76			`ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);--input data writing address`
77			`ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;--working data writing address`
78			`ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);--result address`
79			`ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)`
80			`);`
81			`end CONTROL;`
82
83
84
85			`architecture CONTROL_slip of CONTROL is`
86
87			`constant NN: INTEGER:=2**n;`
88			`constant lat: INTEGER:=7; --latency`
89			`constant lat2: INTEGER:=7; --latency in butterflies`
90			`constant one:INTEGER:=2**(n-1);`
91			`constant onehalf:INTEGER:=2**(n-2);`
92			`signal strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;`
93			`signal fftfly,infly,resfly: STD_LOGIC; --FFT run flag,input flag,result fag`
94			`signal resrdy, resrdy2,idatardy: STD_LOGIC; --FFT result ready flag`
95			`signal fftend,FFTRDYi: STD_LOGIC; --FFT end flag`
96			`signal enditera:STD_LOGIC; --end of iteration`
97			`signal incbfly: STD_LOGIC; -- +1 to reading data address`
98			`signal incbflyw: STD_LOGIC; -- +1 to writing data address`
99			`signal startitera: STD_LOGIC; -- iteration start`
100			`signal startiterad1: STD_LOGIC; -- iteration start`
101			`signal startiterad0: STD_LOGIC; -- iteration start`
102			`signal ODDCi: STD_LOGIC; -- 1 when odd clock cycle`
103			`signal startiterad2: STD_LOGIC; --delayed iteration start`
104			`signal wefft: STD_LOGIC; --we fft data`
105			`signal addrwid, addrwidi :STD_LOGIC_VECTOR(n-1 downto 0); --I. data writing address`
106			`signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address`
107			`signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number`
108			`signal ADDRRi: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address`
109			`signal ADDRwosst,addrrwin: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address`
110			`signal ADDRWi: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address`
111			`signal addres0,addres1: STD_LOGIC_VECTOR (n-1 downto 0);`
112			`signal resnum,resnumi:STD_LOGIC_VECTOR (n-1 downto 0);`
113			`signal ADDRWwin,ADDRwwini,ADDRwnd: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address`
114			`signal ADDRF: STD_LOGIC_VECTOR (n-2 downto 0); --data writing address`
115			`signal bflies: STD_LOGIC_VECTOR (n downto 0); --butterfly counter`
116			`signal startiterad: STD_LOGIC_VECTOR (lat downto 1);`
117			`signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0); -- increment to the factor address`
118			`signal EXPi: STD_LOGIC_VECTOR (3 downto 0);`
119			`signal ADDRROMi :STD_LOGIC_VECTOR (n-2 downto 0);`
120			`signal WERESULTi,wed: STD_LOGIC;`
121			`signal irdy:STD_LOGIC_VECTOR (1 downto 0);`
122			`signal ird,winend,wewin: STD_LOGIC;`
123			`signal inflyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);`
124			`signal fwd,fwdd,resend,resfld,wereswosst:STD_LOGIC;`
125			`constant nulls:STD_LOGIC_VECTOR (n-2 downto 0):=(others=>'0');`
126			`begin`
127
128
129			`CTIDATA:process(CLK,RST) -- data counter for input`
130			`begin`
131			`if RST='1' then`
132			`addrwidi<=(others=>'0');`
133			`addrwid<=(others=>'0');`
134			`irdy<="00";`
135			`ird<='0';`
136			`idatardy<= '0';`
137			`elsif CLK='1' and CLK'event then`
138			`if CE='1' then`
139			`if START='1' then -- or FFTRDYi='1'`
140			`addrwidi<= (others=>'0');`
141			`elsif DATAE='1' then --(strt='1' ) and or go='1' or god2='1'`
142			`irdy<="00";`
143			`if UNSIGNED(addrwidi)=NN-1 then`
144			`addrwidi<= (others=>'0');`
145			`irdy<="10";`
146			`else`
147			`addrwidi<=UNSIGNED(addrwidi)+1;`
148
149			`end if;`
150
151			`if UNSIGNED(addrwidi)=NN-1 then`
152			`irdy<="10";`
153			`elsif UNSIGNED(addrwidi)=NN/2-1 then`
154			`irdy<="01";`
155			`end if;`
156			`end if;`
157			`end if;`
158			`ird<= irdy(0)or irdy(1);`
159			`idatardy<= (irdy(0)or irdy(1)) and not ird;`
160			`end if;`
161			`end process;`
162
163			`CTRIDAT_W:process(CLK,RST,addrwwini) -- data counter for reading/writing to multiply by window`
164			`begin`
165			`if RST='1' then`
166			`addrrwin<=(others=>'0');`
167			`addrwnd<=(others=>'0');`
168			`addrwwini<=(others=>'0');`
169			`wewin<='0';`
170			`winend<='0';`
171			`EVEN<='1';`
172			`fwd<='1';`
173			`fwdd<='1';`
174			`winend<='0'; -- koniec umnozenia na okno`
175			`elsif CLK='1' and CLK'event then`
176			`if CE='1' then`
177			`EVEN<=not infly;`
178			`fwdd<=fwd;`
179			`inflyd<=inflyd(14 downto 0)& infly;`
180			`winend<='0';`
181			`if iarrdy='1' then -- or FFTRDYi='1'`
182			`fwd<='1';`
183			`addrrwin<= irdy(0)& nulls ;`
184			`addrwwini<=(others=>'0');`
185			`addrwnd<=(others=>'0');`
186			`elsif infly='1' then`
187			`addrrwin<=UNSIGNED(addrrwin)+1;`
188			`if UNSIGNED(addrrwin(n-2 downto 0))= nn/2-2 then`
189			`fwd<='0';`
190			`end if;`
191			`if fwd='1' then`
192			`addrwnd<=UNSIGNED(addrwnd)+1;--address okna`
193			`elsif fwdd='0' then`
194			`addrwnd<=UNSIGNED(addrwnd)-1;`
195			`end if;`
196			`if UNSIGNED(addrwnd)= nn-3 and fwd='0' then ---4`
197			`winend<='1'; --konec umnozenia na okno`
198			`end if;`
199			`end if;`
200			`if wewin='1' then -- inflyd(4)='1'`
201			`addrwwini<=UNSIGNED(addrwwini)+1;`
202			`end if;`
203			`wewin<=inflyd(3); --(4)`
204			`end if;`
205			`end if;`
206			`for i in 0 to n-1 loop`
207			`addrwwin(i)<=addrwwini(n-i-1); --addrwwini(i);-- --2-th inverse writing address`
208			`end loop;`
209			`end process;`
210
211
212
213			`CTLAT:process(RST,CLK) --delay on 1 LUT`
214			`begin`
215			`if RST='1' then`
216			`startiterad1<='0';`
217			`startiterad2<='0';`
218			`elsif CLK='1' and CLK'event then`
219			`if CE='1' then`
220			`startiterad1<=startitera;`
221			`startiterad2<=startiterad0;`
222			`end if;`
223			`end if;`
224			`end process;`
225
226			`CTLATS:process(RST,CLK) --delay on 1 LUT`
227			`begin`
228			`if CLK='1' and CLK'event then`
229			`if CE='1' then`
230			`startiterad<=startiterad(lat-1 downto 1)&startitera;`
231			`end if;`
232			`end if;`
233			`end process;`
234			`startiterad0<= startiterad(lat);`
235
236
237			`TODDC:process(CLK,RST) --odd cycle for FFT`
238			`begin`
239			`if RST='1' then`
240			`ODDCi<='0';`
241			`elsif CLK='1' and CLK'event then`
242			`if CE='1' then`
243			`if startitera='1' or FFTend='1' or resend='1' then`
244			`ODDCi<='0';`
245			`elsif fftfly='1' or resfly='1' then`
246			`ODDCi<= not ODDCi;`
247			`end if;`
248			`end if;`
249			`end if;`
250			`end process;`
251
252			`ODDC<= ODDCi;`
253
254			`CTRADDR:process(CLK,RST,ADDRRi) --FFT read counter`
255			`variable sum:STD_LOGIC_VECTOR (n downto 0);`
256			`variable inc:STD_LOGIC;`
257			`begin`
258			`if RST='1' then`
259			`incbfly<='0';`
260			`ADDRRi<=( others=>'0');`
261			`elsif CLK='1' and CLK'event then`
262			`if CE='1' then`
263			`if startitera='1' then`
264			`ADDRRi<=( others=>'0');`
265			`elsif fftfly='1' then`
266			`sum:=UNSIGNED('0'&ADDRRi)+UNSIGNED(itera);`
267			`inc:= sum(n);`
268			`ADDRRi<=UNSIGNED(sum(n-1 downto 0))+inc;`
269			`incbfly<=inc;`
270			`end if;`
271			`end if;`
272			`end if;`
273			`end process;`
274
275			`CTWADDR:process(CLK,RST,ADDRWi) --FFT write counter`
276			`variable sum:STD_LOGIC_VECTOR (n downto 0);`
277			`variable inc:STD_LOGIC;`
278			`begin`
279			`if RST='1' then`
280			`ADDRWi<=( others=>'0');`
281			`elsif CLK='1' and CLK'event then`
282			`if CE='1' then`
283			`if startiterad2='1' then`
284			`ADDRWi<=( others=>'0');`
285			`elsif fftfly='1' then`
286			`sum:=UNSIGNED('0'&ADDRWi)+UNSIGNED(itera);`
287			`inc:= sum(n);`
288			`ADDRWi<=UNSIGNED(sum(n-1 downto 0))+inc;`
289			`end if;`
290			`end if;`
291			`end if;`
292			`end process;`
293
294			`LINCADDRF:process(itera)`
295			`begin`
296			`for i in 0 to n-2 loop`
297			`incaddrf(i)<=itera(n-1-i);`
298			`end loop;`
299			`end process;`
300
301			`CTADDRF: process(CLK,RST) --iteration counter`
302			`begin`
303			`if RST='1' then`
304			`ADDRF<=( others=>'0');`
305			`elsif CLK='1' and CLK'event then`
306			`if CE='1' then`
307			`if startiterad1='1' then`
308			`ADDRF<=( others=>'0');`
309			`elsif fftfly='1' and incbfly = '1' then`
310			`ADDRF<=UNSIGNED(ADDRF)+UNSIGNED(incaddrf);`
311			`end if;`
312			`end if;`
313			`end if;`
314			`end process;`
315
316
317
318			`FADDRROM:process(CLK,RST)`
319			`begin`
320			`if RST='1' then`
321			`SIGNRE<='0';`
322			`ZWR<='0';`
323			`ZWI<='0';`
324			`ADDRROMi<=( others=>'0');`
325			`elsif CLK='1' and CLK'event then`
326			`if CE='1' then`
327			`if UNSIGNED(ADDRF)=onehalf then`
328			`ZWR<='1';`
329			`else`
330			`ZWR<='0';`
331			`end if;`
332
333			`if UNSIGNED(ADDRF)=0 or resfly='1' then`
334			`ZWI<='1';`
335			`else`
336			`ZWI<='0';`
337			`end if;`
338
339			`if ODDCi='1' then --cosine address`
340			`if ADDRF(n-2)='0' then`
341			`ADDRROMi<='0'&ADDRF(n-3 downto 0);`
342			`SIGNRE<='0';`
343			`else`
344			`ADDRROMi<=onehalf-UNSIGNED('0'&ADDRF(n-3 downto 0));`
345			`SIGNRE<='1';`
346			`end if;`
347
348			`else -- sine address`
349			`if ADDRF(n-2)='0' then`
350			`ADDRROMi<=onehalf -UNSIGNED('0'&ADDRF(n-3 downto 0));`
351			`else`
352			`ADDRROMi<='0'&ADDRF(n-3 downto 0);`
353			`end if;`
354			`end if;`
355			`end if;`
356			`end if;`
357			`end process;`
358
359
360			`CTBFLIES:process(CLK,RST,bflies) --butterfly counter`
361			`begin`
362			`if RST='1' then`
363			`wefft<='0';`
364			`enditera<='0';`
365			`bflies<=( others=>'0');`
366			`WERESULTi<='0';`
367			`FFTRDYi<='0';`
368			`elsif CLK='1' and CLK'event then`
369			`if CE='1' then`
370
371			`if startiterad2='1' then`
372			`wefft<='1';`
373			`if itera(n-1)='1'then`
374			`WERESULTi<='1';`
375			`end if;`
376			`end if;`
377
378			`if startitera='1' then`
379			`bflies<=( others=>'0');`
380			`elsif fftfly='1'`
381			`then`
382			`bflies<=UNSIGNED(bflies)+1;`
383			`end if;`
384
385			`if idatardy ='1' and go ='0' then`
386			`FFTRDYi<='1';`
387			`elsif UNSIGNED(bflies)=nn + lat2 and enditera='0' then`
388			`enditera<='1';`
389			`wefft<='0';`
390			`WERESULTi<='0';`
391			`if itera(n-1)='1' then`
392			`FFTRDYi<='1';`
393			`end if;`
394			`else`
395			`enditera<='0';`
396			`FFTRDYi<='0';`
397			`end if;`
398			`end if;`
399			`end if;`
400			`end process;`
401
402			`TIARRDY:process(CLK,RST) --1st input data ready`
403			`begin`
404			`if RST='1' then`
405			`iarrdy<='0';`
406			`iarrdy1<='0';`
407			`go<='0';`
408			`god<='0';`
409			`god2<='0';`
410			`elsif CLK='1' and CLK'event then`
411			`if CE='1' then`
412			`if START='1' then`
413			`iarrdy<='0';`
414			`iarrdy1<='0';`
415			`go<='0';`
416			`elsif idatardy='1' then`
417			`iarrdy<='1';`
418			`go<='1';`
419			`god<='0';`
420			`if go='0'`
421			`then`
422			`iarrdy1<='1';`
423			`end if;`
424
425			`else`
426			`god2<=god;`
427			`iarrdy<='0';`
428			`iarrdy1<='0';`
429			`if FFTRDYi='1' then`
430			`god<='1' ;`
431			`end if;`
432			`end if;`
433			`end if;`
434			`end if;`
435			`end process;`
436
437			`CTITERA:process(CLK,RST) --iteration counter`
438			`begin`
439			`if RST='1' then`
440			`itera<=CONV_STD_LOGIC_VECTOR(1,n);`
441			`elsif CLK='1' and CLK'event then`
442			`if CE='1' then`
443			`if FFTRDYi='1' then`
444			`itera<=CONV_STD_LOGIC_VECTOR(1,n);`
445			`elsif enditera='1' then`
446			`itera<=itera(n-2 downto 0)&'0';`
447			`end if;`
448			`end if;`
449			`end if;`
450			`end process;`
451
452
453			`CTWOSST:process(CLK,RST) -- data counters for wosstanowlenija`
454			`begin`
455			`if RST='1' then`
456			`addres0<=(others=>'0');`
457			`addres1<=(others=>'0');`
458			`resnumi<=(others=>'0');`
459			`resend<='0';`
460			`resfld<='0';`
461			`-- WERESwosst<='0';`
462			`elsif CLK='1' and CLK'event then`
463			`resend<='0';`
464			`if CE='1' then`
465			`resflyd<=resflyd(14 downto 0)& resfly;`
466			`resfld<=resflyd(6);`
467
468			`if fftend='1' then -- or FFTRDYi='1'`
469			`addres0<= (others=>'0');`
470			`addres1<= (others=>'0'); -- conv_std_logic_vector(NN,n+1);`
471			`resnumi<=(others=>'0');`
472
473			`elsif resfly='1' then`
474
475			`if oddci='1' then`
476			`addres0<=UNSIGNED(addres0)+1;`
477			`addres1<=UNSIGNED(addres1)-1;`
478			`end if;`
479
480			`if resfld='1' and resfly='1' then`
481			`resnumi<=UNSIGNED(resnumi)+1;`
482			`end if;`
483			`if UNSIGNED(resnumi)=nn-2 then ---1`
484			`resend<='1';`
485			`end if;`
486			`end if;`
487			`end if;`
488			`end if;`
489			`end process;`
490
491			`WERESwosst<=resfld and resfly;`
492			`addrwosst<=addres0 when oddci='1' else addres1(n-1 downto 0);`
493			`resnum<=resnumi(0)&resnumi(n-1 downto 1);`
494			`resrdy2<=resflyd(6) and not resfld;`
495
496			`TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running`
497			`begin`
498			`if RST='1' then`
499			`infly<='0';`
500			`resfly<='0';`
501			`fftfly<='0';`
502			`resrdy<='0';`
503			`fftend<='0';`
504			`MODE<="00";`
505			`elsif CLK='1' and CLK'event then`
506			`if CE='1' then`
507			`if idatardy='1'then --iarrdy1='1'or FFTRDYi='1' then`
508			`infly<='1';`
509			`MODE<="00";`
510			`elsif winend='1' then`
511			`infly<='0';`
512			`fftfly<='1';`
513			`MODE<="01";`
514			`elsif FFTend='1' then`
515			`fftfly<='0';`
516			`if reall=1 then`
517			`resfly<='1';`
518			`MODE<="10";`
519			`end if;`
520			`elsif resend='1' then`
521			`resfly<='0';`
522			`MODE<="00";`
523			`end if;`
524			`resrdy<= startiterad0 and itera(n-1);`
525			`end if;`
526			`end if;`
527			`fftend<= (enditera and itera(n-1)) ;`
528			`end process;`
529
530			`REXP: process(CLK,RST) --exponent counter`
531			`begin`
532			`if RST='1' then`
533			`EXPi<=( others=>'0');`
534			`DIV2<='0';`
535			`elsif CLK='1' and CLK'event then`
536			`if CE='1' then`
537			`if winend='1' then`
538			`EXPi<=( 0 =>OVERF, others=>'0');`
539			`DIV2<= OVERF;`
540			`elsif enditera='1' or (fftend='1' and reall=1) then`
541			`if OVERF = '1' then`
542			`EXPi<=UNSIGNED(EXPi)+1;`
543			`DIV2<='1';`
544			`else`
545			`DIV2<='0';`
546			`end if;`
547			`elsif resend ='1' then`
548			`DIV2<='0';`
549			`end if;`
550			`end if;`
551			`end if;`
552			`end process;`
553
554
555			`WEI<=DATAE;`
556			`WEd<=DATAE;`
557
558			`ADDRWIN<=addrwidi;`
559
560
561
562			`FFTRDY<= FFTRDYi after 3 ns;`
563			`startitera<= (enditera and not FFTRDYi) or winend; -- idatardy;--`
564			`WEM<=wewin when infly='1'`
565			`else(wefft and fftfly); -- and not itera(n-1)`
566
567
568
569			`WERES<= WERESULTi when reall=0 else WERESwosst after 1 ns;`
570			`ADDRRES<= ADDRWi when fftfly='1' and reall=0 else resnum ;`
571
572			`ADDRR<=addrwosst when resfly='1' else`
573			`addrrwin when infly='1' else`
574			`ADDRRi ;`
575
576			`ADDRWM<=addrwwin when infly='1'`
577			`else ADDRWi;`
578
579			`SELW<= not (FFTfly or resfly);`
580
581			`INITOVERF<=startitera;-- and START;`
582
583			`ADDRROM<= addrwnd(n-2 downto 0) when infly='1'`
584			`else ADDRROMi(n-2 downto 0) when fftfly='1'`
585			`else (others=>'0');-- when oddci='1' else '1'&nulls(n-3 downto 0);`
586
587			`READY<=resrdy2 when reall=1 else resrdy after 3 ns;`
588
589			`EXP<=EXPi;`
590
591			`end CONTROL_slip;`