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[/] [fft_fir_filter/] [trunk/] [rtl/] [fft_filtr2.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
--              DESCRIPTION:
--
--      FUNCTION         FFT filter for FFT length of
--                       N= 64, 128, 256, 512, 1024, 2048 points,
--                       N= 2**n,
--                       ifft=0 forward FFT, =1 inverse FFT
--                       rams=1 - single data RAM, =2 dual data RAM
--                       input data width: iwidth = 8,...,16 bit   signed 
--                                             output   data width: owidth = 8,...,16 bit   signed     
--                       coefficient width : wwidth = 8,...,16 bit
--                                  Synthesable for Virtex2, Spartan3 FPGAs. 
--             
--      FILES:          FFT_Filtr2.VHD -- this file
--             ALFFT_Core_slip.vhd - Slipping FFT with windowing
--               FFTDPATH.vhd   - data path of the FFT butterfly                 
--               CONTROL.vhd   - control unit of FFT processor       
--                                    ROM_COS.vhd   -   coefficient ROM
--                                   RAM2X_2.vhd   -  dual data RAM block            
--              ALFFT_Core_sli.vhd - file of IFFT processor
--               FFTDPATHi.vhd   - data path of the IFFT butterfly                       
--               CONTROL_i.vhd   - control unit of IFFT processor      
--                                    ROM_COSi.vhd   -  coefficient ROM
--                                   RAM1X_2.vhd   - data RAM block    
--             DENORM.vhd  -- denormalizer unit
--                  When redesign data RAM blocks
--                     the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
Use     IEEE.std_logic_arith.all;
 
entity FFT_FILTER2 is
        generic (
                iwidth: INTEGER:=8      ;               --  input data width =8...16
                owidth: INTEGER:=8      ;       -- output data width =8...16
                wwidth: INTEGER:=8;                     --  coefficient width =8...16  
                n:INTEGER:=7 ;                  -- 6,7,8,9,10,11   - transform length factor
                v2:INTEGER:=1 ; -- 1 - Virtex2
                reall:INTEGER:= 1  --wch. mass: 0 -complex 1 - 2 realnych
                );
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;         -- ����� ��������� (���������� �LK)
                START: in STD_LOGIC; -- ������� ���������� �����
                DATAE: in STD_LOGIC; -- ����� ������� ������
                FILTER: in STD_LOGIC_VECTOR (1 downto 0);                --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- ������� ���1
                H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- ������� ���1
                L2:in STD_LOGIC_VECTOR (n-1 downto 0); -- ������� ���2
                H2:in STD_LOGIC_VECTOR (n-1 downto 0); -- ������� ���2
 
                DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--���� 1 �������
                DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--���� 2 �������
                READY: out STD_LOGIC;              --������� ������ ������ ������� ���������� 
                DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--����� 1 �������
                DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--����� 2 �������
 
                SPRDY: out STD_LOGIC;           --������� ������ ������ �������
                WESP: out STD_LOGIC;       -- ����� �������� �������
                SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--�������� ����� ��������
                SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--������ ����� ��������
                FREQ:out STD_LOGIC_VECTOR (n-1 downto 0); --����� ����
                SPEXP:out STD_LOGIC_VECTOR (3 downto 0)    --������� ������� ��������
                );
end FFT_FILTER2;
 
architecture ALFFT_CoreS of FFT_Filter2 is
 
        component  ALFFT_Core is
                generic (       ifft: INTEGER:=0;            --  0- forward FFT
                        rams:INTEGER:=2;   -- 1,2
                        iwidth: INTEGER:=8      ;               --  input data width =8...16
                        owidth: INTEGER:=8      ;       -- output data width =8...16
                        wwidth: INTEGER:=8;                     --  coefficient width =8...16  
                        n:INTEGER:=7 ;
                        v2:INTEGER:=1 ; -- 1 - Virtex2
                        slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2 
                        wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija
                        reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                        );  --4,5, 6,7,8,9,10,11   - transform length factor
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        START: in STD_LOGIC;
                        DATAE: in STD_LOGIC;
                        DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
                        FFTRDY: out STD_LOGIC;
                        READY: out STD_LOGIC;
                        WERES: out STD_LOGIC;
                        ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);
                        DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                        DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
                        EXP: out STD_LOGIC_VECTOR (3 downto 0)
                        );
        end component;
 
        component ALFFT_Corei is
                generic (width: INTEGER:=8      ;       -- output data width =8...16
                        wwidth: INTEGER:=8;                     --  coefficient width =8...16  
                        n:INTEGER:=7 ;
                        v2:INTEGER:=1 ; -- 1 - Virtex2
                        reall:INTEGER:= 0  --wch. mass: 0 -complex 1 - 2 realnych
                        );  --4,5, 6,7,8,9,10,11   - transform length factor
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        START: in STD_LOGIC;
                        FILTER: in STD_LOGIC_VECTOR (1 downto 0);                --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                        L1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                        H1:in STD_LOGIC_VECTOR (n-1 downto 0);            -- tsastoty filtrow
                        L2:in STD_LOGIC_VECTOR (n-1 downto 0);
                        H2:in STD_LOGIC_VECTOR (n-1 downto 0);
                        DATAE: in STD_LOGIC;
                        DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                        DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                        FFTRDY: out STD_LOGIC;
                        READY: out STD_LOGIC;
                        WERES: out STD_LOGIC;
                        ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);
                        DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                        DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);
                        EXP: out STD_LOGIC_VECTOR (3 downto 0)
                        );
        end component ;
        component DENORM is
                generic (width: integer :=8     ;       --  word width =8...24
                        n:INTEGER:=7 ;
                        reall:INTEGER:= 0 ;
                        v2:INTEGER:=1 );-- 1 - Virtex2
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        CE: in STD_LOGIC;
                        DATAE: in STD_LOGIC;
                        START: in STD_LOGIC;      -- 
                        INIT: in STD_LOGIC;      -- 
                        WERES: in STD_LOGIC;
                        SPRDY: in STD_LOGIC;
                        ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);
                        EXPI: in STD_LOGIC_VECTOR (3 downto 0);
                        EXPF: in STD_LOGIC_VECTOR (3 downto 0);
                        REDI: in STD_LOGIC_VECTOR (width-1 downto 0);
                        IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);
                        RDY: out STD_LOGIC;
                        REDO: out STD_LOGIC_VECTOR (width-1 downto 0);
                        IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)
                        );
        end     component;
 
        signal          REDI:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          IMDI:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          IMDO:  STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal          INITOVERF:     STD_LOGIC;
        signal          WEspi:  STD_LOGIC;
        signal          sprdyi: STD_LOGIC;
        signal          WEres: STD_LOGIC;
        signal          fftrdy,ifftrdy:  STD_LOGIC;                                                                       -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM 
        signal          EVEN:  STD_LOGIC;                        --0- 0th bank 1- 1st bank -for DIRE,DIIM
        signal          ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
        signal      MODE: STD_LOGIC_VECTOR (1 downto 0);
        signal     SPREi,SPIMi,DRE,DIM:STD_LOGIC_VECTOR (owidth-1 downto 0);
        signal    EXPF,EXPI:STD_LOGIC_VECTOR (3 downto 0);
        signal     addrres,address: STD_LOGIC_VECTOR (n-1 downto 0);
        signal DIRE,DIIM:    STD_LOGIC_VECTOR (iwidth-1 downto 0);
        constant vcc:STD_LOGIC:='1';
        signal sno1,sno2,sno3:integer;
 
begin
 
        DIRE<=DATAIRE;-- & zeros;
        DIIM<=DATAIIM;-- & zeros;
 
        FFT_F:   ALFFT_Core
        generic map     (ifft=>0,            --  0- forward FFT
                rams=>2,   -- 1,2
                iwidth=>iwidth,         --  input data width =8...16
                owidth=>owidth,         -- output data width =8...16
                wwidth=>wwidth,                         --  coefficient width =8...16  
                n=>n,
                v2=>v2, -- 1 - Virtex2
                slip=> 2, -- 2 -- skolzassij s perekrytiem 2 
                wnd=> 1, -- umnozaecca na okno 1 ,0 -bez umnozenija
                reall=>reall  --wch. mass: 0 -complex 1 - 2 realnych
                )  --4,5, 6,7,8,9,10,11   - transform length factor
        port map (CLK,RST,CE,
                START=>START,
                DATAE=>DATAE,
                DATAIRE=>DIRE,
                DATAIIM=>DIIM,
                FFTRDY=>fftrdy,
                READY=>sprdyi,
                WERES=>wespi,
                ADDRRES=>address,
                DATAORE=>SPREi,
                DATAOIM=>SPIMi,
                EXP=>expf
                );
 
 
                WESP<=wespi;     -- spectr data output 
                SPRDY<=sprdyi;
                SPRE<=SPREi;
                SPIM<=SPIMi;
                SPEXP<=expf;
                FREQ<=address;
 
        FFT_I:   ALFFT_Corei
        generic map     (width=>owidth,         -- output data width =8...16
                wwidth=>wwidth,                         --  coefficient width =8...16  
                n=>n,
                v2=>v2, -- 1 - Virtex2
                reall=>reall  --wch. mass: 0 -complex 1 - 2 realnych
                )  --4,5, 6,7,8,9,10,11   - transform length factor
        port map(CLK,RST,CE,
                START=>sprdyi,
                FILTER=>FILTER,         --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
                L1=>L1,          -- tsastoty filtrow
                H1=>H1,          -- tsastoty filtrow
                L2=>L2,
                H2=>H2,
                DATAE=>wespi,
                DATAIRE=>SPREi,
                DATAIIM=>SPIMi,
                FFTRDY=>open,
                READY=>ifftrdy,
                WERES=>weres,
                ADDRRES=>addrres,
                DATAORE=>DRE,
                DATAOIM=>DIM,
                EXP=>EXPi
                );
 
 
        U_OUT: DENORM
        generic  map(width=>owidth,     --  word width =8...24
                n=>n,
                reall=>reall,
                v2=>v2)
        port map(CLK,RST,CE,
                DATAE=>DATAE,
                START=>start,
                INIT=> ifftrdy,
                WERES=>weres,
                ADDRRES=>addrres,
                SPRDY=>SPRDYi,
                EXPI=>expi,
                EXPF=>expf,
                REDI=>DRE,
                IMDI=>DIM,
                RDY=>READY,
                REDO=>REDO,
                IMDO=>IMDO
                );
 
        DATAORE<=REDO ;
        DATAOIM<=IMDO ;
 
 
end ALFFT_CoreS;

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Subversion Repositories fft_fir_filter

[/] [fft_fir_filter/] [trunk/] [rtl/] [fft_filtr2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
40			`-- DESCRIPTION:`
41			`--`
42			`-- FUNCTION FFT filter for FFT length of`
43			`-- N= 64, 128, 256, 512, 1024, 2048 points,`
44			`-- N= 2**n,`
45			`-- ifft=0 forward FFT, =1 inverse FFT`
46			`-- rams=1 - single data RAM, =2 dual data RAM`
47			`-- input data width: iwidth = 8,...,16 bit signed`
48			`-- output data width: owidth = 8,...,16 bit signed`
49			`-- coefficient width : wwidth = 8,...,16 bit`
50			`-- Synthesable for Virtex2, Spartan3 FPGAs.`
51			`--`
52			`-- FILES: FFT_Filtr2.VHD -- this file`
53			`-- ALFFT_Core_slip.vhd - Slipping FFT with windowing`
54			`-- FFTDPATH.vhd - data path of the FFT butterfly`
55			`-- CONTROL.vhd - control unit of FFT processor`
56			`-- ROM_COS.vhd - coefficient ROM`
57			`-- RAM2X_2.vhd - dual data RAM block`
58			`-- ALFFT_Core_sli.vhd - file of IFFT processor`
59			`-- FFTDPATHi.vhd - data path of the IFFT butterfly`
60			`-- CONTROL_i.vhd - control unit of IFFT processor`
61			`-- ROM_COSi.vhd - coefficient ROM`
62			`-- RAM1X_2.vhd - data RAM block`
63			`-- DENORM.vhd -- denormalizer unit`
64			`-- When redesign data RAM blocks`
65			`-- the Core will fit another FPGA families`
66			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--`
67
68			`library IEEE;`
69			`use IEEE.std_logic_1164.all;`
70			`Use IEEE.std_logic_arith.all;`
71
72			`entity FFT_FILTER2 is`
73			`generic (`
74			`iwidth: INTEGER:=8 ; -- input data width =8...16`
75			`owidth: INTEGER:=8 ; -- output data width =8...16`
76			`wwidth: INTEGER:=8; -- coefficient width =8...16`
77			`n:INTEGER:=7 ; -- 6,7,8,9,10,11 - transform length factor`
78			`v2:INTEGER:=1 ; -- 1 - Virtex2`
79			`reall:INTEGER:= 1 --wch. mass: 0 -complex 1 - 2 realnych`
80			`);`
81			`port (`
82			`CLK: in STD_LOGIC;`
83			`RST: in STD_LOGIC;`
84			`CE: in STD_LOGIC; -- �� (�� LK)`
85			`START: in STD_LOGIC; -- �� `
86			`DATAE: in STD_LOGIC; -- �� `
87			`FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
88			`L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- �� 1`
89			`H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- �� 1`
90			`L2:in STD_LOGIC_VECTOR (n-1 downto 0); -- �� 2`
91			`H2:in STD_LOGIC_VECTOR (n-1 downto 0); -- �� 2`
92
93			`DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--�� 1 ��`
94			`DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--�� 2 ��`
95			`READY: out STD_LOGIC; --�� `
96			`DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--�� 1 ��`
97			`DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--�� 2 ��`
98
99			`SPRDY: out STD_LOGIC; --�� `
100			`WESP: out STD_LOGIC; -- �� `
101			`SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--�� `
102			`SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--�� `
103			`FREQ:out STD_LOGIC_VECTOR (n-1 downto 0); --�� `
104			`SPEXP:out STD_LOGIC_VECTOR (3 downto 0) --�� `
105			`);`
106			`end FFT_FILTER2;`
107
108			`architecture ALFFT_CoreS of FFT_Filter2 is`
109
110			`component ALFFT_Core is`
111			`generic ( ifft: INTEGER:=0; -- 0- forward FFT`
112			`rams:INTEGER:=2; -- 1,2`
113			`iwidth: INTEGER:=8 ; -- input data width =8...16`
114			`owidth: INTEGER:=8 ; -- output data width =8...16`
115			`wwidth: INTEGER:=8; -- coefficient width =8...16`
116			`n:INTEGER:=7 ;`
117			`v2:INTEGER:=1 ; -- 1 - Virtex2`
118			`slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2`
119			`wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija`
120			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
121			`); --4,5, 6,7,8,9,10,11 - transform length factor`
122			`port (`
123			`CLK: in STD_LOGIC;`
124			`RST: in STD_LOGIC;`
125			`CE: in STD_LOGIC;`
126			`START: in STD_LOGIC;`
127			`DATAE: in STD_LOGIC;`
128			`DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
129			`DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);`
130			`FFTRDY: out STD_LOGIC;`
131			`READY: out STD_LOGIC;`
132			`WERES: out STD_LOGIC;`
133			`ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);`
134			`DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
135			`DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);`
136			`EXP: out STD_LOGIC_VECTOR (3 downto 0)`
137			`);`
138			`end component;`
139
140			`component ALFFT_Corei is`
141			`generic (width: INTEGER:=8 ; -- output data width =8...16`
142			`wwidth: INTEGER:=8; -- coefficient width =8...16`
143			`n:INTEGER:=7 ;`
144			`v2:INTEGER:=1 ; -- 1 - Virtex2`
145			`reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych`
146			`); --4,5, 6,7,8,9,10,11 - transform length factor`
147			`port (`
148			`CLK: in STD_LOGIC;`
149			`RST: in STD_LOGIC;`
150			`CE: in STD_LOGIC;`
151			`START: in STD_LOGIC;`
152			`FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
153			`L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
154			`H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow`
155			`L2:in STD_LOGIC_VECTOR (n-1 downto 0);`
156			`H2:in STD_LOGIC_VECTOR (n-1 downto 0);`
157			`DATAE: in STD_LOGIC;`
158			`DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
159			`DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
160			`FFTRDY: out STD_LOGIC;`
161			`READY: out STD_LOGIC;`
162			`WERES: out STD_LOGIC;`
163			`ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);`
164			`DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
165			`DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);`
166			`EXP: out STD_LOGIC_VECTOR (3 downto 0)`
167			`);`
168			`end component ;`
169			`component DENORM is`
170			`generic (width: integer :=8 ; -- word width =8...24`
171			`n:INTEGER:=7 ;`
172			`reall:INTEGER:= 0 ;`
173			`v2:INTEGER:=1 );-- 1 - Virtex2`
174			`port (`
175			`CLK: in STD_LOGIC;`
176			`RST: in STD_LOGIC;`
177			`CE: in STD_LOGIC;`
178			`DATAE: in STD_LOGIC;`
179			`START: in STD_LOGIC; --`
180			`INIT: in STD_LOGIC; --`
181			`WERES: in STD_LOGIC;`
182			`SPRDY: in STD_LOGIC;`
183			`ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);`
184			`EXPI: in STD_LOGIC_VECTOR (3 downto 0);`
185			`EXPF: in STD_LOGIC_VECTOR (3 downto 0);`
186			`REDI: in STD_LOGIC_VECTOR (width-1 downto 0);`
187			`IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);`
188			`RDY: out STD_LOGIC;`
189			`REDO: out STD_LOGIC_VECTOR (width-1 downto 0);`
190			`IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)`
191			`);`
192			`end component;`
193
194			`signal REDI: STD_LOGIC_VECTOR (owidth-1 downto 0);`
195			`signal IMDI: STD_LOGIC_VECTOR (owidth-1 downto 0);`
196			`signal REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);`
197			`signal IMDO: STD_LOGIC_VECTOR (owidth-1 downto 0);`
198			`signal INITOVERF: STD_LOGIC;`
199			`signal WEspi: STD_LOGIC;`
200			`signal sprdyi: STD_LOGIC;`
201			`signal WEres: STD_LOGIC;`
202			`signal fftrdy,ifftrdy: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
203			`signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM`
204			`signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);`
205			`signal MODE: STD_LOGIC_VECTOR (1 downto 0);`
206			`signal SPREi,SPIMi,DRE,DIM:STD_LOGIC_VECTOR (owidth-1 downto 0);`
207			`signal EXPF,EXPI:STD_LOGIC_VECTOR (3 downto 0);`
208			`signal addrres,address: STD_LOGIC_VECTOR (n-1 downto 0);`
209			`signal DIRE,DIIM: STD_LOGIC_VECTOR (iwidth-1 downto 0);`
210			`constant vcc:STD_LOGIC:='1';`
211			`signal sno1,sno2,sno3:integer;`
212
213			`begin`
214
215			`DIRE<=DATAIRE;-- & zeros;`
216			`DIIM<=DATAIIM;-- & zeros;`
217
218			`FFT_F: ALFFT_Core`
219			`generic map (ifft=>0, -- 0- forward FFT`
220			`rams=>2, -- 1,2`
221			`iwidth=>iwidth, -- input data width =8...16`
222			`owidth=>owidth, -- output data width =8...16`
223			`wwidth=>wwidth, -- coefficient width =8...16`
224			`n=>n,`
225			`v2=>v2, -- 1 - Virtex2`
226			`slip=> 2, -- 2 -- skolzassij s perekrytiem 2`
227			`wnd=> 1, -- umnozaecca na okno 1 ,0 -bez umnozenija`
228			`reall=>reall --wch. mass: 0 -complex 1 - 2 realnych`
229			`) --4,5, 6,7,8,9,10,11 - transform length factor`
230			`port map (CLK,RST,CE,`
231			`START=>START,`
232			`DATAE=>DATAE,`
233			`DATAIRE=>DIRE,`
234			`DATAIIM=>DIIM,`
235			`FFTRDY=>fftrdy,`
236			`READY=>sprdyi,`
237			`WERES=>wespi,`
238			`ADDRRES=>address,`
239			`DATAORE=>SPREi,`
240			`DATAOIM=>SPIMi,`
241			`EXP=>expf`
242			`);`
243
244
245			`WESP<=wespi; -- spectr data output`
246			`SPRDY<=sprdyi;`
247			`SPRE<=SPREi;`
248			`SPIM<=SPIMi;`
249			`SPEXP<=expf;`
250			`FREQ<=address;`
251
252			`FFT_I: ALFFT_Corei`
253			`generic map (width=>owidth, -- output data width =8...16`
254			`wwidth=>wwidth, -- coefficient width =8...16`
255			`n=>n,`
256			`v2=>v2, -- 1 - Virtex2`
257			`reall=>reall --wch. mass: 0 -complex 1 - 2 realnych`
258			`) --4,5, 6,7,8,9,10,11 - transform length factor`
259			`port map(CLK,RST,CE,`
260			`START=>sprdyi,`
261			`FILTER=>FILTER, --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff`
262			`L1=>L1, -- tsastoty filtrow`
263			`H1=>H1, -- tsastoty filtrow`
264			`L2=>L2,`
265			`H2=>H2,`
266			`DATAE=>wespi,`
267			`DATAIRE=>SPREi,`
268			`DATAIIM=>SPIMi,`
269			`FFTRDY=>open,`
270			`READY=>ifftrdy,`
271			`WERES=>weres,`
272			`ADDRRES=>addrres,`
273			`DATAORE=>DRE,`
274			`DATAOIM=>DIM,`
275			`EXP=>EXPi`
276			`);`
277
278
279			`U_OUT: DENORM`
280			`generic map(width=>owidth, -- word width =8...24`
281			`n=>n,`
282			`reall=>reall,`
283			`v2=>v2)`
284			`port map(CLK,RST,CE,`
285			`DATAE=>DATAE,`
286			`START=>start,`
287			`INIT=> ifftrdy,`
288			`WERES=>weres,`
289			`ADDRRES=>addrres,`
290			`SPRDY=>SPRDYi,`
291			`EXPI=>expi,`
292			`EXPF=>expf,`
293			`REDI=>DRE,`
294			`IMDI=>DIM,`
295			`RDY=>READY,`
296			`REDO=>REDO,`
297			`IMDO=>IMDO`
298			`);`
299
300			`DATAORE<=REDO ;`
301			`DATAOIM<=IMDO ;`
302
303
304			`end ALFFT_CoreS;`