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[/] [fft_fir_filter/] [trunk/] [rtl/] [ram1x_2.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  FFT Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity RAM1X_2 is
        generic(width : INTEGER;
                n:INTEGER;        -- 6,7,8,9,10,11
                v2:INTEGER:=1);
        port (
                CLK: in STD_LOGIC;
                RST: in STD_LOGIC;
                CE: in STD_LOGIC;
                WE: in STD_LOGIC;
                INITOVERF:    in STD_LOGIC;
                ADDRW: in STD_LOGIC_VECTOR (n downto 0);
                ADDRR: in STD_LOGIC_VECTOR (n downto 0);
                SEL: in STD_LOGIC;                                                                        -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
                RESRAM:  in STD_LOGIC;
                DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
                DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
                OVERF:out  STD_LOGIC;
                DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
                DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
                );
end RAM1X_2;
 
 
architecture RAM1X of RAM1X_2 is
 
        component RAMB4_S1_S1 is
                port (
                        CLKA,CLKB: in STD_LOGIC;
                        RSTA,RSTB: in STD_LOGIC;
                        ENA,    ENB: in STD_LOGIC;
                        WEA,    WEB: in STD_LOGIC;
                        ADDRA,ADDRB: in STD_LOGIC_VECTOR (11 downto 0);
                        DIA,DIB: in STD_LOGIC;
                        DOA,DOB: out STD_LOGIC  );
        end component;
        component RAMB4_S2_S2 is
                port (
                        CLKA,   CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
                        ADDRA,ADDRB: in STD_LOGIC_VECTOR (10 downto 0);
                        DIA,DIB: in STD_LOGIC_VECTOR (1 downto 0);
                        DOA,DOB: out STD_LOGIC_VECTOR (1 downto 0)
                        );
        end component;
        component RAMB4_S4_S4 is
                port (
                        CLKA,   CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
                        ADDRA,ADDRB: in STD_LOGIC_VECTOR (9 downto 0);
                        DIA,DIB: in STD_LOGIC_VECTOR (3 downto 0);
                        DOA,DOB: out STD_LOGIC_VECTOR (3 downto 0)
                        );
        end component;
        component RAMB4_S8_S8 is
                port (
                        CLKA,   CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
                        ADDRA,ADDRB: in STD_LOGIC_VECTOR (8 downto 0);
                        DIA,DIB: in STD_LOGIC_VECTOR (7 downto 0);
                        DOA,DOB: out STD_LOGIC_VECTOR (7 downto 0)
                        );
        end component;
        component RAMB4_S16_S16 is
                port (
                        CLKA,CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
                        ADDRA,ADDRB: in STD_LOGIC_VECTOR (7 downto 0);
                        DIA,DIB  : in STD_LOGIC_VECTOR (15 downto 0);
                        DOA,DOB: out STD_LOGIC_VECTOR (15 downto 0)
                        );
        end component;
        component   RAMB16_S18_S18 is
                port (DIA    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIB    : in STD_LOGIC_VECTOR (15 downto 0);
                        DIPA    : in STD_LOGIC_VECTOR (1 downto 0);
                        DIPB    : in STD_LOGIC_VECTOR (1 downto 0);
                        ENA    : in STD_ULOGIC;
                        ENB    : in STD_ULOGIC;
                        WEA    : in STD_ULOGIC;
                        WEB    : in STD_ULOGIC;
                        SSRA   : in STD_ULOGIC;
                        SSRB   : in STD_ULOGIC;
                        CLKA   : in STD_ULOGIC;
                        CLKB   : in STD_ULOGIC;
                        ADDRA  : in STD_LOGIC_VECTOR (9 downto 0);
                        ADDRB  : in STD_LOGIC_VECTOR (9 downto 0);
                        DOA    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOB    : out STD_LOGIC_VECTOR (15 downto 0);
                        DOPA    : out STD_LOGIC_VECTOR (1 downto 0);
                        DOPB    : out STD_LOGIC_VECTOR (1 downto 0)
                        );
        end     component;
 
        --constant zeros: STD_LOGIC_VECTOR (width-iwidth-1 downto 0):=(others=>'0');
        signal EN,A10 : STD_LOGIC;
        signal DIREi,DIIMi:    STD_LOGIC_VECTOR (width-1 downto 0);
        signal ADDRA8,ADDRB8:  STD_LOGIC_VECTOR (7 downto 0);
        signal ADDRA9,ADDRB9:  STD_LOGIC_VECTOR (8 downto 0);
        signal ADDRA10,ADDRB10:  STD_LOGIC_VECTOR (9 downto 0);
        signal ADDRA11,ADDRB11:  STD_LOGIC_VECTOR (10 downto 0);
        signal ADDRA12,ADDRB12:  STD_LOGIC_VECTOR (11 downto 0);
        signal  WE0,WE1,WEB,over:STD_LOGIC;
        Signal DIAR,DIB,DOA,DOBR,DOBR0,DOBR1:  STD_LOGIC_VECTOR (17 downto 0);
        Signal DIAI,DOBI,DOBI0,DOBI1:  STD_LOGIC_VECTOR (17 downto 0);
 
 
begin
        --Writing at ADDRW address
        --      Reading at ADDRR address
 
        EN <= '1';
        DIB<=(others=>'0');
        RDI:process(CLK,RST)
        begin
                if RST='1' then
                        DIREi<=(others=>'0');
                        DIIMi<=(others=>'0');
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                DIREi<=DIRE;
                                DIIMi<=DIIM;
                        end if;
                end if;
        end process;
        --      DIREi<=DIRE;
        --                              DIIMi<=DIIM;
 
 
        --      Virtex:if V2=0 generate
        --              ZEROD:    for i in  width to 15 generate                                                                                                                                        
        --                      DIAR(i)<='0';   
        --                      DIAI(i)<='0';   
        --              end generate;
        --              
        --              DIB<=(others=>'0');                                       
        --              WEB<='0';
        --              
        --              RAMD256:        if       n=4 or n=5 or n=6 or n=7 or n=8 generate               
        --                      EMPTYA4:if n=4 generate
        --                              ADDRA8(7 downto 4) <= "0000";                   
        --                              ADDRB8(7 downto 4) <= "0000";
        --                      end generate;     
        --                      
        --                      EMPTYA5:if n=5 generate
        --                              ADDRA8(7 downto 5) <= "000";                    
        --                              ADDRB8(7 downto 5) <= "000";
        --                      end generate;    
        --                      
        --                      EMPTYA6:if n=6 generate
        --                              ADDRA8(6) <= '0';                       
        --                              ADDRB8(6) <= '0';        
        --                              ADDRA8(7) <= '0';                       
        --                              ADDRB8(7) <= '0';
        --                      end generate;      
        --                      EMPTYA7:if n=7 generate
        --                              ADDRA8(7) <= '0';                       
        --                              ADDRB8(7) <= '0';
        --                      end generate;   
        --                      
        --                      ADDRA8(n-1 downto 0)<=ADDRW(n-1 downto 0);
        --                      ADDRB8(n-1 downto 0)<=ADDRR(n-1 downto 0);
        --                      
        --                      
        --                      RAM256_R:  RAMB4_S16_S16        
        --                      port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                              ENA => EN,ENB => EN,
        --                              WEA =>WE,WEB => WEB,
        --                              DOA => DOA, DOB => DOBR, 
        --                              ADDRA => ADDRA8, ADDRB => ADDRB8,
        --                              DIA => DIAR, DIB => DIB);               
        --                      
        --                      RAM256_I:  RAMB4_S16_S16        
        --                      port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                              ENA => EN,ENB => EN,
        --                              WEA =>WE,WEB => WEB,
        --                              DOA => DOA, DOB => DOBI, 
        --                              ADDRA => ADDRA8, ADDRB => ADDRB8,
        --                              DIA => DIAI, DIB => DIB);                       
        --              end generate;                                                    
        --              
        --              RAMD512:        if        n=9 generate          
        --                      
        --                      ADDRA9(n-1 downto 0)<=ADDRW(n-1 downto 0);
        --                      ADDRB9(n-1 downto 0)<=ADDRR(n-1 downto 0);
        --                      
        --                      RAMD9:for i in 0 to 1 generate
        --                              
        --                              RAM512_R:  RAMB4_S8_S8  
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(8*i+7 downto 8*i), DOB => DOBR(8*i+7 downto 8*i), 
        --                                      ADDRA => ADDRA9, ADDRB => ADDRB9,
        --                                      DIA => DIAR(8*i+7 downto 8*i), DIB => DIB(8*i+7 downto 8*i));           
        --                              
        --                              RAM512_I:  RAMB4_S8_S8  
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(8*i+7 downto 8*i), DOB => DOBI(8*i+7 downto 8*i), 
        --                                      ADDRA => ADDRA9, ADDRB => ADDRB9,
        --                                      DIA => DIAI(8*i+7 downto 8*i), DIB => DIB(8*i+7 downto 8*i));           
        --                              
        --                      end generate;   
        --                      
        --              end generate;           
        --              
        --              RAMD1024:       if        n=10 generate         
        --                      
        --                      ADDRA10(n-1 downto 0)<=ADDRW(n-1 downto 0);
        --                      ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
        --                      
        --                      RAMD10:for i in 0 to 3 generate
        --                              
        --                              RAM1024_R:  RAMB4_S4_S4 
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(4*i+3 downto 4*i), DOB => DOBR(4*i+3 downto 4*i), 
        --                                      ADDRA => ADDRA10, ADDRB => ADDRB10,
        --                                      DIA => DIAR(4*i+3 downto 4*i), DIB => DIB(4*i+3 downto 4*i));           
        --                              
        --                              RAM1024_I:  RAMB4_S4_S4 
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(4*i+3 downto 4*i), DOB => DOBI(4*i+3 downto 4*i), 
        --                                      ADDRA => ADDRA10, ADDRB => ADDRB10,
        --                                      DIA => DIAI(4*i+3 downto 4*i), DIB => DIB(4*i+3 downto 4*i));           
        --                              
        --                      end generate;   
        --              end generate;
        --              
        --              RAMD2048:       if        n=11 generate         
        --                      
        --                      ADDRA11(n-1 downto 0)<=ADDRW(n-1 downto 0);
        --                      ADDRB11(n-1 downto 0)<=ADDRR(n-1 downto 0);
        --                      RAMD11:for i in 0 to 7 generate
        --                              
        --                              RAM2048_R:  RAMB4_S2_S2 
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(2*i+1 downto 2*i), DOB => DOBR(2*i+1 downto 2*i), 
        --                                      ADDRA => ADDRA11, ADDRB => ADDRB11,
        --                                      DIA => DIAR(2*i+1 downto 2*i), DIB => DIB(2*i+1 downto 2*i));   
        --                              
        --                              RAM2048_I:  RAMB4_S2_S2 
        --                              port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
        --                                      ENA => EN,ENB => EN,
        --                                      WEA =>WE,WEB => WEB,
        --                                      DOA => DOA(2*i+1 downto 2*i), DOB => DOBI(2*i+1 downto 2*i), 
        --                                      ADDRA => ADDRA11, ADDRB => ADDRB11,
        --                                      DIA => DIAI(2*i+1 downto 2*i), DIB => DIB(2*i+1 downto 2*i));                           
        --                              
        --                      end generate;
        --              end generate;
        --      end generate;
 
        RAMD512v2:      if        n<=9 and v2=1 generate
                DIB<=(others=>'0');
                WEB<='0';
                ADDRB10(n downto 0)<=ADDRR(n downto 0);
 
                DIAR( width-1 downto 0)<= DMRE;
                DIAI( width-1 downto 0)<=DMIM;
 
                ADDRA10(n downto 0)<=ADDRW(n downto 0);
                ADDRA10(9 downto n+1)<=(others=>'0');
                ADDRB10(n downto 0)<=ADDRR(n downto 0);
                ADDRB10(9 downto n+1)<=(others=>'0');
 
 
                -- Working RAMs         
                RAM1024_R:   RAMB16_S18_S18      --Re -part
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RESRAM,
                        WEA  => WE, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAR(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAR(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10,
                        ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBR(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBR(15 downto 0));
 
                RAM1024_I:   RAMB16_S18_S18
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB =>  RESRAM,
                        WEA  => WE, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAI(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAI(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBI(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBI(15 downto 0));
        end generate;
 
        RAMD1024v2:     if        n=10 and v2=1 generate
                DIB<=(others=>'0');
                WEB<='0';
 
                ADDRB10<=ADDRR(n-1 downto 0);
                ADDRA10<=ADDRW(n-1 downto 0);
 
                DIAR( width-1 downto 0)<= DMRE;
                DIAI( width-1 downto 0)<=DMIM;
 
                WE0<=WE when ADDRW(n)='0' else '0';
                WE1<=WE when ADDRW(n)='1' else '0';
 
 
                -- Working RAMs         
                RAM1024_R0:   RAMB16_S18_S18     --Re -part
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB =>  RESRAM,
                        WEA  => WE0, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAR(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAR(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10,
                        ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBR0(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBR0(15 downto 0));
 
                RAM1024_I0:   RAMB16_S18_S18
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB =>  RESRAM,
                        WEA  => WE0, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAI(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAI(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBI0(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBI0(15 downto 0));
 
                RAM1024_R1:   RAMB16_S18_S18     --Re -part
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RESRAM,
                        WEA  => WE1, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAR(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAR(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10,
                        ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBR1(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBR1(15 downto 0));
 
                RAM1024_I1:   RAMB16_S18_S18
                port map (
                        CLKA => CLK,  CLKB => CLK,SSRA => RST,SSRB => RESRAM,
                        WEA  => WE1, WEB  => WEB,ENA  => EN,ENB  => EN,
                        DIPA => DIAI(17 downto 16),
                        DIPB => DIB(17 downto 16),
                        DIA  => DIAI(15 downto 0),
                        DIB  => DIB(15 downto 0),
                        ADDRA => ADDRA10, ADDRB => ADDRB10,
                        DOPA => open,--DOA2(17 downto 16),
                        DOPB => DOBI1(17 downto 16),
                        DOA  => open,--DOA2(15 downto 0),
                        DOB  => DOBI1(15 downto 0));
 
                TA:process(CLK,RST)begin
                        if RST='1' then
                                A10<='0';
                        elsif rising_edge(CLK) then
                                A10<=ADDRR(n);
                        end if;
                end process;
 
                DOBR<=DOBR0 when A10='0' else DOBR1;
                DOBI<=DOBI0 when A10='0' else DOBI1;
 
        end generate;
 
 
        TOVERFR:process(CLK,RST,DIAR,DIAI)
        begin
                over<=  (DIAI( width-1) xor  DIAI( width-2)) or (DIAI( width-1) xor  DIAI( width-3))
                or (DIAR( width-1) xor  DIAR( width-2)) or (DIAR( width-1) xor  DIAR( width-3));
 
                if RST='1' then
                        OVERF<='0';
                elsif CLK='1' and CLK'event then
                        if CE='1' then
                                if  INITOVERF='1' then
                                        OVERF<='0';
                                elsif over='1' and WE='1' then
                                        OVERF<='1';
                                end if;
                        end if;
                end if;
        end process;
 
 
 
        DORE<=DOBR(width-1 downto 0)when SEL='0' else DIREi;
        DOIM<=DOBI(width-1 downto 0)when SEL='0' else DIIMi;
 
 
 
end RAM1X;

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[/] [fft_fir_filter/] [trunk/] [rtl/] [ram1x_2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FFT Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39
40			`library IEEE;`
41			`use IEEE.std_logic_1164.all;`
42			`use IEEE.std_logic_arith.all;`
43			`use IEEE.std_logic_unsigned.all;`
44
45			`entity RAM1X_2 is`
46			`generic(width : INTEGER;`
47			`n:INTEGER; -- 6,7,8,9,10,11`
48			`v2:INTEGER:=1);`
49			`port (`
50			`CLK: in STD_LOGIC;`
51			`RST: in STD_LOGIC;`
52			`CE: in STD_LOGIC;`
53			`WE: in STD_LOGIC;`
54			`INITOVERF: in STD_LOGIC;`
55			`ADDRW: in STD_LOGIC_VECTOR (n downto 0);`
56			`ADDRR: in STD_LOGIC_VECTOR (n downto 0);`
57			`SEL: in STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM`
58			`RESRAM: in STD_LOGIC;`
59			`DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
60			`DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
61			`DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);`
62			`DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);`
63			`OVERF:out STD_LOGIC;`
64			`DORE: out STD_LOGIC_VECTOR (width-1 downto 0);`
65			`DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)`
66			`);`
67			`end RAM1X_2;`
68
69
70			`architecture RAM1X of RAM1X_2 is`
71
72			`component RAMB4_S1_S1 is`
73			`port (`
74			`CLKA,CLKB: in STD_LOGIC;`
75			`RSTA,RSTB: in STD_LOGIC;`
76			`ENA, ENB: in STD_LOGIC;`
77			`WEA, WEB: in STD_LOGIC;`
78			`ADDRA,ADDRB: in STD_LOGIC_VECTOR (11 downto 0);`
79			`DIA,DIB: in STD_LOGIC;`
80			`DOA,DOB: out STD_LOGIC );`
81			`end component;`
82			`component RAMB4_S2_S2 is`
83			`port (`
84			`CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;`
85			`ADDRA,ADDRB: in STD_LOGIC_VECTOR (10 downto 0);`
86			`DIA,DIB: in STD_LOGIC_VECTOR (1 downto 0);`
87			`DOA,DOB: out STD_LOGIC_VECTOR (1 downto 0)`
88			`);`
89			`end component;`
90			`component RAMB4_S4_S4 is`
91			`port (`
92			`CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;`
93			`ADDRA,ADDRB: in STD_LOGIC_VECTOR (9 downto 0);`
94			`DIA,DIB: in STD_LOGIC_VECTOR (3 downto 0);`
95			`DOA,DOB: out STD_LOGIC_VECTOR (3 downto 0)`
96			`);`
97			`end component;`
98			`component RAMB4_S8_S8 is`
99			`port (`
100			`CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;`
101			`ADDRA,ADDRB: in STD_LOGIC_VECTOR (8 downto 0);`
102			`DIA,DIB: in STD_LOGIC_VECTOR (7 downto 0);`
103			`DOA,DOB: out STD_LOGIC_VECTOR (7 downto 0)`
104			`);`
105			`end component;`
106			`component RAMB4_S16_S16 is`
107			`port (`
108			`CLKA,CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;`
109			`ADDRA,ADDRB: in STD_LOGIC_VECTOR (7 downto 0);`
110			`DIA,DIB : in STD_LOGIC_VECTOR (15 downto 0);`
111			`DOA,DOB: out STD_LOGIC_VECTOR (15 downto 0)`
112			`);`
113			`end component;`
114			`component RAMB16_S18_S18 is`
115			`port (DIA : in STD_LOGIC_VECTOR (15 downto 0);`
116			`DIB : in STD_LOGIC_VECTOR (15 downto 0);`
117			`DIPA : in STD_LOGIC_VECTOR (1 downto 0);`
118			`DIPB : in STD_LOGIC_VECTOR (1 downto 0);`
119			`ENA : in STD_ULOGIC;`
120			`ENB : in STD_ULOGIC;`
121			`WEA : in STD_ULOGIC;`
122			`WEB : in STD_ULOGIC;`
123			`SSRA : in STD_ULOGIC;`
124			`SSRB : in STD_ULOGIC;`
125			`CLKA : in STD_ULOGIC;`
126			`CLKB : in STD_ULOGIC;`
127			`ADDRA : in STD_LOGIC_VECTOR (9 downto 0);`
128			`ADDRB : in STD_LOGIC_VECTOR (9 downto 0);`
129			`DOA : out STD_LOGIC_VECTOR (15 downto 0);`
130			`DOB : out STD_LOGIC_VECTOR (15 downto 0);`
131			`DOPA : out STD_LOGIC_VECTOR (1 downto 0);`
132			`DOPB : out STD_LOGIC_VECTOR (1 downto 0)`
133			`);`
134			`end component;`
135
136			`--constant zeros: STD_LOGIC_VECTOR (width-iwidth-1 downto 0):=(others=>'0');`
137			`signal EN,A10 : STD_LOGIC;`
138			`signal DIREi,DIIMi: STD_LOGIC_VECTOR (width-1 downto 0);`
139			`signal ADDRA8,ADDRB8: STD_LOGIC_VECTOR (7 downto 0);`
140			`signal ADDRA9,ADDRB9: STD_LOGIC_VECTOR (8 downto 0);`
141			`signal ADDRA10,ADDRB10: STD_LOGIC_VECTOR (9 downto 0);`
142			`signal ADDRA11,ADDRB11: STD_LOGIC_VECTOR (10 downto 0);`
143			`signal ADDRA12,ADDRB12: STD_LOGIC_VECTOR (11 downto 0);`
144			`signal WE0,WE1,WEB,over:STD_LOGIC;`
145			`Signal DIAR,DIB,DOA,DOBR,DOBR0,DOBR1: STD_LOGIC_VECTOR (17 downto 0);`
146			`Signal DIAI,DOBI,DOBI0,DOBI1: STD_LOGIC_VECTOR (17 downto 0);`
147
148
149			`begin`
150			`--Writing at ADDRW address`
151			`-- Reading at ADDRR address`
152
153			`EN <= '1';`
154			`DIB<=(others=>'0');`
155			`RDI:process(CLK,RST)`
156			`begin`
157			`if RST='1' then`
158			`DIREi<=(others=>'0');`
159			`DIIMi<=(others=>'0');`
160			`elsif CLK='1' and CLK'event then`
161			`if CE='1' then`
162			`DIREi<=DIRE;`
163			`DIIMi<=DIIM;`
164			`end if;`
165			`end if;`
166			`end process;`
167			`-- DIREi<=DIRE;`
168			`-- DIIMi<=DIIM;`
169
170
171			`-- Virtex:if V2=0 generate`
172			`-- ZEROD: for i in width to 15 generate`
173			`-- DIAR(i)<='0';`
174			`-- DIAI(i)<='0';`
175			`-- end generate;`
176			`--`
177			`-- DIB<=(others=>'0');`
178			`-- WEB<='0';`
179			`--`
180			`-- RAMD256: if n=4 or n=5 or n=6 or n=7 or n=8 generate`
181			`-- EMPTYA4:if n=4 generate`
182			`-- ADDRA8(7 downto 4) <= "0000";`
183			`-- ADDRB8(7 downto 4) <= "0000";`
184			`-- end generate;`
185			`--`
186			`-- EMPTYA5:if n=5 generate`
187			`-- ADDRA8(7 downto 5) <= "000";`
188			`-- ADDRB8(7 downto 5) <= "000";`
189			`-- end generate;`
190			`--`
191			`-- EMPTYA6:if n=6 generate`
192			`-- ADDRA8(6) <= '0';`
193			`-- ADDRB8(6) <= '0';`
194			`-- ADDRA8(7) <= '0';`
195			`-- ADDRB8(7) <= '0';`
196			`-- end generate;`
197			`-- EMPTYA7:if n=7 generate`
198			`-- ADDRA8(7) <= '0';`
199			`-- ADDRB8(7) <= '0';`
200			`-- end generate;`
201			`--`
202			`-- ADDRA8(n-1 downto 0)<=ADDRW(n-1 downto 0);`
203			`-- ADDRB8(n-1 downto 0)<=ADDRR(n-1 downto 0);`
204			`--`
205			`--`
206			`-- RAM256_R: RAMB4_S16_S16`
207			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
208			`-- ENA => EN,ENB => EN,`
209			`-- WEA =>WE,WEB => WEB,`
210			`-- DOA => DOA, DOB => DOBR,`
211			`-- ADDRA => ADDRA8, ADDRB => ADDRB8,`
212			`-- DIA => DIAR, DIB => DIB);`
213			`--`
214			`-- RAM256_I: RAMB4_S16_S16`
215			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
216			`-- ENA => EN,ENB => EN,`
217			`-- WEA =>WE,WEB => WEB,`
218			`-- DOA => DOA, DOB => DOBI,`
219			`-- ADDRA => ADDRA8, ADDRB => ADDRB8,`
220			`-- DIA => DIAI, DIB => DIB);`
221			`-- end generate;`
222			`--`
223			`-- RAMD512: if n=9 generate`
224			`--`
225			`-- ADDRA9(n-1 downto 0)<=ADDRW(n-1 downto 0);`
226			`-- ADDRB9(n-1 downto 0)<=ADDRR(n-1 downto 0);`
227			`--`
228			`-- RAMD9:for i in 0 to 1 generate`
229			`--`
230			`-- RAM512_R: RAMB4_S8_S8`
231			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
232			`-- ENA => EN,ENB => EN,`
233			`-- WEA =>WE,WEB => WEB,`
234			`-- DOA => DOA(8i+7 downto 8i), DOB => DOBR(8i+7 downto 8i),`
235			`-- ADDRA => ADDRA9, ADDRB => ADDRB9,`
236			`-- DIA => DIAR(8i+7 downto 8i), DIB => DIB(8i+7 downto 8i));`
237			`--`
238			`-- RAM512_I: RAMB4_S8_S8`
239			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
240			`-- ENA => EN,ENB => EN,`
241			`-- WEA =>WE,WEB => WEB,`
242			`-- DOA => DOA(8i+7 downto 8i), DOB => DOBI(8i+7 downto 8i),`
243			`-- ADDRA => ADDRA9, ADDRB => ADDRB9,`
244			`-- DIA => DIAI(8i+7 downto 8i), DIB => DIB(8i+7 downto 8i));`
245			`--`
246			`-- end generate;`
247			`--`
248			`-- end generate;`
249			`--`
250			`-- RAMD1024: if n=10 generate`
251			`--`
252			`-- ADDRA10(n-1 downto 0)<=ADDRW(n-1 downto 0);`
253			`-- ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);`
254			`--`
255			`-- RAMD10:for i in 0 to 3 generate`
256			`--`
257			`-- RAM1024_R: RAMB4_S4_S4`
258			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
259			`-- ENA => EN,ENB => EN,`
260			`-- WEA =>WE,WEB => WEB,`
261			`-- DOA => DOA(4i+3 downto 4i), DOB => DOBR(4i+3 downto 4i),`
262			`-- ADDRA => ADDRA10, ADDRB => ADDRB10,`
263			`-- DIA => DIAR(4i+3 downto 4i), DIB => DIB(4i+3 downto 4i));`
264			`--`
265			`-- RAM1024_I: RAMB4_S4_S4`
266			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
267			`-- ENA => EN,ENB => EN,`
268			`-- WEA =>WE,WEB => WEB,`
269			`-- DOA => DOA(4i+3 downto 4i), DOB => DOBI(4i+3 downto 4i),`
270			`-- ADDRA => ADDRA10, ADDRB => ADDRB10,`
271			`-- DIA => DIAI(4i+3 downto 4i), DIB => DIB(4i+3 downto 4i));`
272			`--`
273			`-- end generate;`
274			`-- end generate;`
275			`--`
276			`-- RAMD2048: if n=11 generate`
277			`--`
278			`-- ADDRA11(n-1 downto 0)<=ADDRW(n-1 downto 0);`
279			`-- ADDRB11(n-1 downto 0)<=ADDRR(n-1 downto 0);`
280			`-- RAMD11:for i in 0 to 7 generate`
281			`--`
282			`-- RAM2048_R: RAMB4_S2_S2`
283			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
284			`-- ENA => EN,ENB => EN,`
285			`-- WEA =>WE,WEB => WEB,`
286			`-- DOA => DOA(2i+1 downto 2i), DOB => DOBR(2i+1 downto 2i),`
287			`-- ADDRA => ADDRA11, ADDRB => ADDRB11,`
288			`-- DIA => DIAR(2i+1 downto 2i), DIB => DIB(2i+1 downto 2i));`
289			`--`
290			`-- RAM2048_I: RAMB4_S2_S2`
291			`-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,`
292			`-- ENA => EN,ENB => EN,`
293			`-- WEA =>WE,WEB => WEB,`
294			`-- DOA => DOA(2i+1 downto 2i), DOB => DOBI(2i+1 downto 2i),`
295			`-- ADDRA => ADDRA11, ADDRB => ADDRB11,`
296			`-- DIA => DIAI(2i+1 downto 2i), DIB => DIB(2i+1 downto 2i));`
297			`--`
298			`-- end generate;`
299			`-- end generate;`
300			`-- end generate;`
301
302			`RAMD512v2: if n<=9 and v2=1 generate`
303			`DIB<=(others=>'0');`
304			`WEB<='0';`
305			`ADDRB10(n downto 0)<=ADDRR(n downto 0);`
306
307			`DIAR( width-1 downto 0)<= DMRE;`
308			`DIAI( width-1 downto 0)<=DMIM;`
309
310			`ADDRA10(n downto 0)<=ADDRW(n downto 0);`
311			`ADDRA10(9 downto n+1)<=(others=>'0');`
312			`ADDRB10(n downto 0)<=ADDRR(n downto 0);`
313			`ADDRB10(9 downto n+1)<=(others=>'0');`
314
315
316			`-- Working RAMs`
317			`RAM1024_R: RAMB16_S18_S18 --Re -part`
318			`port map (`
319			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
320			`WEA => WE, WEB => WEB,ENA => EN,ENB => EN,`
321			`DIPA => DIAR(17 downto 16),`
322			`DIPB => DIB(17 downto 16),`
323			`DIA => DIAR(15 downto 0),`
324			`DIB => DIB(15 downto 0),`
325			`ADDRA => ADDRA10,`
326			`ADDRB => ADDRB10,`
327			`DOPA => open,--DOA2(17 downto 16),`
328			`DOPB => DOBR(17 downto 16),`
329			`DOA => open,--DOA2(15 downto 0),`
330			`DOB => DOBR(15 downto 0));`
331
332			`RAM1024_I: RAMB16_S18_S18`
333			`port map (`
334			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
335			`WEA => WE, WEB => WEB,ENA => EN,ENB => EN,`
336			`DIPA => DIAI(17 downto 16),`
337			`DIPB => DIB(17 downto 16),`
338			`DIA => DIAI(15 downto 0),`
339			`DIB => DIB(15 downto 0),`
340			`ADDRA => ADDRA10, ADDRB => ADDRB10,`
341			`DOPA => open,--DOA2(17 downto 16),`
342			`DOPB => DOBI(17 downto 16),`
343			`DOA => open,--DOA2(15 downto 0),`
344			`DOB => DOBI(15 downto 0));`
345			`end generate;`
346
347			`RAMD1024v2: if n=10 and v2=1 generate`
348			`DIB<=(others=>'0');`
349			`WEB<='0';`
350
351			`ADDRB10<=ADDRR(n-1 downto 0);`
352			`ADDRA10<=ADDRW(n-1 downto 0);`
353
354			`DIAR( width-1 downto 0)<= DMRE;`
355			`DIAI( width-1 downto 0)<=DMIM;`
356
357			`WE0<=WE when ADDRW(n)='0' else '0';`
358			`WE1<=WE when ADDRW(n)='1' else '0';`
359
360
361			`-- Working RAMs`
362			`RAM1024_R0: RAMB16_S18_S18 --Re -part`
363			`port map (`
364			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
365			`WEA => WE0, WEB => WEB,ENA => EN,ENB => EN,`
366			`DIPA => DIAR(17 downto 16),`
367			`DIPB => DIB(17 downto 16),`
368			`DIA => DIAR(15 downto 0),`
369			`DIB => DIB(15 downto 0),`
370			`ADDRA => ADDRA10,`
371			`ADDRB => ADDRB10,`
372			`DOPA => open,--DOA2(17 downto 16),`
373			`DOPB => DOBR0(17 downto 16),`
374			`DOA => open,--DOA2(15 downto 0),`
375			`DOB => DOBR0(15 downto 0));`
376
377			`RAM1024_I0: RAMB16_S18_S18`
378			`port map (`
379			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
380			`WEA => WE0, WEB => WEB,ENA => EN,ENB => EN,`
381			`DIPA => DIAI(17 downto 16),`
382			`DIPB => DIB(17 downto 16),`
383			`DIA => DIAI(15 downto 0),`
384			`DIB => DIB(15 downto 0),`
385			`ADDRA => ADDRA10, ADDRB => ADDRB10,`
386			`DOPA => open,--DOA2(17 downto 16),`
387			`DOPB => DOBI0(17 downto 16),`
388			`DOA => open,--DOA2(15 downto 0),`
389			`DOB => DOBI0(15 downto 0));`
390
391			`RAM1024_R1: RAMB16_S18_S18 --Re -part`
392			`port map (`
393			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
394			`WEA => WE1, WEB => WEB,ENA => EN,ENB => EN,`
395			`DIPA => DIAR(17 downto 16),`
396			`DIPB => DIB(17 downto 16),`
397			`DIA => DIAR(15 downto 0),`
398			`DIB => DIB(15 downto 0),`
399			`ADDRA => ADDRA10,`
400			`ADDRB => ADDRB10,`
401			`DOPA => open,--DOA2(17 downto 16),`
402			`DOPB => DOBR1(17 downto 16),`
403			`DOA => open,--DOA2(15 downto 0),`
404			`DOB => DOBR1(15 downto 0));`
405
406			`RAM1024_I1: RAMB16_S18_S18`
407			`port map (`
408			`CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,`
409			`WEA => WE1, WEB => WEB,ENA => EN,ENB => EN,`
410			`DIPA => DIAI(17 downto 16),`
411			`DIPB => DIB(17 downto 16),`
412			`DIA => DIAI(15 downto 0),`
413			`DIB => DIB(15 downto 0),`
414			`ADDRA => ADDRA10, ADDRB => ADDRB10,`
415			`DOPA => open,--DOA2(17 downto 16),`
416			`DOPB => DOBI1(17 downto 16),`
417			`DOA => open,--DOA2(15 downto 0),`
418			`DOB => DOBI1(15 downto 0));`
419
420			`TA:process(CLK,RST)begin`
421			`if RST='1' then`
422			`A10<='0';`
423			`elsif rising_edge(CLK) then`
424			`A10<=ADDRR(n);`
425			`end if;`
426			`end process;`
427
428			`DOBR<=DOBR0 when A10='0' else DOBR1;`
429			`DOBI<=DOBI0 when A10='0' else DOBI1;`
430
431			`end generate;`
432
433
434			`TOVERFR:process(CLK,RST,DIAR,DIAI)`
435			`begin`
436			`over<= (DIAI( width-1) xor DIAI( width-2)) or (DIAI( width-1) xor DIAI( width-3))`
437			`or (DIAR( width-1) xor DIAR( width-2)) or (DIAR( width-1) xor DIAR( width-3));`
438
439			`if RST='1' then`
440			`OVERF<='0';`
441			`elsif CLK='1' and CLK'event then`
442			`if CE='1' then`
443			`if INITOVERF='1' then`
444			`OVERF<='0';`
445			`elsif over='1' and WE='1' then`
446			`OVERF<='1';`
447			`end if;`
448			`end if;`
449			`end if;`
450			`end process;`
451
452
453
454			`DORE<=DOBR(width-1 downto 0)when SEL='0' else DIREi;`
455			`DOIM<=DOBI(width-1 downto 0)when SEL='0' else DIIMi;`
456
457
458
459			`end RAM1X;`