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-------------------------------------------------------------------------------
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-- Title      : Parametrilayze based on SRL16 shift register FIFO
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : fifo_srl_uni.vhd
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-- Author     : Tomasz Turek  <tomasz.turek@gmail.com>
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-- Company    : SzuWar INC
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-- Created    : 13:27:31 14-03-2010
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-- Last update: 12:03:49 18-03-2010
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-- Platform   : Xilinx ISE 10.1.03
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-- Standard   : VHDL'93
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-------------------------------------------------------------------------------
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-- Description: 
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 SzuWar INC
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date                  Version  Author  Description
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-- 13:27:31 14-03-2010   1.0      szuwarek  Created
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-------------------------------------------------------------------------------
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22
 
23
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_arith.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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--use ieee.numeric_std.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity fifo_srl_uni is
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   generic (
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      iDataWidth        : integer range 1 to 32   := 17;
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      ififoWidth        : integer range 1 to 1023 := 32;
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      iInputReg         : integer range 0 to 2    := 0;
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      iOutputReg        : integer range 0 to 3    := 2;
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      iFullFlagOfSet    : integer range 0 to 1021 := 2;
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      iEmptyFlagOfSet   : integer range 0 to 1021 := 5;
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      iSizeDelayCounter : integer range 5 to 11   := 6
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      );
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   port (
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      CLK_I          : in  std_logic;
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      DATA_I         : in  std_logic_vector(iDataWidth - 1 downto 0);
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      DATA_O         : out std_logic_vector(iDataWidth - 1 downto 0);
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      WRITE_ENABLE_I : in  std_logic;
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      READ_ENABLE_I  : in  std_logic;
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      READ_VALID_O   : out std_logic;
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      FIFO_COUNT_O   : out std_logic_vector(iSizeDelayCounter - 1 downto 0);
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      FULL_FLAG_O    : out std_logic;
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      EMPTY_FLAG_O   : out std_logic
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      );
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end entity fifo_srl_uni;
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architecture fifo_srl_uni_rtl of fifo_srl_uni is
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-------------------------------------------------------------------------------
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-- functions --
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-------------------------------------------------------------------------------
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   function f_srl_count (constant c_fifo_size : integer) return integer is
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      variable i_temp  : integer;
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      variable i_count : integer;
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   begin  -- function f_srl_count
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      i_temp := c_fifo_size;
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      i_count := 0;
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      for i in 0 to 64 loop
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         if i_temp < 1 then
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            if i_count = 0 then
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               i_count := i;
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            else
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               i_count := i_count;
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            end if;
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         else
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            i_temp := i_temp - 16;
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         end if;
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      end loop;  -- i
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      return i_count;
97
 
98
   end function f_srl_count;
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100
-------------------------------------------------------------------------------
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-- constants --
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-------------------------------------------------------------------------------
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   constant c_srl_count : integer range 0 to 64 := f_srl_count(ififoWidth);
104
 
105
-------------------------------------------------------------------------------
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-- types --
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-------------------------------------------------------------------------------
108
   type type_in_reg    is array (0 to iInputReg - 1)   of std_logic_vector(iDataWidth - 1 downto 0);
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   type type_out_reg   is array (0 to iOutputReg)      of std_logic_vector(iDataWidth - 1 downto 0);
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   type type_data_path is array (0 to c_srl_count - 1) of std_logic_vector(iDataWidth - 1 downto 0);
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   type type_srl_path  is array (0 to c_srl_count)    of std_logic_vector(iDataWidth - 1 downto 0);
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113
-------------------------------------------------------------------------------
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-- signals --
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-------------------------------------------------------------------------------
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   signal v_delay_counter : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
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   signal v_size_counter  : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
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   signal v_zeros         : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
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   signal v_ones          : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
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   signal v_WRITE_ENABLE  : std_logic_vector(iInputReg downto 0);
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   signal v_READ_ENABLE   : std_logic_vector(iOutputReg downto 0);
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   signal i_size_counter  : integer range 0 to 1023 := 0;
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   signal i_srl_select    : integer range 0 to 64 := 0;
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   signal i_temp          : integer range 0 to 64;
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   signal t_mux_in        : type_data_path;
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   signal t_srl_in        : type_srl_path;
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   signal t_mux_out       : type_out_reg;
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   signal t_reg_in        : type_in_reg;
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   signal one_delay       : std_logic := '0';
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   signal dupa       : std_logic := '0';
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begin  -- architecture fifo_srl_uni_r
133
 
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   v_zeros <= (others => '0');
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   v_ones  <= (others => '1');
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138
   GR0: if iInputReg = 0 generate
139
 
140
      t_srl_in(0) <= DATA_I;
141
      v_WRITE_ENABLE(0) <= WRITE_ENABLE_I;
142
 
143
   end generate GR0;
144
 
145
   GR1: if iInputReg = 1 generate
146
 
147
      t_srl_in(0) <= t_reg_in(0);
148
      v_WRITE_ENABLE(1) <= WRITE_ENABLE_I;
149
 
150
      P1: process (CLK_I) is
151
      begin  -- process P1
152
 
153
         if rising_edge(CLK_I) then
154
 
155
            t_reg_in(0) <= DATA_I;
156
            v_WRITE_ENABLE(0) <= v_WRITE_ENABLE(1);
157
 
158
         end if;
159
 
160
      end process P1;
161
 
162
   end generate GR1;
163
 
164
   GR2: if iInputReg = 2 generate
165
 
166
      t_srl_in(0) <= t_reg_in(0);
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      v_WRITE_ENABLE(2) <= WRITE_ENABLE_I;
168
 
169
      P1: process (CLK_I) is
170
      begin  -- process P1
171
 
172
         if rising_edge(CLK_I) then
173
 
174
            t_reg_in(1) <= DATA_I;
175
            t_reg_in(0) <= t_reg_in(1);
176
            v_WRITE_ENABLE(1 downto 0) <= v_WRITE_ENABLE(2 downto 1);
177
 
178
         end if;
179
 
180
      end process P1;
181
 
182
   end generate GR2;
183
 
184
   G1: for i in 0 to c_srl_count - 1 generate
185
 
186
      G0: for j in 0 to iDataWidth - 1 generate
187
 
188
         SRLC16_inst : SRLC16E
189
            port map
190
            (
191
                  Q => t_mux_in(i)(j), -- SRL data output
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                  Q15 => t_srl_in(i+1)(j), -- Carry output (connect to next SRL)
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                  A0 => v_delay_counter(0), -- Select[0] input
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                  A1 => v_delay_counter(1), -- Select[1] input
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                  A2 => v_delay_counter(2), -- Select[2] input
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                  A3 => v_delay_counter(3), -- Select[3] input
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                  CE => v_WRITE_ENABLE(0), -- Clock enable input
198
                  CLK => CLK_I, -- Clock input
199
                  D => t_srl_in(i)(j) -- SRL data input
200
                  );
201
 
202
      end generate G0;
203
 
204
   end generate G1;
205
 
206
   i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
207
   i_size_counter <= conv_integer(v_size_counter);
208
 
209
   P0: process (CLK_I) is
210
   begin  -- process P0
211
 
212
      if rising_edge(CLK_I) then
213
 
214
         if (v_WRITE_ENABLE(0) = '1') and (READ_ENABLE_I = '0') and (v_size_counter /= v_ones) then
215
 
216
            if one_delay = '1' then
217
 
218
               v_delay_counter <= v_delay_counter + 1;
219
               one_delay <= '1';
220
 
221
            else
222
 
223
               one_delay <= '1';
224
               v_delay_counter <= v_delay_counter;
225
 
226
            end if;
227
 
228
            v_size_counter <= v_size_counter + 1;
229
 
230
         elsif (v_WRITE_ENABLE(0) = '0') and (READ_ENABLE_I = '1') and (v_size_counter /= v_zeros) then
231
 
232
            if v_delay_counter = v_zeros then
233
 
234
               one_delay <= '0';
235
 
236
            else
237
 
238
               one_delay <= '1';
239
               v_delay_counter <= v_delay_counter - 1;
240
 
241
            end if;
242
 
243
           v_size_counter <= v_size_counter - 1;
244
 
245
         else
246
 
247
            v_delay_counter <= v_delay_counter;
248
            v_size_counter <= v_size_counter;
249
            one_delay <= one_delay;
250
 
251
         end if;
252
 
253
      end if;
254
 
255
   end process P0;
256
 
257
   t_mux_out(0) <= t_mux_in(i_srl_select);
258
   READ_VALID_O <= v_READ_ENABLE(0);
259
   FIFO_COUNT_O <= v_size_counter;
260
 
261
   GM0: if iOutputReg = 0 generate
262
 
263
      DATA_O <= t_mux_out(0);
264
      v_READ_ENABLE(0) <= READ_ENABLE_I;
265
 
266
   end generate GM0;
267
 
268
 
269
   GM1: if iOutputReg = 1 generate
270
 
271
      DATA_O <= t_mux_out(1);
272
      v_READ_ENABLE(1) <= READ_ENABLE_I;
273
 
274
      P2: process (CLK_I) is
275
      begin  -- process P2
276
 
277
         if rising_edge(CLK_I) then
278
 
279
            v_READ_ENABLE(0) <= v_READ_ENABLE(1);
280
            t_mux_out(1) <= t_mux_out(0);
281
 
282
         end if;
283
 
284
      end process P2;
285
 
286
   end generate GM1;
287
 
288
   GM2: if iOutputReg > 1 generate
289
 
290
      DATA_O <= t_mux_out(iOutputReg);
291
      v_READ_ENABLE(iOutputReg) <= READ_ENABLE_I;
292
 
293
      P2: process (CLK_I) is
294
      begin  -- process P2
295
 
296
         if rising_edge(CLK_I) then
297
 
298
            v_READ_ENABLE(iOutputReg - 1 downto 0) <= v_READ_ENABLE(iOutputReg downto 1);
299
            t_mux_out(1 to iOutputReg) <= t_mux_out(0 to iOutputReg - 1);
300
 
301
         end if;
302
 
303
      end process P2;
304
 
305
   end generate GM2;
306
 
307
   PF: process (CLK_I) is
308
   begin  -- process PF
309
 
310
      if rising_edge(CLK_I) then
311
 
312
         if i_size_counter >= ififoWidth - iFullFlagOfSet then
313
 
314
            FULL_FLAG_O <= '1';
315
 
316
         else
317
 
318
            FULL_FLAG_O <= '0';
319
 
320
         end if;
321
 
322
         if i_size_counter < iEmptyFlagOfSet then
323
 
324
            EMPTY_FLAG_O <= '1';
325
 
326
         else
327
 
328
            EMPTY_FLAG_O <= '0';
329
 
330
         end if;
331
 
332
      end if;
333
 
334
   end process PF;
335
 
336
 
337
 
338
end architecture fifo_srl_uni_rtl;
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