OpenCores
URL https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk

Subversion Repositories fir_wishbone

[/] [fir_wishbone/] [trunk/] [hw/] [packages/] [pkg-tlm.vhdl] - Blame information for rev 17

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 daniel.kho
/*
2
        This file is part of the AXI4 Transactor and Bus Functional Model
3
        (axi4_tlm_bfm) project:
4
                http://www.opencores.org/project,axi4_tlm_bfm
5
 
6
        Description
7
        This implements a generic interface for transactors, and has a set
8
        of reusable procedures to read and write from / to a bus. This
9
        interface can be used in many different bus protocols, by means of
10
        instantiating this package. An example implementation for the AXI4
11
        protocol can be found at
12
                pkg-axi-tlm.vhdl
13
        under the axi4_tlm_bfm project.
14
 
15
        To Do:
16
 
17
        Author(s):
18
        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
19
 
20
        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
21
 
22
        This source file may be used and distributed without
23
        restriction provided that this copyright statement is not
24
        removed from the file and that any derivative work contains
25
        the original copyright notice and the associated disclaimer.
26
 
27
        This source file is free software; you can redistribute it
28
        and/or modify it under the terms of the GNU Lesser General
29
        Public License as published by the Free Software Foundation;
30
        either version 2.1 of the License, or (at your option) any
31
        later version.
32
 
33
        This source is distributed in the hope that it will be
34
        useful, but WITHOUT ANY WARRANTY; without even the implied
35
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
36
        PURPOSE. See the GNU Lesser General Public License for more
37
        details.
38
 
39
        You should have received a copy of the GNU Lesser General
40
        Public License along with this source; if not, download it
41
        from http://www.opencores.org/lgpl.shtml.
42
*/
43
/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
44
library ieee;   use ieee.std_logic_1164.all, ieee.numeric_std.all;
45
--use std.textio.all;
46
 
47
package tlm is
48
        generic(type t_addr; type t_data; type t_cnt);
49
 
50
--      /* TODO remove once generic packages are supported. */
51
--      subtype t_addr  is u_unsigned(31 downto 0);
52
--      subtype t_data  is std_ulogic_vector(31 downto 0);
53
--      subtype t_cnt   is u_unsigned(127 downto 0);
54
 
55
        /* BFM control interface.
56
                address is only used for non-stream interfaces.
57
        */
58
        type t_bfm is record
59
                address:                        t_addr;
60
                data:                           t_data;
61
                trigger:                        std_ulogic;
62
        end record t_bfm;
63
 
64
        procedure write(
65
                signal request: out     t_bfm;
66
                address:                in      t_addr;
67
                data:                   in      t_data
68
        );
69
 
70
        procedure read(
71
                signal request: out     t_bfm;
72
                address:                in      t_addr
73
        );
74
end package tlm;
75
 
76
package body tlm is
77
        procedure write(
78
                signal request: out     t_bfm;
79
                address:                in      t_addr;                         -- used only for non-stream interfaces.
80
                data:                   in      t_data
81
        ) is begin
82
                request.address <= address;
83
                request.data    <= data;
84
                request.trigger <= not request.trigger;
85
        end procedure write;
86
 
87
        procedure read(
88
                signal request: out     t_bfm;
89
                address:                in      t_addr                          -- used only for non-stream interfaces.
90
        ) is begin
91
                request.address <= address;
92
                request.trigger <= not request.trigger;
93
                --report "request.address: " & to_hstring(request.address);
94
        end procedure read;
95
end package body tlm;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.