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Subversion Repositories fir_wishbone

[/] [fir_wishbone/] [trunk/] [workspaces/] [synthesis/] [quartus/] [stp.qsys] - Blame information for rev 16

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   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="" />
 
{
   element signaltap_ii_logic_analyzer_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
}
]]>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   name="acq_clk"
   internal="signaltap_ii_logic_analyzer_0.acq_clk"
   type="clock"
   dir="end">
  
 
 
   name="tap"
   internal="signaltap_ii_logic_analyzer_0.tap"
   type="conduit"
   dir="end">
  
  
 
 
   name="signaltap_ii_logic_analyzer_0"
   kind="altera_signaltap_ii_logic_analyzer"
   version="16.0"
   enabled="1"
   autoexport="1">
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	16	daniel.kho
2
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4			`name="$${FILENAME}"`
5			`displayName="$${FILENAME}"`
6			`version="1.0"`
7			`description=""`
8			`tags="INTERNAL_COMPONENT=true"`
9			`categories="" />`
10
11			`{`
12			`element signaltap_ii_logic_analyzer_0`
13			`{`
14			`datum _sortIndex`
15			`{`
16			`value = "0";`
17			`type = "int";`
18			`}`
19			`}`
20			`}`
21			`]]>`
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42			`name="acq_clk"`
43			`internal="signaltap_ii_logic_analyzer_0.acq_clk"`
44			`type="clock"`
45			`dir="end">`
46
47
48
49			`name="tap"`
50			`internal="signaltap_ii_logic_analyzer_0.tap"`
51			`type="conduit"`
52			`dir="end">`
53
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57			`name="signaltap_ii_logic_analyzer_0"`
58			`kind="altera_signaltap_ii_logic_analyzer"`
59			`version="16.0"`
60			`enabled="1"`
61			`autoexport="1">`
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Subversion Repositories fir_wishbone

[/] [fir_wishbone/] [trunk/] [workspaces/] [synthesis/] [quartus/] [stp.qsys] - Blame information for rev 16