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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [FluidCore.twr] - Blame information for rev 4

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Line No. Rev Author Line
1 4 azmathmoos 
--------------------------------------------------------------------------------
2 
Release 14.5 Trace  (nt)
3 
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
4 
 
5 
C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
6 
3 -fastpaths -xml FluidCore.twx FluidCore.ncd -o FluidCore.twr FluidCore.pcf
7 
 
8 
Design file:              FluidCore.ncd
9 
Physical constraint file: FluidCore.pcf
10 
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-03-26)
11 
Report level:             verbose report
12 
 
13 
Environment Variable      Effect
14 
--------------------      ------
15 
NONE                      No environment variables were set
16 
--------------------------------------------------------------------------------
17 
 
18 
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
19 
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
20 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
21 
   option. All paths that are not constrained will be reported in the
22 
   unconstrained paths section(s) of the report.
23 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
24 
   a 50 Ohm transmission line loading model.  For the details of this model,
25 
   and for more information on accounting for different loading conditions,
26 
   please see the device datasheet.
27 
INFO:Timing:3390 - This architecture does not support a default System Jitter
28 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
29 
   Uncertainty calculation.
30 
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
31 
   'Phase Error' calculations, these terms will be zero in the Clock
32 
   Uncertainty calculation.  Please make appropriate modification to
33 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
34 
   Error.
35 
 
36 
 
37 
 
38 
Data Sheet report:
39 
-----------------
40 
All values displayed in nanoseconds (ns)
41 
 
42 
Setup/Hold to clock Clk
43 
-----------------+------------+------------+------------------+--------+
44 
                 |Max Setup to|Max Hold to |                  | Clock  |
45 
Source           | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
46 
-----------------+------------+------------+------------------+--------+
47 
Interrupt<0>     |    5.379(R)|   -1.465(R)|Clk_IBUF          |   0.000|
48 
Interrupt<1>     |    5.324(R)|   -1.421(R)|Clk_IBUF          |   0.000|
49 
Interrupt<2>     |    5.396(R)|   -1.479(R)|Clk_IBUF          |   0.000|
50 
exInstruction<1> |    4.650(R)|   -0.772(R)|Clk_IBUF          |   0.000|
51 
exInstruction<2> |    4.655(R)|   -0.779(R)|Clk_IBUF          |   0.000|
52 
exInstruction<3> |    4.655(R)|   -0.779(R)|Clk_IBUF          |   0.000|
53 
exInstruction<4> |    4.686(R)|   -0.815(R)|Clk_IBUF          |   0.000|
54 
exInstruction<5> |    4.693(R)|   -0.823(R)|Clk_IBUF          |   0.000|
55 
exInstruction<6> |    4.693(R)|   -0.823(R)|Clk_IBUF          |   0.000|
56 
exInstruction<7> |    4.672(R)|   -0.799(R)|Clk_IBUF          |   0.000|
57 
exInstruction<8> |    4.672(R)|   -0.799(R)|Clk_IBUF          |   0.000|
58 
exInstruction<9> |    4.665(R)|   -0.791(R)|Clk_IBUF          |   0.000|
59 
exInstruction<10>|    4.665(R)|   -0.791(R)|Clk_IBUF          |   0.000|
60 
exInstruction<11>|    4.676(R)|   -0.803(R)|Clk_IBUF          |   0.000|
61 
exInstruction<12>|    4.676(R)|   -0.803(R)|Clk_IBUF          |   0.000|
62 
exInstruction<13>|    4.686(R)|   -0.815(R)|Clk_IBUF          |   0.000|
63 
exInstruction<14>|    4.679(R)|   -0.807(R)|Clk_IBUF          |   0.000|
64 
exInstruction<15>|    4.679(R)|   -0.807(R)|Clk_IBUF          |   0.000|
65 
exMemoryData<0>  |   -5.878(R)|    9.222(R)|EX_MEM_reg/Clk_RST|   0.000|
66 
exMemoryData<1>  |   -6.204(R)|    9.490(R)|EX_MEM_reg/Clk_RST|   0.000|
67 
exMemoryData<2>  |   -5.932(R)|    9.274(R)|EX_MEM_reg/Clk_RST|   0.000|
68 
exMemoryData<3>  |   -5.402(R)|    8.850(R)|EX_MEM_reg/Clk_RST|   0.000|
69 
exMemoryData<4>  |   -5.524(R)|    8.945(R)|EX_MEM_reg/Clk_RST|   0.000|
70 
exMemoryData<5>  |   -5.287(R)|    8.749(R)|EX_MEM_reg/Clk_RST|   0.000|
71 
exMemoryData<6>  |   -5.823(R)|    9.179(R)|EX_MEM_reg/Clk_RST|   0.000|
72 
exMemoryData<7>  |   -5.322(R)|    8.778(R)|EX_MEM_reg/Clk_RST|   0.000|
73 
exMemoryData<8>  |   -5.970(R)|    9.305(R)|EX_MEM_reg/Clk_RST|   0.000|
74 
exMemoryData<9>  |   -6.218(R)|    9.497(R)|EX_MEM_reg/Clk_RST|   0.000|
75 
exMemoryData<10> |   -5.903(R)|    9.250(R)|EX_MEM_reg/Clk_RST|   0.000|
76 
exMemoryData<11> |   -6.308(R)|    9.574(R)|EX_MEM_reg/Clk_RST|   0.000|
77 
exMemoryData<12> |   -6.444(R)|    9.683(R)|EX_MEM_reg/Clk_RST|   0.000|
78 
exMemoryData<13> |   -6.502(R)|    9.733(R)|EX_MEM_reg/Clk_RST|   0.000|
79 
exMemoryData<14> |   -6.799(R)|    9.970(R)|EX_MEM_reg/Clk_RST|   0.000|
80 
exMemoryData<15> |   -6.198(R)|    9.493(R)|EX_MEM_reg/Clk_RST|   0.000|
81 
exMemoryData<16> |   -6.809(R)|    9.982(R)|EX_MEM_reg/Clk_RST|   0.000|
82 
exMemoryData<17> |   -6.834(R)|   10.002(R)|EX_MEM_reg/Clk_RST|   0.000|
83 
exMemoryData<18> |   -7.108(R)|   10.224(R)|EX_MEM_reg/Clk_RST|   0.000|
84 
exMemoryData<19> |   -6.893(R)|   10.051(R)|EX_MEM_reg/Clk_RST|   0.000|
85 
exMemoryData<20> |   -6.523(R)|    9.749(R)|EX_MEM_reg/Clk_RST|   0.000|
86 
exMemoryData<21> |   -6.286(R)|    9.559(R)|EX_MEM_reg/Clk_RST|   0.000|
87 
exMemoryData<22> |   -6.984(R)|   10.121(R)|EX_MEM_reg/Clk_RST|   0.000|
88 
exMemoryData<23> |   -6.672(R)|    9.869(R)|EX_MEM_reg/Clk_RST|   0.000|
89 
exMemoryData<24> |   -6.406(R)|    9.656(R)|EX_MEM_reg/Clk_RST|   0.000|
90 
exMemoryData<25> |   -6.920(R)|   10.066(R)|EX_MEM_reg/Clk_RST|   0.000|
91 
exMemoryData<26> |   -6.545(R)|    9.764(R)|EX_MEM_reg/Clk_RST|   0.000|
92 
exMemoryData<27> |   -6.366(R)|    9.620(R)|EX_MEM_reg/Clk_RST|   0.000|
93 
exMemoryData<28> |   -6.615(R)|    9.818(R)|EX_MEM_reg/Clk_RST|   0.000|
94 
exMemoryData<29> |   -6.201(R)|    9.481(R)|EX_MEM_reg/Clk_RST|   0.000|
95 
exMemoryData<30> |   -6.833(R)|    9.992(R)|EX_MEM_reg/Clk_RST|   0.000|
96 
exMemoryData<31> |   -6.453(R)|    9.682(R)|EX_MEM_reg/Clk_RST|   0.000|
97 
-----------------+------------+------------+------------------+--------+
98 
 
99 
Setup/Hold to clock Interrupt<3>
100 
------------+------------+------------+------------------+--------+
101 
            |Max Setup to|Max Hold to |                  | Clock  |
102 
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
103 
------------+------------+------------+------------------+--------+
104 
Interrupt<2>|    1.212(F)|    0.240(F)|Interrupt_3_IBUF  |   0.000|
105 
------------+------------+------------+------------------+--------+
106 
 
107 
Setup/Hold to clock RST
108 
----------------+------------+------------+------------------+--------+
109 
                |Max Setup to|Max Hold to |                  | Clock  |
110 
Source          | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
111 
----------------+------------+------------+------------------+--------+
112 
exMemoryData<0> |   -2.686(R)|    5.231(R)|EX_MEM_reg/Clk_RST|   0.000|
113 
exMemoryData<1> |   -3.012(R)|    5.499(R)|EX_MEM_reg/Clk_RST|   0.000|
114 
exMemoryData<2> |   -2.740(R)|    5.283(R)|EX_MEM_reg/Clk_RST|   0.000|
115 
exMemoryData<3> |   -2.210(R)|    4.859(R)|EX_MEM_reg/Clk_RST|   0.000|
116 
exMemoryData<4> |   -2.332(R)|    4.954(R)|EX_MEM_reg/Clk_RST|   0.000|
117 
exMemoryData<5> |   -2.095(R)|    4.758(R)|EX_MEM_reg/Clk_RST|   0.000|
118 
exMemoryData<6> |   -2.631(R)|    5.188(R)|EX_MEM_reg/Clk_RST|   0.000|
119 
exMemoryData<7> |   -2.130(R)|    4.787(R)|EX_MEM_reg/Clk_RST|   0.000|
120 
exMemoryData<8> |   -2.778(R)|    5.314(R)|EX_MEM_reg/Clk_RST|   0.000|
121 
exMemoryData<9> |   -3.026(R)|    5.506(R)|EX_MEM_reg/Clk_RST|   0.000|
122 
exMemoryData<10>|   -2.711(R)|    5.259(R)|EX_MEM_reg/Clk_RST|   0.000|
123 
exMemoryData<11>|   -3.116(R)|    5.583(R)|EX_MEM_reg/Clk_RST|   0.000|
124 
exMemoryData<12>|   -3.252(R)|    5.692(R)|EX_MEM_reg/Clk_RST|   0.000|
125 
exMemoryData<13>|   -3.310(R)|    5.742(R)|EX_MEM_reg/Clk_RST|   0.000|
126 
exMemoryData<14>|   -3.607(R)|    5.979(R)|EX_MEM_reg/Clk_RST|   0.000|
127 
exMemoryData<15>|   -3.006(R)|    5.502(R)|EX_MEM_reg/Clk_RST|   0.000|
128 
exMemoryData<16>|   -3.617(R)|    5.991(R)|EX_MEM_reg/Clk_RST|   0.000|
129 
exMemoryData<17>|   -3.642(R)|    6.011(R)|EX_MEM_reg/Clk_RST|   0.000|
130 
exMemoryData<18>|   -3.916(R)|    6.233(R)|EX_MEM_reg/Clk_RST|   0.000|
131 
exMemoryData<19>|   -3.701(R)|    6.060(R)|EX_MEM_reg/Clk_RST|   0.000|
132 
exMemoryData<20>|   -3.331(R)|    5.758(R)|EX_MEM_reg/Clk_RST|   0.000|
133 
exMemoryData<21>|   -3.094(R)|    5.568(R)|EX_MEM_reg/Clk_RST|   0.000|
134 
exMemoryData<22>|   -3.792(R)|    6.130(R)|EX_MEM_reg/Clk_RST|   0.000|
135 
exMemoryData<23>|   -3.480(R)|    5.878(R)|EX_MEM_reg/Clk_RST|   0.000|
136 
exMemoryData<24>|   -3.214(R)|    5.665(R)|EX_MEM_reg/Clk_RST|   0.000|
137 
exMemoryData<25>|   -3.728(R)|    6.075(R)|EX_MEM_reg/Clk_RST|   0.000|
138 
exMemoryData<26>|   -3.353(R)|    5.773(R)|EX_MEM_reg/Clk_RST|   0.000|
139 
exMemoryData<27>|   -3.174(R)|    5.629(R)|EX_MEM_reg/Clk_RST|   0.000|
140 
exMemoryData<28>|   -3.423(R)|    5.827(R)|EX_MEM_reg/Clk_RST|   0.000|
141 
exMemoryData<29>|   -3.009(R)|    5.490(R)|EX_MEM_reg/Clk_RST|   0.000|
142 
exMemoryData<30>|   -3.641(R)|    6.001(R)|EX_MEM_reg/Clk_RST|   0.000|
143 
exMemoryData<31>|   -3.261(R)|    5.691(R)|EX_MEM_reg/Clk_RST|   0.000|
144 
----------------+------------+------------+------------------+--------+
145 
 
146 
Clock Clk to Pad
147 
----------------+------------+------------------+--------+
148 
                | clk (edge) |                  | Clock  |
149 
Destination     |   to PAD   |Internal Clock(s) | Phase  |
150 
----------------+------------+------------------+--------+
151 
exInstAddr<0>   |    6.154(R)|Clk_IBUF          |   0.000|
152 
exInstAddr<1>   |    6.154(R)|Clk_IBUF          |   0.000|
153 
exInstAddr<2>   |    6.171(R)|Clk_IBUF          |   0.000|
154 
exInstAddr<3>   |    6.175(R)|Clk_IBUF          |   0.000|
155 
exInstAddr<4>   |    6.159(R)|Clk_IBUF          |   0.000|
156 
exInstAddr<5>   |    6.167(R)|Clk_IBUF          |   0.000|
157 
exMemoryAddr<0> |   15.381(R)|EX_MEM_reg/Clk_RST|   0.000|
158 
exMemoryAddr<1> |   15.370(R)|EX_MEM_reg/Clk_RST|   0.000|
159 
exMemoryAddr<2> |   15.370(R)|EX_MEM_reg/Clk_RST|   0.000|
160 
exMemoryAddr<3> |   15.370(R)|EX_MEM_reg/Clk_RST|   0.000|
161 
exMemoryClk     |   21.643(R)|EX_MEM_reg/Clk_RST|   0.000|
162 
exMemoryData<0> |   21.222(R)|EX_MEM_reg/Clk_RST|   0.000|
163 
exMemoryData<1> |   21.750(R)|EX_MEM_reg/Clk_RST|   0.000|
164 
exMemoryData<2> |   21.487(R)|EX_MEM_reg/Clk_RST|   0.000|
165 
exMemoryData<3> |   21.726(R)|EX_MEM_reg/Clk_RST|   0.000|
166 
exMemoryData<4> |   21.766(R)|EX_MEM_reg/Clk_RST|   0.000|
167 
exMemoryData<5> |   21.762(R)|EX_MEM_reg/Clk_RST|   0.000|
168 
exMemoryData<6> |   21.727(R)|EX_MEM_reg/Clk_RST|   0.000|
169 
exMemoryData<7> |   22.037(R)|EX_MEM_reg/Clk_RST|   0.000|
170 
exMemoryData<8> |   22.002(R)|EX_MEM_reg/Clk_RST|   0.000|
171 
exMemoryData<9> |   20.815(R)|EX_MEM_reg/Clk_RST|   0.000|
172 
exMemoryData<10>|   20.580(R)|EX_MEM_reg/Clk_RST|   0.000|
173 
exMemoryData<11>|   20.533(R)|EX_MEM_reg/Clk_RST|   0.000|
174 
exMemoryData<12>|   20.502(R)|EX_MEM_reg/Clk_RST|   0.000|
175 
exMemoryData<13>|   20.245(R)|EX_MEM_reg/Clk_RST|   0.000|
176 
exMemoryData<14>|   20.532(R)|EX_MEM_reg/Clk_RST|   0.000|
177 
exMemoryData<15>|   20.520(R)|EX_MEM_reg/Clk_RST|   0.000|
178 
exMemoryData<16>|   20.826(R)|EX_MEM_reg/Clk_RST|   0.000|
179 
exMemoryData<17>|   20.806(R)|EX_MEM_reg/Clk_RST|   0.000|
180 
exMemoryData<18>|   21.107(R)|EX_MEM_reg/Clk_RST|   0.000|
181 
exMemoryData<19>|   21.110(R)|EX_MEM_reg/Clk_RST|   0.000|
182 
exMemoryData<20>|   20.926(R)|EX_MEM_reg/Clk_RST|   0.000|
183 
exMemoryData<21>|   21.122(R)|EX_MEM_reg/Clk_RST|   0.000|
184 
exMemoryData<22>|   21.207(R)|EX_MEM_reg/Clk_RST|   0.000|
185 
exMemoryData<23>|   21.206(R)|EX_MEM_reg/Clk_RST|   0.000|
186 
exMemoryData<24>|   21.400(R)|EX_MEM_reg/Clk_RST|   0.000|
187 
exMemoryData<25>|   21.482(R)|EX_MEM_reg/Clk_RST|   0.000|
188 
exMemoryData<26>|   21.677(R)|EX_MEM_reg/Clk_RST|   0.000|
189 
exMemoryData<27>|   21.762(R)|EX_MEM_reg/Clk_RST|   0.000|
190 
exMemoryData<28>|   21.764(R)|EX_MEM_reg/Clk_RST|   0.000|
191 
exMemoryData<29>|   21.962(R)|EX_MEM_reg/Clk_RST|   0.000|
192 
exMemoryData<30>|   21.766(R)|EX_MEM_reg/Clk_RST|   0.000|
193 
exMemoryData<31>|   22.237(R)|EX_MEM_reg/Clk_RST|   0.000|
194 
exMemoryWrite   |   20.980(R)|EX_MEM_reg/Clk_RST|   0.000|
195 
----------------+------------+------------------+--------+
196 
 
197 
Clock RST to Pad
198 
----------------+------------+------------------+--------+
199 
                | clk (edge) |                  | Clock  |
200 
Destination     |   to PAD   |Internal Clock(s) | Phase  |
201 
----------------+------------+------------------+--------+
202 
exMemoryAddr<0> |   11.390(R)|EX_MEM_reg/Clk_RST|   0.000|
203 
exMemoryAddr<1> |   11.379(R)|EX_MEM_reg/Clk_RST|   0.000|
204 
exMemoryAddr<2> |   11.379(R)|EX_MEM_reg/Clk_RST|   0.000|
205 
exMemoryAddr<3> |   11.379(R)|EX_MEM_reg/Clk_RST|   0.000|
206 
exMemoryClk     |   17.652(R)|EX_MEM_reg/Clk_RST|   0.000|
207 
exMemoryData<0> |   17.231(R)|EX_MEM_reg/Clk_RST|   0.000|
208 
exMemoryData<1> |   17.759(R)|EX_MEM_reg/Clk_RST|   0.000|
209 
exMemoryData<2> |   17.496(R)|EX_MEM_reg/Clk_RST|   0.000|
210 
exMemoryData<3> |   17.735(R)|EX_MEM_reg/Clk_RST|   0.000|
211 
exMemoryData<4> |   17.775(R)|EX_MEM_reg/Clk_RST|   0.000|
212 
exMemoryData<5> |   17.771(R)|EX_MEM_reg/Clk_RST|   0.000|
213 
exMemoryData<6> |   17.736(R)|EX_MEM_reg/Clk_RST|   0.000|
214 
exMemoryData<7> |   18.046(R)|EX_MEM_reg/Clk_RST|   0.000|
215 
exMemoryData<8> |   18.011(R)|EX_MEM_reg/Clk_RST|   0.000|
216 
exMemoryData<9> |   16.824(R)|EX_MEM_reg/Clk_RST|   0.000|
217 
exMemoryData<10>|   16.589(R)|EX_MEM_reg/Clk_RST|   0.000|
218 
exMemoryData<11>|   16.542(R)|EX_MEM_reg/Clk_RST|   0.000|
219 
exMemoryData<12>|   16.511(R)|EX_MEM_reg/Clk_RST|   0.000|
220 
exMemoryData<13>|   16.254(R)|EX_MEM_reg/Clk_RST|   0.000|
221 
exMemoryData<14>|   16.541(R)|EX_MEM_reg/Clk_RST|   0.000|
222 
exMemoryData<15>|   16.529(R)|EX_MEM_reg/Clk_RST|   0.000|
223 
exMemoryData<16>|   16.835(R)|EX_MEM_reg/Clk_RST|   0.000|
224 
exMemoryData<17>|   16.815(R)|EX_MEM_reg/Clk_RST|   0.000|
225 
exMemoryData<18>|   17.116(R)|EX_MEM_reg/Clk_RST|   0.000|
226 
exMemoryData<19>|   17.119(R)|EX_MEM_reg/Clk_RST|   0.000|
227 
exMemoryData<20>|   16.935(R)|EX_MEM_reg/Clk_RST|   0.000|
228 
exMemoryData<21>|   17.131(R)|EX_MEM_reg/Clk_RST|   0.000|
229 
exMemoryData<22>|   17.216(R)|EX_MEM_reg/Clk_RST|   0.000|
230 
exMemoryData<23>|   17.215(R)|EX_MEM_reg/Clk_RST|   0.000|
231 
exMemoryData<24>|   17.409(R)|EX_MEM_reg/Clk_RST|   0.000|
232 
exMemoryData<25>|   17.491(R)|EX_MEM_reg/Clk_RST|   0.000|
233 
exMemoryData<26>|   17.686(R)|EX_MEM_reg/Clk_RST|   0.000|
234 
exMemoryData<27>|   17.771(R)|EX_MEM_reg/Clk_RST|   0.000|
235 
exMemoryData<28>|   17.773(R)|EX_MEM_reg/Clk_RST|   0.000|
236 
exMemoryData<29>|   17.971(R)|EX_MEM_reg/Clk_RST|   0.000|
237 
exMemoryData<30>|   17.775(R)|EX_MEM_reg/Clk_RST|   0.000|
238 
exMemoryData<31>|   18.246(R)|EX_MEM_reg/Clk_RST|   0.000|
239 
exMemoryWrite   |   16.989(R)|EX_MEM_reg/Clk_RST|   0.000|
240 
----------------+------------+------------------+--------+
241 
 
242 
Clock to Setup on destination clock Clk
243 
---------------+---------+---------+---------+---------+
244 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
245 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
246 
---------------+---------+---------+---------+---------+
247 
Clk            |   27.183|   10.335|         |         |
248 
Interrupt<3>   |    5.967|    6.776|         |         |
249 
RST            |   27.183|    5.840|         |         |
250 
---------------+---------+---------+---------+---------+
251 
 
252 
Clock to Setup on destination clock RST
253 
---------------+---------+---------+---------+---------+
254 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
255 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
256 
---------------+---------+---------+---------+---------+
257 
Clk            |    6.954|         |         |         |
258 
RST            |    6.937|    2.152|         |         |
259 
---------------+---------+---------+---------+---------+
260 
 
261 
Pad to Pad
262 
---------------+---------------+---------+
263 
Source Pad     |Destination Pad|  Delay  |
264 
---------------+---------------+---------+
265 
Clk            |exMemoryClk    |    6.810|
266 
---------------+---------------+---------+
267 
 
268 
 
269 
Analysis completed Mon Apr 27 23:05:09 2015
270 
--------------------------------------------------------------------------------
271 
 
272 
Trace Settings:
273 
-------------------------
274 
Trace Settings
275 
 
276 
Peak Memory Usage: 142 MB
277 
 
278 
 
279 
 

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