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azmathmoos |
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Release 14.5 Trace (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
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3 -fastpaths -xml FluidCore_preroute.twx FluidCore_map.ncd -o
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FluidCore_preroute.twr FluidCore.pcf -ucf Test_Bed.ucf -ucf FluidCore.ucf
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Design file: FluidCore_map.ncd
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Physical constraint file: FluidCore.pcf
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Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-03-26)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3284 - This timing report was generated using estimated delay
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information. For accurate numbers, please refer to the post Place and Route
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timing report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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INFO:Timing:3390 - This architecture does not support a default System Jitter
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value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
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Uncertainty calculation.
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INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
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'Phase Error' calculations, these terms will be zero in the Clock
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Uncertainty calculation. Please make appropriate modification to
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SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
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Error.
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================================================================================
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Timing constraint: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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12461 paths analyzed, 1856 endpoints analyzed, 1143 failing endpoints
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1143 timing errors detected. (1128 setup errors, 15 hold errors, 0 component switching limit errors)
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Minimum period is 10.716ns.
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--------------------------------------------------------------------------------
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Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINA), 43 paths
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--------------------------------------------------------------------------------
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Slack (setup path): -5.716ns (requirement - (data path - clock path skew + uncertainty))
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Source: IF_ID_reg/pipeline_register_4 (FF)
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
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Requirement: 5.000ns
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Data Path Delay: 8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
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Clock Path Skew: -1.972ns (2.137 - 4.109)
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Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
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Destination Clock: Clk_IBUF rising at 5.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
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IF_ID_reg/pipeline_register_4
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SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
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SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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ID_Stage_inst/rrr_adm_SW0
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SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
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SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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ID_Stage_inst/rrr_adm
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SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
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SLICE_X65Y43.X Tilo 0.704 reg_a<2>
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ID_Stage_inst/RF_a<2>1
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SLICE_X52Y40.F1 net (fanout=128) e 1.207 reg_a<2>
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SLICE_X52Y40.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<7>
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Reg_File_inst/mux29_4
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Reg_File_inst/mux29_3_f5
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SLICE_X52Y40.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux29_3_f5
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SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
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Reg_File_inst/mux29_2_f6
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ID_Stage_inst/buff_op_a_7
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------------------------------------------------- ---------------------------
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Total 8.744ns (4.389ns logic, 4.355ns route)
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(50.2% logic, 49.8% route)
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--------------------------------------------------------------------------------
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Slack (setup path): -5.716ns (requirement - (data path - clock path skew + uncertainty))
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Source: IF_ID_reg/pipeline_register_4 (FF)
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
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Requirement: 5.000ns
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Data Path Delay: 8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
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Clock Path Skew: -1.972ns (2.137 - 4.109)
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Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
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Destination Clock: Clk_IBUF rising at 5.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
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IF_ID_reg/pipeline_register_4
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SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
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SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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ID_Stage_inst/rrr_adm_SW0
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| 107 |
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SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
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| 108 |
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SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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| 109 |
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ID_Stage_inst/rrr_adm
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SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
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SLICE_X65Y43.X Tilo 0.704 reg_a<2>
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ID_Stage_inst/RF_a<2>1
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| 113 |
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SLICE_X52Y40.G1 net (fanout=128) e 1.207 reg_a<2>
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| 114 |
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SLICE_X52Y40.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<7>
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Reg_File_inst/mux29_5
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Reg_File_inst/mux29_3_f5
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SLICE_X52Y40.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux29_3_f5
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SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
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Reg_File_inst/mux29_2_f6
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ID_Stage_inst/buff_op_a_7
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------------------------------------------------- ---------------------------
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Total 8.744ns (4.389ns logic, 4.355ns route)
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(50.2% logic, 49.8% route)
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| 124 |
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--------------------------------------------------------------------------------
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Slack (setup path): -5.604ns (requirement - (data path - clock path skew + uncertainty))
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Source: IF_ID_reg/pipeline_register_2 (FF)
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| 128 |
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
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Requirement: 5.000ns
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Data Path Delay: 8.632ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
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Clock Path Skew: -1.972ns (2.137 - 4.109)
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| 132 |
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Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
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| 133 |
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Destination Clock: Clk_IBUF rising at 5.000ns
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Clock Uncertainty: 0.000ns
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| 135 |
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| 136 |
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Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_7
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| 137 |
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Location Delay type Delay(ns) Physical Resource
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| 138 |
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X36Y62.YQ Tcko 0.652 IF_ID_reg/pipeline_register<1>
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IF_ID_reg/pipeline_register_2
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| 142 |
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SLICE_X36Y63.G1 net (fanout=14) e 0.487 IF_ID_reg/pipeline_register<2>
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| 143 |
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SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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| 144 |
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ID_Stage_inst/rrr_adm_SW0
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| 145 |
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SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
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| 146 |
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SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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| 147 |
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ID_Stage_inst/rrr_adm
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| 148 |
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SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
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| 149 |
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SLICE_X65Y43.X Tilo 0.704 reg_a<2>
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| 150 |
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ID_Stage_inst/RF_a<2>1
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| 151 |
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SLICE_X52Y40.G1 net (fanout=128) e 1.207 reg_a<2>
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| 152 |
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SLICE_X52Y40.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<7>
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| 153 |
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Reg_File_inst/mux29_5
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Reg_File_inst/mux29_3_f5
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| 155 |
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SLICE_X52Y40.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux29_3_f5
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| 156 |
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SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
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| 157 |
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Reg_File_inst/mux29_2_f6
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| 158 |
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ID_Stage_inst/buff_op_a_7
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------------------------------------------------- ---------------------------
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Total 8.632ns (4.449ns logic, 4.183ns route)
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(51.5% logic, 48.5% route)
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| 162 |
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--------------------------------------------------------------------------------
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Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINB), 43 paths
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--------------------------------------------------------------------------------
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Slack (setup path): -5.716ns (requirement - (data path - clock path skew + uncertainty))
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Source: IF_ID_reg/pipeline_register_4 (FF)
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
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Requirement: 5.000ns
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| 171 |
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Data Path Delay: 8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
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| 172 |
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Clock Path Skew: -1.972ns (2.137 - 4.109)
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| 173 |
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Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
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| 174 |
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Destination Clock: Clk_IBUF rising at 5.000ns
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| 175 |
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Clock Uncertainty: 0.000ns
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| 176 |
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|
| 177 |
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Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
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| 178 |
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Location Delay type Delay(ns) Physical Resource
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| 179 |
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Logical Resource(s)
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| 180 |
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------------------------------------------------- -------------------
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| 181 |
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SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
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| 182 |
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IF_ID_reg/pipeline_register_4
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| 183 |
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SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
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| 184 |
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SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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| 185 |
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ID_Stage_inst/rrr_adm_SW0
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| 186 |
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SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
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| 187 |
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SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
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| 188 |
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ID_Stage_inst/rrr_adm
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| 189 |
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SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
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| 190 |
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SLICE_X65Y43.X Tilo 0.704 reg_a<2>
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| 191 |
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ID_Stage_inst/RF_a<2>1
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| 192 |
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SLICE_X52Y41.F1 net (fanout=128) e 1.207 reg_a<2>
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| 193 |
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SLICE_X52Y41.F5 Tif5 1.033 Reg_File_inst/mux29_4_f5
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| 194 |
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Reg_File_inst/mux29_51
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| 195 |
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Reg_File_inst/mux29_4_f5
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| 196 |
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SLICE_X52Y40.FXINB net (fanout=1) e 0.000 Reg_File_inst/mux29_4_f5
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| 197 |
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SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
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| 198 |
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Reg_File_inst/mux29_2_f6
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| 199 |
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ID_Stage_inst/buff_op_a_7
|
| 200 |
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------------------------------------------------- ---------------------------
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| 201 |
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Total 8.744ns (4.389ns logic, 4.355ns route)
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| 202 |
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(50.2% logic, 49.8% route)
|
| 203 |
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|
| 204 |
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--------------------------------------------------------------------------------
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| 205 |
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Slack (setup path): -5.716ns (requirement - (data path - clock path skew + uncertainty))
|
| 206 |
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Source: IF_ID_reg/pipeline_register_4 (FF)
|
| 207 |
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
|
| 208 |
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Requirement: 5.000ns
|
| 209 |
|
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Data Path Delay: 8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
|
| 210 |
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Clock Path Skew: -1.972ns (2.137 - 4.109)
|
| 211 |
|
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Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
|
| 212 |
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Destination Clock: Clk_IBUF rising at 5.000ns
|
| 213 |
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Clock Uncertainty: 0.000ns
|
| 214 |
|
|
|
| 215 |
|
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Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
|
| 216 |
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Location Delay type Delay(ns) Physical Resource
|
| 217 |
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Logical Resource(s)
|
| 218 |
|
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------------------------------------------------- -------------------
|
| 219 |
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SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
|
| 220 |
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IF_ID_reg/pipeline_register_4
|
| 221 |
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SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
|
| 222 |
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SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 223 |
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ID_Stage_inst/rrr_adm_SW0
|
| 224 |
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SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
|
| 225 |
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SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 226 |
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ID_Stage_inst/rrr_adm
|
| 227 |
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SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
|
| 228 |
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SLICE_X65Y43.X Tilo 0.704 reg_a<2>
|
| 229 |
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ID_Stage_inst/RF_a<2>1
|
| 230 |
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SLICE_X52Y41.G1 net (fanout=128) e 1.207 reg_a<2>
|
| 231 |
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SLICE_X52Y41.F5 Tif5 1.033 Reg_File_inst/mux29_4_f5
|
| 232 |
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Reg_File_inst/mux29_6
|
| 233 |
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Reg_File_inst/mux29_4_f5
|
| 234 |
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SLICE_X52Y40.FXINB net (fanout=1) e 0.000 Reg_File_inst/mux29_4_f5
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| 235 |
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SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
|
| 236 |
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Reg_File_inst/mux29_2_f6
|
| 237 |
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ID_Stage_inst/buff_op_a_7
|
| 238 |
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------------------------------------------------- ---------------------------
|
| 239 |
|
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Total 8.744ns (4.389ns logic, 4.355ns route)
|
| 240 |
|
|
(50.2% logic, 49.8% route)
|
| 241 |
|
|
|
| 242 |
|
|
--------------------------------------------------------------------------------
|
| 243 |
|
|
Slack (setup path): -5.604ns (requirement - (data path - clock path skew + uncertainty))
|
| 244 |
|
|
Source: IF_ID_reg/pipeline_register_2 (FF)
|
| 245 |
|
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Destination: ID_Stage_inst/buff_op_a_7 (LATCH)
|
| 246 |
|
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Requirement: 5.000ns
|
| 247 |
|
|
Data Path Delay: 8.632ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
|
| 248 |
|
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Clock Path Skew: -1.972ns (2.137 - 4.109)
|
| 249 |
|
|
Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
|
| 250 |
|
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Destination Clock: Clk_IBUF rising at 5.000ns
|
| 251 |
|
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Clock Uncertainty: 0.000ns
|
| 252 |
|
|
|
| 253 |
|
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Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_7
|
| 254 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 255 |
|
|
Logical Resource(s)
|
| 256 |
|
|
------------------------------------------------- -------------------
|
| 257 |
|
|
SLICE_X36Y62.YQ Tcko 0.652 IF_ID_reg/pipeline_register<1>
|
| 258 |
|
|
IF_ID_reg/pipeline_register_2
|
| 259 |
|
|
SLICE_X36Y63.G1 net (fanout=14) e 0.487 IF_ID_reg/pipeline_register<2>
|
| 260 |
|
|
SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 261 |
|
|
ID_Stage_inst/rrr_adm_SW0
|
| 262 |
|
|
SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
|
| 263 |
|
|
SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 264 |
|
|
ID_Stage_inst/rrr_adm
|
| 265 |
|
|
SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
|
| 266 |
|
|
SLICE_X65Y43.X Tilo 0.704 reg_a<2>
|
| 267 |
|
|
ID_Stage_inst/RF_a<2>1
|
| 268 |
|
|
SLICE_X52Y41.G1 net (fanout=128) e 1.207 reg_a<2>
|
| 269 |
|
|
SLICE_X52Y41.F5 Tif5 1.033 Reg_File_inst/mux29_4_f5
|
| 270 |
|
|
Reg_File_inst/mux29_6
|
| 271 |
|
|
Reg_File_inst/mux29_4_f5
|
| 272 |
|
|
SLICE_X52Y40.FXINB net (fanout=1) e 0.000 Reg_File_inst/mux29_4_f5
|
| 273 |
|
|
SLICE_X52Y40.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<7>
|
| 274 |
|
|
Reg_File_inst/mux29_2_f6
|
| 275 |
|
|
ID_Stage_inst/buff_op_a_7
|
| 276 |
|
|
------------------------------------------------- ---------------------------
|
| 277 |
|
|
Total 8.632ns (4.449ns logic, 4.183ns route)
|
| 278 |
|
|
(51.5% logic, 48.5% route)
|
| 279 |
|
|
|
| 280 |
|
|
--------------------------------------------------------------------------------
|
| 281 |
|
|
|
| 282 |
|
|
Paths for end point ID_Stage_inst/buff_op_a_18 (SLICE_X64Y52.FXINA), 43 paths
|
| 283 |
|
|
--------------------------------------------------------------------------------
|
| 284 |
|
|
Slack (setup path): -5.680ns (requirement - (data path - clock path skew + uncertainty))
|
| 285 |
|
|
Source: IF_ID_reg/pipeline_register_4 (FF)
|
| 286 |
|
|
Destination: ID_Stage_inst/buff_op_a_18 (LATCH)
|
| 287 |
|
|
Requirement: 5.000ns
|
| 288 |
|
|
Data Path Delay: 8.708ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
|
| 289 |
|
|
Clock Path Skew: -1.972ns (2.137 - 4.109)
|
| 290 |
|
|
Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
|
| 291 |
|
|
Destination Clock: Clk_IBUF rising at 5.000ns
|
| 292 |
|
|
Clock Uncertainty: 0.000ns
|
| 293 |
|
|
|
| 294 |
|
|
Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_18
|
| 295 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 296 |
|
|
Logical Resource(s)
|
| 297 |
|
|
------------------------------------------------- -------------------
|
| 298 |
|
|
SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
|
| 299 |
|
|
IF_ID_reg/pipeline_register_4
|
| 300 |
|
|
SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
|
| 301 |
|
|
SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 302 |
|
|
ID_Stage_inst/rrr_adm_SW0
|
| 303 |
|
|
SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
|
| 304 |
|
|
SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 305 |
|
|
ID_Stage_inst/rrr_adm
|
| 306 |
|
|
SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
|
| 307 |
|
|
SLICE_X65Y43.X Tilo 0.704 reg_a<2>
|
| 308 |
|
|
ID_Stage_inst/RF_a<2>1
|
| 309 |
|
|
SLICE_X64Y52.F1 net (fanout=128) e 1.171 reg_a<2>
|
| 310 |
|
|
SLICE_X64Y52.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<18>
|
| 311 |
|
|
Reg_File_inst/mux9_4
|
| 312 |
|
|
Reg_File_inst/mux9_3_f5
|
| 313 |
|
|
SLICE_X64Y52.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux9_3_f5
|
| 314 |
|
|
SLICE_X64Y52.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<18>
|
| 315 |
|
|
Reg_File_inst/mux9_2_f6
|
| 316 |
|
|
ID_Stage_inst/buff_op_a_18
|
| 317 |
|
|
------------------------------------------------- ---------------------------
|
| 318 |
|
|
Total 8.708ns (4.389ns logic, 4.319ns route)
|
| 319 |
|
|
(50.4% logic, 49.6% route)
|
| 320 |
|
|
|
| 321 |
|
|
--------------------------------------------------------------------------------
|
| 322 |
|
|
Slack (setup path): -5.680ns (requirement - (data path - clock path skew + uncertainty))
|
| 323 |
|
|
Source: IF_ID_reg/pipeline_register_4 (FF)
|
| 324 |
|
|
Destination: ID_Stage_inst/buff_op_a_18 (LATCH)
|
| 325 |
|
|
Requirement: 5.000ns
|
| 326 |
|
|
Data Path Delay: 8.708ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
|
| 327 |
|
|
Clock Path Skew: -1.972ns (2.137 - 4.109)
|
| 328 |
|
|
Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
|
| 329 |
|
|
Destination Clock: Clk_IBUF rising at 5.000ns
|
| 330 |
|
|
Clock Uncertainty: 0.000ns
|
| 331 |
|
|
|
| 332 |
|
|
Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_18
|
| 333 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 334 |
|
|
Logical Resource(s)
|
| 335 |
|
|
------------------------------------------------- -------------------
|
| 336 |
|
|
SLICE_X38Y58.XQ Tcko 0.592 IF_ID_reg/pipeline_register<4>
|
| 337 |
|
|
IF_ID_reg/pipeline_register_4
|
| 338 |
|
|
SLICE_X36Y63.G3 net (fanout=16) e 0.659 IF_ID_reg/pipeline_register<4>
|
| 339 |
|
|
SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 340 |
|
|
ID_Stage_inst/rrr_adm_SW0
|
| 341 |
|
|
SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
|
| 342 |
|
|
SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 343 |
|
|
ID_Stage_inst/rrr_adm
|
| 344 |
|
|
SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
|
| 345 |
|
|
SLICE_X65Y43.X Tilo 0.704 reg_a<2>
|
| 346 |
|
|
ID_Stage_inst/RF_a<2>1
|
| 347 |
|
|
SLICE_X64Y52.G1 net (fanout=128) e 1.171 reg_a<2>
|
| 348 |
|
|
SLICE_X64Y52.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<18>
|
| 349 |
|
|
Reg_File_inst/mux9_5
|
| 350 |
|
|
Reg_File_inst/mux9_3_f5
|
| 351 |
|
|
SLICE_X64Y52.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux9_3_f5
|
| 352 |
|
|
SLICE_X64Y52.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<18>
|
| 353 |
|
|
Reg_File_inst/mux9_2_f6
|
| 354 |
|
|
ID_Stage_inst/buff_op_a_18
|
| 355 |
|
|
------------------------------------------------- ---------------------------
|
| 356 |
|
|
Total 8.708ns (4.389ns logic, 4.319ns route)
|
| 357 |
|
|
(50.4% logic, 49.6% route)
|
| 358 |
|
|
|
| 359 |
|
|
--------------------------------------------------------------------------------
|
| 360 |
|
|
Slack (setup path): -5.568ns (requirement - (data path - clock path skew + uncertainty))
|
| 361 |
|
|
Source: IF_ID_reg/pipeline_register_2 (FF)
|
| 362 |
|
|
Destination: ID_Stage_inst/buff_op_a_18 (LATCH)
|
| 363 |
|
|
Requirement: 5.000ns
|
| 364 |
|
|
Data Path Delay: 8.596ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
|
| 365 |
|
|
Clock Path Skew: -1.972ns (2.137 - 4.109)
|
| 366 |
|
|
Source Clock: EX_MEM_reg/Clk_RST rising at 0.000ns
|
| 367 |
|
|
Destination Clock: Clk_IBUF rising at 5.000ns
|
| 368 |
|
|
Clock Uncertainty: 0.000ns
|
| 369 |
|
|
|
| 370 |
|
|
Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_18
|
| 371 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 372 |
|
|
Logical Resource(s)
|
| 373 |
|
|
------------------------------------------------- -------------------
|
| 374 |
|
|
SLICE_X36Y62.YQ Tcko 0.652 IF_ID_reg/pipeline_register<1>
|
| 375 |
|
|
IF_ID_reg/pipeline_register_2
|
| 376 |
|
|
SLICE_X36Y63.G1 net (fanout=14) e 0.487 IF_ID_reg/pipeline_register<2>
|
| 377 |
|
|
SLICE_X36Y63.Y Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 378 |
|
|
ID_Stage_inst/rrr_adm_SW0
|
| 379 |
|
|
SLICE_X36Y63.F4 net (fanout=1) e 0.342 ID_Stage_inst/rrr_adm_SW0/O
|
| 380 |
|
|
SLICE_X36Y63.X Tilo 0.759 ID_EX_reg/pipeline_register_77_BRB1
|
| 381 |
|
|
ID_Stage_inst/rrr_adm
|
| 382 |
|
|
SLICE_X65Y43.F2 net (fanout=6) e 2.147 rrr_adm
|
| 383 |
|
|
SLICE_X65Y43.X Tilo 0.704 reg_a<2>
|
| 384 |
|
|
ID_Stage_inst/RF_a<2>1
|
| 385 |
|
|
SLICE_X64Y52.G1 net (fanout=128) e 1.171 reg_a<2>
|
| 386 |
|
|
SLICE_X64Y52.F5 Tif5 1.033 ID_Stage_inst/buff_op_a<18>
|
| 387 |
|
|
Reg_File_inst/mux9_5
|
| 388 |
|
|
Reg_File_inst/mux9_3_f5
|
| 389 |
|
|
SLICE_X64Y52.FXINA net (fanout=1) e 0.000 Reg_File_inst/mux9_3_f5
|
| 390 |
|
|
SLICE_X64Y52.CLK Tfxck 0.542 ID_Stage_inst/buff_op_a<18>
|
| 391 |
|
|
Reg_File_inst/mux9_2_f6
|
| 392 |
|
|
ID_Stage_inst/buff_op_a_18
|
| 393 |
|
|
------------------------------------------------- ---------------------------
|
| 394 |
|
|
Total 8.596ns (4.449ns logic, 4.147ns route)
|
| 395 |
|
|
(51.8% logic, 48.2% route)
|
| 396 |
|
|
|
| 397 |
|
|
--------------------------------------------------------------------------------
|
| 398 |
|
|
|
| 399 |
|
|
Hold Paths: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
|
| 400 |
|
|
--------------------------------------------------------------------------------
|
| 401 |
|
|
|
| 402 |
|
|
Paths for end point ID_EX_reg/pipeline_register_69_BRB0 (SLICE_X36Y43.BY), 1 path
|
| 403 |
|
|
--------------------------------------------------------------------------------
|
| 404 |
|
|
Slack (hold path): -0.566ns (requirement - (clock path skew + uncertainty - data path))
|
| 405 |
|
|
Source: ID_Stage_inst/buff_op_b_7 (LATCH)
|
| 406 |
|
|
Destination: ID_EX_reg/pipeline_register_69_BRB0 (FF)
|
| 407 |
|
|
Requirement: 0.000ns
|
| 408 |
|
|
Data Path Delay: 1.406ns (Levels of Logic = 0)
|
| 409 |
|
|
Clock Path Skew: 1.972ns (4.109 - 2.137)
|
| 410 |
|
|
Source Clock: Clk_IBUF rising at 5.000ns
|
| 411 |
|
|
Destination Clock: EX_MEM_reg/Clk_RST rising at 5.000ns
|
| 412 |
|
|
Clock Uncertainty: 0.000ns
|
| 413 |
|
|
|
| 414 |
|
|
Minimum Data Path: ID_Stage_inst/buff_op_b_7 to ID_EX_reg/pipeline_register_69_BRB0
|
| 415 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 416 |
|
|
Logical Resource(s)
|
| 417 |
|
|
------------------------------------------------- -------------------
|
| 418 |
|
|
SLICE_X39Y44.YQ Tcklo 0.533 ID_Stage_inst/buff_op_b<7>
|
| 419 |
|
|
ID_Stage_inst/buff_op_b_7
|
| 420 |
|
|
SLICE_X36Y43.BY net (fanout=1) e 0.721 ID_Stage_inst/buff_op_b<7>
|
| 421 |
|
|
SLICE_X36Y43.CLK Tckdi (-Th) -0.152 ID_EX_reg/pipeline_register_45_BRB0
|
| 422 |
|
|
ID_EX_reg/pipeline_register_69_BRB0
|
| 423 |
|
|
------------------------------------------------- ---------------------------
|
| 424 |
|
|
Total 1.406ns (0.685ns logic, 0.721ns route)
|
| 425 |
|
|
(48.7% logic, 51.3% route)
|
| 426 |
|
|
|
| 427 |
|
|
--------------------------------------------------------------------------------
|
| 428 |
|
|
|
| 429 |
|
|
Paths for end point ID_EX_reg/pipeline_register_61_BRB0 (SLICE_X37Y56.BX), 1 path
|
| 430 |
|
|
--------------------------------------------------------------------------------
|
| 431 |
|
|
Slack (hold path): -0.371ns (requirement - (clock path skew + uncertainty - data path))
|
| 432 |
|
|
Source: ID_Stage_inst/buff_op_b_15 (LATCH)
|
| 433 |
|
|
Destination: ID_EX_reg/pipeline_register_61_BRB0 (FF)
|
| 434 |
|
|
Requirement: 0.000ns
|
| 435 |
|
|
Data Path Delay: 1.601ns (Levels of Logic = 0)
|
| 436 |
|
|
Clock Path Skew: 1.972ns (4.109 - 2.137)
|
| 437 |
|
|
Source Clock: Clk_IBUF rising at 5.000ns
|
| 438 |
|
|
Destination Clock: EX_MEM_reg/Clk_RST rising at 5.000ns
|
| 439 |
|
|
Clock Uncertainty: 0.000ns
|
| 440 |
|
|
|
| 441 |
|
|
Minimum Data Path: ID_Stage_inst/buff_op_b_15 to ID_EX_reg/pipeline_register_61_BRB0
|
| 442 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 443 |
|
|
Logical Resource(s)
|
| 444 |
|
|
------------------------------------------------- -------------------
|
| 445 |
|
|
SLICE_X43Y58.YQ Tcklo 0.533 ID_Stage_inst/buff_op_b<15>
|
| 446 |
|
|
ID_Stage_inst/buff_op_b_15
|
| 447 |
|
|
SLICE_X37Y56.BX net (fanout=1) e 0.975 ID_Stage_inst/buff_op_b<15>
|
| 448 |
|
|
SLICE_X37Y56.CLK Tckdi (-Th) -0.093 ID_EX_reg/pipeline_register_61_BRB0
|
| 449 |
|
|
ID_EX_reg/pipeline_register_61_BRB0
|
| 450 |
|
|
------------------------------------------------- ---------------------------
|
| 451 |
|
|
Total 1.601ns (0.626ns logic, 0.975ns route)
|
| 452 |
|
|
(39.1% logic, 60.9% route)
|
| 453 |
|
|
|
| 454 |
|
|
--------------------------------------------------------------------------------
|
| 455 |
|
|
|
| 456 |
|
|
Paths for end point ID_EX_reg/pipeline_register_53_BRB0 (SLICE_X34Y45.BX), 1 path
|
| 457 |
|
|
--------------------------------------------------------------------------------
|
| 458 |
|
|
Slack (hold path): -0.360ns (requirement - (clock path skew + uncertainty - data path))
|
| 459 |
|
|
Source: ID_Stage_inst/buff_op_b_23 (LATCH)
|
| 460 |
|
|
Destination: ID_EX_reg/pipeline_register_53_BRB0 (FF)
|
| 461 |
|
|
Requirement: 0.000ns
|
| 462 |
|
|
Data Path Delay: 1.612ns (Levels of Logic = 0)
|
| 463 |
|
|
Clock Path Skew: 1.972ns (4.109 - 2.137)
|
| 464 |
|
|
Source Clock: Clk_IBUF rising at 5.000ns
|
| 465 |
|
|
Destination Clock: EX_MEM_reg/Clk_RST rising at 5.000ns
|
| 466 |
|
|
Clock Uncertainty: 0.000ns
|
| 467 |
|
|
|
| 468 |
|
|
Minimum Data Path: ID_Stage_inst/buff_op_b_23 to ID_EX_reg/pipeline_register_53_BRB0
|
| 469 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 470 |
|
|
Logical Resource(s)
|
| 471 |
|
|
------------------------------------------------- -------------------
|
| 472 |
|
|
SLICE_X35Y52.YQ Tcklo 0.533 ID_Stage_inst/buff_op_b<23>
|
| 473 |
|
|
ID_Stage_inst/buff_op_b_23
|
| 474 |
|
|
SLICE_X34Y45.BX net (fanout=1) e 0.945 ID_Stage_inst/buff_op_b<23>
|
| 475 |
|
|
SLICE_X34Y45.CLK Tckdi (-Th) -0.134 ID_EX_reg/pipeline_register_53_BRB0
|
| 476 |
|
|
ID_EX_reg/pipeline_register_53_BRB0
|
| 477 |
|
|
------------------------------------------------- ---------------------------
|
| 478 |
|
|
Total 1.612ns (0.667ns logic, 0.945ns route)
|
| 479 |
|
|
(41.4% logic, 58.6% route)
|
| 480 |
|
|
|
| 481 |
|
|
--------------------------------------------------------------------------------
|
| 482 |
|
|
|
| 483 |
|
|
Component Switching Limit Checks: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
|
| 484 |
|
|
--------------------------------------------------------------------------------
|
| 485 |
|
|
Slack: 1.808ns (period - (min low pulse limit / (low pulse / period)))
|
| 486 |
|
|
Period: 5.000ns
|
| 487 |
|
|
Low pulse: 2.500ns
|
| 488 |
|
|
Low pulse limit: 1.596ns (Trpw)
|
| 489 |
|
|
Physical resource: exMemoryAddr<0>/SR
|
| 490 |
|
|
Logical resource: EX_MEM_reg/pipeline_register_68/SR
|
| 491 |
|
|
Location pin: V15.SR
|
| 492 |
|
|
Clock network: EX_MEM_reg/zero
|
| 493 |
|
|
--------------------------------------------------------------------------------
|
| 494 |
|
|
Slack: 1.808ns (period - (min high pulse limit / (high pulse / period)))
|
| 495 |
|
|
Period: 5.000ns
|
| 496 |
|
|
High pulse: 2.500ns
|
| 497 |
|
|
High pulse limit: 1.596ns (Trpw)
|
| 498 |
|
|
Physical resource: exMemoryAddr<0>/SR
|
| 499 |
|
|
Logical resource: EX_MEM_reg/pipeline_register_68/SR
|
| 500 |
|
|
Location pin: V15.SR
|
| 501 |
|
|
Clock network: EX_MEM_reg/zero
|
| 502 |
|
|
--------------------------------------------------------------------------------
|
| 503 |
|
|
Slack: 1.808ns (period - (min low pulse limit / (low pulse / period)))
|
| 504 |
|
|
Period: 5.000ns
|
| 505 |
|
|
Low pulse: 2.500ns
|
| 506 |
|
|
Low pulse limit: 1.596ns (Trpw)
|
| 507 |
|
|
Physical resource: exMemoryAddr<1>/SR
|
| 508 |
|
|
Logical resource: EX_MEM_reg/pipeline_register_69/SR
|
| 509 |
|
|
Location pin: U15.SR
|
| 510 |
|
|
Clock network: EX_MEM_reg/zero
|
| 511 |
|
|
--------------------------------------------------------------------------------
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
1 constraint not met.
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
Data Sheet report:
|
| 518 |
|
|
-----------------
|
| 519 |
|
|
All values displayed in nanoseconds (ns)
|
| 520 |
|
|
|
| 521 |
|
|
Clock to Setup on destination clock Clk
|
| 522 |
|
|
---------------+---------+---------+---------+---------+
|
| 523 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 524 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 525 |
|
|
---------------+---------+---------+---------+---------+
|
| 526 |
|
|
Clk | 10.716| | | |
|
| 527 |
|
|
RST | 10.716| | | |
|
| 528 |
|
|
---------------+---------+---------+---------+---------+
|
| 529 |
|
|
|
| 530 |
|
|
Clock to Setup on destination clock RST
|
| 531 |
|
|
---------------+---------+---------+---------+---------+
|
| 532 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 533 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 534 |
|
|
---------------+---------+---------+---------+---------+
|
| 535 |
|
|
Clk | 8.165| | | |
|
| 536 |
|
|
RST | 8.165| | | |
|
| 537 |
|
|
---------------+---------+---------+---------+---------+
|
| 538 |
|
|
|
| 539 |
|
|
|
| 540 |
|
|
Timing summary:
|
| 541 |
|
|
---------------
|
| 542 |
|
|
|
| 543 |
|
|
Timing errors: 1143 Score: 2952759 (Setup/Max: 2949354, Hold: 3405)
|
| 544 |
|
|
|
| 545 |
|
|
Constraints cover 12461 paths, 0 nets, and 3911 connections
|
| 546 |
|
|
|
| 547 |
|
|
Design statistics:
|
| 548 |
|
|
Minimum period: 10.716ns{1} (Maximum frequency: 93.318MHz)
|
| 549 |
|
|
|
| 550 |
|
|
|
| 551 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 552 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 553 |
|
|
|
| 554 |
|
|
Analysis completed Mon Apr 27 19:19:28 2015
|
| 555 |
|
|
--------------------------------------------------------------------------------
|
| 556 |
|
|
|
| 557 |
|
|
Trace Settings:
|
| 558 |
|
|
-------------------------
|
| 559 |
|
|
Trace Settings
|
| 560 |
|
|
|
| 561 |
|
|
Peak Memory Usage: 143 MB
|
| 562 |
|
|
|
| 563 |
|
|
|
| 564 |
|
|
|
