1 |
4 |
azmathmoos |
|
2 |
|
|
|
3 |
|
|
|
4 |
|
|
twDebug*, twFoot?, twClientInfo?)>
|
5 |
|
|
|
6 |
|
|
|
7 |
|
|
|
8 |
|
|
|
9 |
|
|
|
10 |
|
|
|
11 |
|
|
|
12 |
|
|
|
13 |
|
|
|
14 |
|
|
|
15 |
|
|
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
|
22 |
|
|
|
23 |
|
|
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
|
27 |
|
|
|
28 |
|
|
|
29 |
|
|
|
30 |
|
|
|
31 |
|
|
|
32 |
|
|
|
33 |
|
|
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
|
37 |
|
|
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
|
41 |
|
|
|
42 |
|
|
|
43 |
|
|
|
44 |
|
|
|
45 |
|
|
|
46 |
|
|
|
47 |
|
|
|
48 |
|
|
|
49 |
|
|
|
50 |
|
|
NETDELAY |
|
51 |
|
|
NETSKEW |
|
52 |
|
|
PATH |
|
53 |
|
|
DEFPERIOD |
|
54 |
|
|
UNCONSTPATH |
|
55 |
|
|
DEFPATH |
|
56 |
|
|
PATH2SETUP |
|
57 |
|
|
UNCONSTPATH2SETUP |
|
58 |
|
|
PATHCLASS |
|
59 |
|
|
PATHDELAY |
|
60 |
|
|
PERIOD |
|
61 |
|
|
FREQUENCY |
|
62 |
|
|
PATHBLOCK |
|
63 |
|
|
OFFSET |
|
64 |
|
|
OFFSETIN |
|
65 |
|
|
OFFSETINCLOCK |
|
66 |
|
|
UNCONSTOFFSETINCLOCK |
|
67 |
|
|
OFFSETINDELAY |
|
68 |
|
|
OFFSETINMOD |
|
69 |
|
|
OFFSETOUT |
|
70 |
|
|
OFFSETOUTCLOCK |
|
71 |
|
|
UNCONSTOFFSETOUTCLOCK |
|
72 |
|
|
OFFSETOUTDELAY |
|
73 |
|
|
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
74 |
|
|
|
75 |
|
|
twEndPtCnt?,
|
76 |
|
|
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
77 |
|
|
|
78 |
|
|
|
79 |
|
|
|
80 |
|
|
|
81 |
|
|
|
82 |
|
|
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
|
86 |
|
|
|
87 |
|
|
|
88 |
|
|
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
|
99 |
|
|
|
100 |
|
|
|
101 |
|
|
|
102 |
|
|
|
103 |
|
|
|
104 |
|
|
twSimpleMinPath CDATA #IMPLIED>
|
105 |
|
|
|
106 |
|
|
|
107 |
|
|
|
108 |
|
|
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
|
112 |
|
|
|
113 |
|
|
|
114 |
|
|
|
115 |
|
|
|
116 |
|
|
|
117 |
|
|
|
118 |
|
|
|
119 |
|
|
|
120 |
|
|
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
fDCMJit CDATA #IMPLIED
|
124 |
|
|
fPhaseErr CDATA #IMPLIED
|
125 |
|
|
sEqu CDATA #IMPLIED>
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
|
129 |
|
|
|
130 |
|
|
|
131 |
|
|
|
132 |
|
|
|
133 |
|
|
|
134 |
|
|
|
135 |
|
|
|
136 |
|
|
|
137 |
|
|
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
|
141 |
|
|
|
142 |
|
|
|
143 |
|
|
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
|
147 |
|
|
|
148 |
|
|
|
149 |
|
|
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
|
153 |
|
|
|
154 |
|
|
|
155 |
|
|
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
|
162 |
|
|
|
163 |
|
|
|
164 |
|
|
|
165 |
|
|
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
|
169 |
|
|
|
170 |
|
|
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
|
174 |
|
|
|
175 |
|
|
|
176 |
|
|
|
177 |
|
|
|
178 |
|
|
|
179 |
|
|
|
180 |
|
|
|
181 |
|
|
|
182 |
|
|
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
|
195 |
|
|
|
196 |
|
|
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
197 |
|
|
|
198 |
|
|
|
199 |
|
|
|
200 |
|
|
|
201 |
|
|
|
202 |
|
|
|
203 |
|
|
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
|
210 |
|
|
|
211 |
|
|
|
212 |
|
|
|
213 |
|
|
|
214 |
|
|
|
215 |
|
|
|
216 |
|
|
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
|
220 |
|
|
|
221 |
|
|
|
222 |
|
|
|
223 |
|
|
|
224 |
|
|
best CDATA #IMPLIED requested CDATA #IMPLIED
|
225 |
|
|
errors CDATA #IMPLIED
|
226 |
|
|
score CDATA #IMPLIED>
|
227 |
|
|
|
228 |
|
|
|
229 |
|
|
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
|
236 |
|
|
|
237 |
|
|
|
238 |
|
|
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
|
246 |
|
|
|
247 |
|
|
|
248 |
|
|
|
249 |
|
|
|
250 |
|
|
|
251 |
|
|
|
252 |
|
|
|
253 |
|
|
|
254 |
|
|
|
255 |
|
|
|
256 |
|
|
|
257 |
|
|
|
258 |
|
|
|
259 |
|
|
|
260 |
|
|
|
261 |
|
|
|
262 |
|
|
|
263 |
|
|
|
264 |
|
|
|
265 |
|
|
|
266 |
|
|
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
|
270 |
|
|
|
271 |
|
|
|
272 |
|
|
|
273 |
|
|
|
274 |
|
|
|
275 |
|
|
|
276 |
|
|
|
277 |
|
|
|
278 |
|
|
|
279 |
|
|
|
280 |
|
|
|
281 |
|
|
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
|
289 |
|
|
|
290 |
|
|
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
|
300 |
|
|
|
301 |
|
|
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
|
306 |
|
|
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
]>
|
332 |
|
|
Release 14.5 Trace (nt)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
|
333 |
|
|
3 -fastpaths -xml FluidCore_preroute.twx FluidCore_map.ncd -o
|
334 |
|
|
FluidCore_preroute.twr FluidCore.pcf -ucf Test_Bed.ucf -ucf FluidCore.ucf
|
335 |
|
|
|
336 |
|
|
FluidCore_map.ncdFluidCore_map.ncdFluidCore.pcfFluidCore.pcfxc3s500e-4PRODUCTION 1.27 2013-03-263INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;124611128114315018561022210.716Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINA), 43 paths
|
337 |
|
|
-5.716IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_78.7441.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_75SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y40.F1net1281.207reg_a<2>SLICE_X52Y40.F5Tif51.033ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_4Reg_File_inst/mux29_3_f5SLICE_X52Y40.FXINAnet10.000Reg_File_inst/mux29_3_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.3894.3558.744Clk_IBUF50.249.8-5.716IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_78.7441.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_75SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y40.G1net1281.207reg_a<2>SLICE_X52Y40.F5Tif51.033ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_5Reg_File_inst/mux29_3_f5SLICE_X52Y40.FXINAnet10.000Reg_File_inst/mux29_3_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.3894.3558.744Clk_IBUF50.249.8-5.604IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_78.6321.9725.00010.000IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_75SLICE_X36Y62.CLKEX_MEM_reg/Clk_RSTSLICE_X36Y62.YQTcko0.652IF_ID_reg/pipeline_register<1>IF_ID_reg/pipeline_register_2SLICE_X36Y63.G1net140.487IF_ID_reg/pipeline_register<2>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y40.G1net1281.207reg_a<2>SLICE_X52Y40.F5Tif51.033ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_5Reg_File_inst/mux29_3_f5SLICE_X52Y40.FXINAnet10.000Reg_File_inst/mux29_3_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.4494.1838.632Clk_IBUF51.548.5Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINB), 43 paths
|
338 |
|
|
-5.716IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_78.7441.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_75SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y41.F1net1281.207reg_a<2>SLICE_X52Y41.F5Tif51.033Reg_File_inst/mux29_4_f5Reg_File_inst/mux29_51Reg_File_inst/mux29_4_f5SLICE_X52Y40.FXINBnet10.000Reg_File_inst/mux29_4_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.3894.3558.744Clk_IBUF50.249.8-5.716IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_78.7441.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_75SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y41.G1net1281.207reg_a<2>SLICE_X52Y41.F5Tif51.033Reg_File_inst/mux29_4_f5Reg_File_inst/mux29_6Reg_File_inst/mux29_4_f5SLICE_X52Y40.FXINBnet10.000Reg_File_inst/mux29_4_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.3894.3558.744Clk_IBUF50.249.8-5.604IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_78.6321.9725.00010.000IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_75SLICE_X36Y62.CLKEX_MEM_reg/Clk_RSTSLICE_X36Y62.YQTcko0.652IF_ID_reg/pipeline_register<1>IF_ID_reg/pipeline_register_2SLICE_X36Y63.G1net140.487IF_ID_reg/pipeline_register<2>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X52Y41.G1net1281.207reg_a<2>SLICE_X52Y41.F5Tif51.033Reg_File_inst/mux29_4_f5Reg_File_inst/mux29_6Reg_File_inst/mux29_4_f5SLICE_X52Y40.FXINBnet10.000Reg_File_inst/mux29_4_f5SLICE_X52Y40.CLKTfxck0.542ID_Stage_inst/buff_op_a<7>Reg_File_inst/mux29_2_f6ID_Stage_inst/buff_op_a_74.4494.1838.632Clk_IBUF51.548.5Paths for end point ID_Stage_inst/buff_op_a_18 (SLICE_X64Y52.FXINA), 43 paths
|
339 |
|
|
-5.680IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_188.7081.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_185SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X64Y52.F1net1281.171reg_a<2>SLICE_X64Y52.F5Tif51.033ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_4Reg_File_inst/mux9_3_f5SLICE_X64Y52.FXINAnet10.000Reg_File_inst/mux9_3_f5SLICE_X64Y52.CLKTfxck0.542ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_2_f6ID_Stage_inst/buff_op_a_184.3894.3198.708Clk_IBUF50.449.6-5.680IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_188.7081.9725.00010.000IF_ID_reg/pipeline_register_4ID_Stage_inst/buff_op_a_185SLICE_X38Y58.CLKEX_MEM_reg/Clk_RSTSLICE_X38Y58.XQTcko0.592IF_ID_reg/pipeline_register<4>IF_ID_reg/pipeline_register_4SLICE_X36Y63.G3net160.659IF_ID_reg/pipeline_register<4>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X64Y52.G1net1281.171reg_a<2>SLICE_X64Y52.F5Tif51.033ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_5Reg_File_inst/mux9_3_f5SLICE_X64Y52.FXINAnet10.000Reg_File_inst/mux9_3_f5SLICE_X64Y52.CLKTfxck0.542ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_2_f6ID_Stage_inst/buff_op_a_184.3894.3198.708Clk_IBUF50.449.6-5.568IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_188.5961.9725.00010.000IF_ID_reg/pipeline_register_2ID_Stage_inst/buff_op_a_185SLICE_X36Y62.CLKEX_MEM_reg/Clk_RSTSLICE_X36Y62.YQTcko0.652IF_ID_reg/pipeline_register<1>IF_ID_reg/pipeline_register_2SLICE_X36Y63.G1net140.487IF_ID_reg/pipeline_register<2>SLICE_X36Y63.YTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_adm_SW0SLICE_X36Y63.F4net10.342ID_Stage_inst/rrr_adm_SW0/OSLICE_X36Y63.XTilo0.759ID_EX_reg/pipeline_register_77_BRB1ID_Stage_inst/rrr_admSLICE_X65Y43.F2net62.147rrr_admSLICE_X65Y43.XTilo0.704reg_a<2>ID_Stage_inst/RF_a<2>1SLICE_X64Y52.G1net1281.171reg_a<2>SLICE_X64Y52.F5Tif51.033ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_5Reg_File_inst/mux9_3_f5SLICE_X64Y52.FXINAnet10.000Reg_File_inst/mux9_3_f5SLICE_X64Y52.CLKTfxck0.542ID_Stage_inst/buff_op_a<18>Reg_File_inst/mux9_2_f6ID_Stage_inst/buff_op_a_184.4494.1478.596Clk_IBUF51.848.2Hold Paths: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
|
340 |
|
|
Paths for end point ID_EX_reg/pipeline_register_69_BRB0 (SLICE_X36Y43.BY), 1 path
|
341 |
|
|
-0.566ID_Stage_inst/buff_op_b_7ID_EX_reg/pipeline_register_69_BRB01.406-1.9720.0000.000ID_Stage_inst/buff_op_b_7ID_EX_reg/pipeline_register_69_BRB00SLICE_X39Y44.CLKClk_IBUFSLICE_X39Y44.YQTcklo0.533ID_Stage_inst/buff_op_b<7>ID_Stage_inst/buff_op_b_7SLICE_X36Y43.BYnet10.721ID_Stage_inst/buff_op_b<7>SLICE_X36Y43.CLKTckdi0.152ID_EX_reg/pipeline_register_45_BRB0ID_EX_reg/pipeline_register_69_BRB00.6850.7211.406EX_MEM_reg/Clk_RST48.751.3Paths for end point ID_EX_reg/pipeline_register_61_BRB0 (SLICE_X37Y56.BX), 1 path
|
342 |
|
|
-0.371ID_Stage_inst/buff_op_b_15ID_EX_reg/pipeline_register_61_BRB01.601-1.9720.0000.000ID_Stage_inst/buff_op_b_15ID_EX_reg/pipeline_register_61_BRB00SLICE_X43Y58.CLKClk_IBUFSLICE_X43Y58.YQTcklo0.533ID_Stage_inst/buff_op_b<15>ID_Stage_inst/buff_op_b_15SLICE_X37Y56.BXnet10.975ID_Stage_inst/buff_op_b<15>SLICE_X37Y56.CLKTckdi0.093ID_EX_reg/pipeline_register_61_BRB0ID_EX_reg/pipeline_register_61_BRB00.6260.9751.601EX_MEM_reg/Clk_RST39.160.9Paths for end point ID_EX_reg/pipeline_register_53_BRB0 (SLICE_X34Y45.BX), 1 path
|
343 |
|
|
-0.360ID_Stage_inst/buff_op_b_23ID_EX_reg/pipeline_register_53_BRB01.612-1.9720.0000.000ID_Stage_inst/buff_op_b_23ID_EX_reg/pipeline_register_53_BRB00SLICE_X35Y52.CLKClk_IBUFSLICE_X35Y52.YQTcklo0.533ID_Stage_inst/buff_op_b<23>ID_Stage_inst/buff_op_b_23SLICE_X34Y45.BXnet10.945ID_Stage_inst/buff_op_b<23>SLICE_X34Y45.CLKTckdi0.134ID_EX_reg/pipeline_register_53_BRB0ID_EX_reg/pipeline_register_53_BRB00.6670.9451.612EX_MEM_reg/Clk_RST41.458.6Component Switching Limit Checks: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;1ClkClk10.716RST10.716RSTClk8.165RST8.1651143295275929493543405124610391110.71693.318Mon Apr 27 19:19:28 2015 TraceTrace Settings
|
344 |
|
|
|
345 |
|
|
Peak Memory Usage: 143 MB
|
346 |
|
|
|