Subversion Repositories fluid_core_2

Release 14.5 - xst P.58f (nt)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.08 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.08 secs

--> Reading design: Shifter.prj

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) Design Hierarchy Analysis

  4) HDL Analysis

  5) HDL Synthesis

     5.1) HDL Synthesis Report

  6) Advanced HDL Synthesis

     6.1) Advanced HDL Synthesis Report

  7) Low Level Synthesis

  8) Partition Report

  9) Final Report

        9.1) Device utilization summary

        9.2) Partition Resource Summary

        9.3) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "Shifter.prj"

Input Format                       : mixed

Ignore Synthesis Constraint File   : NO

---- Target Parameters

Output File Name                   : "Shifter"

Output Format                      : NGC

Target Device                      : xc3s500e-4-fg320

---- Source Options

Top Module Name                    : Shifter

Automatic FSM Extraction           : YES

FSM Encoding Algorithm             : Auto

Safe Implementation                : No

FSM Style                          : LUT

RAM Extraction                     : Yes

RAM Style                          : Auto

ROM Extraction                     : Yes

Mux Style                          : Auto

Decoder Extraction                 : YES

Priority Encoder Extraction        : Yes

Shift Register Extraction          : YES

Logical Shifter Extraction         : YES

XOR Collapsing                     : YES

ROM Style                          : Auto

Mux Extraction                     : Yes

Resource Sharing                   : YES

Asynchronous To Synchronous        : NO

Multiplier Style                   : LUT

Automatic Register Balancing       : Yes

---- Target Options

Add IO Buffers                     : YES

Global Maximum Fanout              : 100000

Add Generic Clock Buffer(BUFG)     : 24

Register Duplication               : YES

Move First FlipFlop Stage          : YES

Move Last FlipFlop Stage           : YES

Slice Packing                      : YES

Optimize Instantiated Primitives   : NO

Use Clock Enable                   : Yes

Use Synchronous Set                : Yes

Use Synchronous Reset              : Yes

Pack IO Registers into IOBs        : True

Equivalent register Removal        : YES

---- General Options

Optimization Goal                  : Speed

Optimization Effort                : 2

Keep Hierarchy                     : No

Netlist Hierarchy                  : As_Optimized

RTL Output                         : Yes

Global Optimization                : AllClockNets

Read Cores                         : YES

Write Timing Constraints           : NO

Cross Clock Analysis               : NO

Hierarchy Separator                : /

Bus Delimiter                      : <>

Case Specifier                     : Maintain

Slice Utilization Ratio            : 100

BRAM Utilization Ratio             : 100

Verilog 2001                       : YES

Auto BRAM Packing                  : NO

Slice Utilization Ratio Delta      : 5

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling verilog file "Shifter.v" in library work

Compiling verilog include file "Configuration.v"

Module  compiled

No errors in compilation

Analysis of file <"Shifter.prj"> succeeded.

=========================================================================

*                     Design Hierarchy Analysis                         *

=========================================================================

Analyzing hierarchy for module  in library .

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing top module .

Module  is correct for synthesis.

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit .

    Related source file is "Shifter.v".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.

    Found 32-bit shifter logical left for signal  created at line 15.

    Found 32-bit shifter logical right for signal  created at line 16.

    Summary:

        inferred   2 Combinational logic shifter(s).

Unit  synthesized.

=========================================================================

HDL Synthesis Report

Macro Statistics

# Latches                                              : 1

 32-bit latch                                          : 1

# Logic shifters                                       : 2

 32-bit shifter logical left                           : 1

 32-bit shifter logical right                          : 1

=========================================================================

=========================================================================

*                       Advanced HDL Synthesis                          *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report

Macro Statistics

# Latches                                              : 1

 32-bit latch                                          : 1

# Logic shifters                                       : 2

 32-bit shifter logical left                           : 1

 32-bit shifter logical right                          : 1

=========================================================================

=========================================================================

*                         Low Level Synthesis                           *

=========================================================================

Optimizing unit  ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block Shifter, actual ratio is 4.

Final Macro Processing ...

=========================================================================

Final Register Report

Found no macro

=========================================================================

=========================================================================

*                           Partition Report                            *

=========================================================================

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : Shifter.ngr

Top Level Output File Name         : Shifter

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : No

Design Statistics

# IOs                              : 101

Cell Usage :

# BELS                             : 418

#      GND                         : 1

#      LUT2                        : 13

#      LUT3                        : 149

#      LUT4                        : 193

#      MUXCY                       : 7

#      MUXF5                       : 54

#      VCC                         : 1

# FlipFlops/Latches                : 32

#      LD                          : 32

# Clock Buffers                    : 1

#      BUFG                        : 1

# IO Buffers                       : 99

#      IBUF                        : 67

#      OBUF                        : 32

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s500efg320-4

 Number of Slices:                      196  out of   4656     4%

 Number of 4 input LUTs:                355  out of   9312     3%

 Number of IOs:                         101

 Number of bonded IOBs:                  99  out of    232    42%

    IOB Flip Flops:                      32

 Number of GCLKs:                         1  out of     24     4%

---------------------------

Partition Resource Summary:

---------------------------

  No Partitions were found in this design.

---------------------------

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal                       | Clock buffer(FF name)  | Load  |

-----------------------------------+------------------------+-------+

Result_not00021(Result_not00021:O) | BUFG(*)(Result_0)      | 32    |

-----------------------------------+------------------------+-------+

(*) This 1 clock signal(s) are generated by combinatorial logic,

and XST is not able to identify which are the primary clock signals.

Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

   Minimum period: No path found

   Minimum input arrival time before clock: 9.422ns

   Maximum output required time after clock: 4.368ns

   Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'Result_not00021'

  Total number of paths / destination ports: 4086 / 32

-------------------------------------------------------------------------

Offset:              9.422ns (Levels of Logic = 8)

  Source:            OP2<30> (PAD)

  Destination:       Result_5 (LATCH)

  Destination Clock: Result_not00021 falling

  Data Path: OP2<30> to Result_5

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     IBUF:I->O            71   1.218   1.450  OP2_30_IBUF (OP2_30_IBUF)

     LUT3:I0->O            2   0.704   0.526  Sh117_SW0 (N121)

     LUT3:I1->O            5   0.704   0.712  Sh117 (Sh117)

     LUT4:I1->O            1   0.704   0.000  Sh1491 (Sh1491)

     MUXF5:I1->O           2   0.321   0.451  Sh149_f5 (Sh149)

     LUT4:I3->O            1   0.704   0.595  Result_mux0000<5>73 (Result_mux0000<5>73)

     LUT3:I0->O            1   0.704   0.000  Result_mux0000<5>119_F (N257)

     MUXF5:I0->O           1   0.321   0.000  Result_mux0000<5>119 (Result_mux0000<5>)

     LD:D                      0.308          Result_5

    ----------------------------------------

    Total                      9.422ns (5.688ns logic, 3.734ns route)

                                       (60.4% logic, 39.6% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'Result_not00021'

  Total number of paths / destination ports: 32 / 32

-------------------------------------------------------------------------

Offset:              4.368ns (Levels of Logic = 1)

  Source:            Result_31 (LATCH)

  Destination:       Result<0> (PAD)

  Source Clock:      Result_not00021 falling

  Data Path: Result_31 to Result<0>

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     LD:G->Q               1   0.676   0.420  Result_31 (Result_31)

     OBUF:I->O                 3.272          Result_0_OBUF (Result<0>)

    ----------------------------------------

    Total                      4.368ns (3.948ns logic, 0.420ns route)

                                       (90.4% logic, 9.6% route)

=========================================================================

Total REAL time to Xst completion: 7.00 secs

Total CPU time to Xst completion: 7.46 secs

-->

Total memory usage is 203444 kilobytes

Number of errors   :    0 (   0 filtered)

Number of warnings :    2 (   0 filtered)

Number of infos    :    1 (   0 filtered)