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azmathmoos |
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| 7 |
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"FluidCore.v" line 35 Connection to input port 'stall' does not match port size
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| 9 |
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| 10 |
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| 11 |
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"FluidCore.v" line 111 Connection to input port 'wb_reg' does not match port size
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| 12 |
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| 13 |
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| 14 |
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"FluidCore.v" line 175 Connection to input port 'write_uop' does not match port size
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| 15 |
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| 16 |
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| 17 |
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"FluidCore.v" line 225 Connection to input port 'intr_inx' does not match port size
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| 18 |
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| 19 |
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| 20 |
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"FluidCore.v" line 228 Connection to input port 'new_vector' does not match port size
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| 21 |
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| 22 |
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| 23 |
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Contents of array <isr_vectors> may be accessed with an index that does not cover the full array size.
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| 24 |
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| 25 |
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| 26 |
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Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 27 |
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| 28 |
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| 29 |
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HDL ADVISOR - 256 flip-flops were inferred for signal <registers>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
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| 30 |
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| 31 |
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| 32 |
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Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 33 |
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| 34 |
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| 35 |
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Found 32-bit latch for signal <buff_op_a>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 36 |
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| 37 |
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| 38 |
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Found 32-bit latch for signal <buff_op_b>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 39 |
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| 40 |
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| 41 |
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HDL ADVISOR - 338 flip-flops were inferred for signal <uOP_rom>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
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| 42 |
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| 43 |
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| 44 |
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Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 45 |
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| 46 |
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| 47 |
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Found 1-bit latch for signal <ret>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 48 |
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| 49 |
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| 50 |
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Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 51 |
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| 52 |
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| 53 |
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Found 2-bit latch for signal <vctr_inx>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 54 |
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| 55 |
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| 56 |
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Input <prev_Flag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 57 |
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| 58 |
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| 59 |
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Found 32-bit latch for signal <result_buff>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 60 |
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| 61 |
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| 62 |
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Found 1-bit latch for signal <C>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 63 |
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| 64 |
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| 65 |
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Found 1-bit latch for signal <S>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 66 |
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| 67 |
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| 68 |
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Found 1-bit latch for signal <O>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 69 |
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| 70 |
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| 71 |
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Found 1-bit latch for signal <Z>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 72 |
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| 73 |
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| 74 |
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Found 32-bit latch for signal <Result_buff>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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| 75 |
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| 76 |
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| 77 |
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HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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| 78 |
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| 79 |
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| 80 |
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Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 81 |
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| 82 |
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| 83 |
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Signal <OP3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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| 84 |
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| 85 |
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| 86 |
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Signal <t_IF_ID_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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| 87 |
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| 88 |
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| 89 |
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Signal <adm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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| 90 |
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| 91 |
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| 92 |
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HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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| 93 |
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| 94 |
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| 95 |
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FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
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| 96 |
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| 97 |
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| 98 |
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FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
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| 99 |
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| 100 |
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| 101 |
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FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
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| 102 |
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| 103 |
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| 104 |
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FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
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| 105 |
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| 106 |
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| 107 |
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HDL ADVISOR - The RAM <Mram_isr_vectors> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
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| 108 |
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| 109 |
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| 110 |
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Node <PCStack_3_5> of sequential type is unconnected in block <IF_Stage>.
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| 111 |
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| 112 |
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| 113 |
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Node <PCStack_3_4> of sequential type is unconnected in block <IF_Stage>.
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| 114 |
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| 115 |
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| 116 |
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Node <PCStack_3_3> of sequential type is unconnected in block <IF_Stage>.
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| 117 |
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| 118 |
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| 119 |
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Node <PCStack_3_2> of sequential type is unconnected in block <IF_Stage>.
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| 120 |
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| 121 |
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| 122 |
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Node <PCStack_3_1> of sequential type is unconnected in block <IF_Stage>.
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| 123 |
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| 124 |
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| 125 |
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Node <PCStack_3_0> of sequential type is unconnected in block <IF_Stage>.
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| 126 |
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| 127 |
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| 128 |
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FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
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| 129 |
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| 130 |
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| 131 |
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FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
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| 132 |
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| 133 |
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| 134 |
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FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
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| 135 |
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| 136 |
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| 137 |
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FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
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| 138 |
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| 139 |
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| 140 |
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Unit FluidCore: 6 internal tristates are replaced by logic (pull-up yes):
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| 141 |
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| 142 |
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Unit EX_Stage: 36 internal tristates are replaced by logic (pull-up yes):
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| 143 |
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| 144 |
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Unit interrupt_unit: 6 internal tristates are replaced by logic (pull-up yes):
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| 145 |
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| 146 |
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Unit WB_Stage: 37 internal tristates are replaced by logic (pull-up yes):
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| 147 |
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| 148 |
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Unit IF_Stage: 4 internal tristates are replaced by logic (pull-up yes):
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| 149 |
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| 150 |
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Unit Shifter: 32 internal tristates are replaced by logic (pull-up yes):
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| 151 |
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| 152 |
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Unit int_ALU: 32 internal tristates are replaced by logic (pull-up yes):
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| 153 |
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| 154 |
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Node <MEM_WB_reg/pipeline_register_1> of sequential type is unconnected in block <FluidCore>.
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| 155 |
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| 156 |
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| 157 |
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FF/Latch <uOP_Store_inst/uOP_rom_12_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 158 |
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| 159 |
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| 160 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 161 |
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| 162 |
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| 163 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 164 |
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| 165 |
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| 166 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 167 |
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| 168 |
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| 169 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 170 |
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| 171 |
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| 172 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 173 |
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| 174 |
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| 175 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 176 |
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| 177 |
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| 178 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 179 |
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| 180 |
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| 181 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 182 |
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| 183 |
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| 184 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 185 |
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| 186 |
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| 187 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 188 |
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| 189 |
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| 190 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 191 |
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| 192 |
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| 193 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 194 |
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| 195 |
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| 196 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 197 |
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| 198 |
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| 199 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 200 |
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| 201 |
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| 202 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 203 |
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| 204 |
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| 205 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 206 |
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| 207 |
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| 208 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 209 |
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| 210 |
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| 211 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 212 |
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| 213 |
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| 214 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 215 |
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| 216 |
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| 217 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 218 |
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| 219 |
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| 220 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 221 |
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| 222 |
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| 223 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 224 |
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| 225 |
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| 226 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 227 |
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| 228 |
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| 229 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 230 |
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| 231 |
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| 232 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 233 |
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| 234 |
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| 235 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 236 |
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| 237 |
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| 238 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 239 |
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| 240 |
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| 241 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 242 |
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| 243 |
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| 244 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 245 |
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| 246 |
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| 247 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 248 |
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| 249 |
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| 250 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 251 |
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| 252 |
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| 253 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 254 |
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| 255 |
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| 256 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 257 |
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| 258 |
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| 259 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 260 |
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| 261 |
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| 262 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 263 |
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| 264 |
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| 265 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 266 |
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| 267 |
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| 268 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 269 |
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| 270 |
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| 271 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
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| 272 |
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| 273 |
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| 274 |
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Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 275 |
|
|
|
| 276 |
|
|
|
| 277 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 281 |
|
|
|
| 282 |
|
|
|
| 283 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 284 |
|
|
|
| 285 |
|
|
|
| 286 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 287 |
|
|
|
| 288 |
|
|
|
| 289 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 290 |
|
|
|
| 291 |
|
|
|
| 292 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 293 |
|
|
|
| 294 |
|
|
|
| 295 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 296 |
|
|
|
| 297 |
|
|
|
| 298 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 299 |
|
|
|
| 300 |
|
|
|
| 301 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 302 |
|
|
|
| 303 |
|
|
|
| 304 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 305 |
|
|
|
| 306 |
|
|
|
| 307 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 311 |
|
|
|
| 312 |
|
|
|
| 313 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 314 |
|
|
|
| 315 |
|
|
|
| 316 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 350 |
|
|
|
| 351 |
|
|
|
| 352 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 353 |
|
|
|
| 354 |
|
|
|
| 355 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 362 |
|
|
|
| 363 |
|
|
|
| 364 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 374 |
|
|
|
| 375 |
|
|
|
| 376 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 383 |
|
|
|
| 384 |
|
|
|
| 385 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 386 |
|
|
|
| 387 |
|
|
|
| 388 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 407 |
|
|
|
| 408 |
|
|
|
| 409 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 413 |
|
|
|
| 414 |
|
|
|
| 415 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 416 |
|
|
|
| 417 |
|
|
|
| 418 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 422 |
|
|
|
| 423 |
|
|
|
| 424 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 428 |
|
|
|
| 429 |
|
|
|
| 430 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 431 |
|
|
|
| 432 |
|
|
|
| 433 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 443 |
|
|
|
| 444 |
|
|
|
| 445 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 449 |
|
|
|
| 450 |
|
|
|
| 451 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 461 |
|
|
|
| 462 |
|
|
|
| 463 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 473 |
|
|
|
| 474 |
|
|
|
| 475 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_2> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 479 |
|
|
|
| 480 |
|
|
|
| 481 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 485 |
|
|
|
| 486 |
|
|
|
| 487 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 488 |
|
|
|
| 489 |
|
|
|
| 490 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 494 |
|
|
|
| 495 |
|
|
|
| 496 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 500 |
|
|
|
| 501 |
|
|
|
| 502 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 518 |
|
|
|
| 519 |
|
|
|
| 520 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 521 |
|
|
|
| 522 |
|
|
|
| 523 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 524 |
|
|
|
| 525 |
|
|
|
| 526 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 527 |
|
|
|
| 528 |
|
|
|
| 529 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 530 |
|
|
|
| 531 |
|
|
|
| 532 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 533 |
|
|
|
| 534 |
|
|
|
| 535 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 542 |
|
|
|
| 543 |
|
|
|
| 544 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 545 |
|
|
|
| 546 |
|
|
|
| 547 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 548 |
|
|
|
| 549 |
|
|
|
| 550 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 551 |
|
|
|
| 552 |
|
|
|
| 553 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 554 |
|
|
|
| 555 |
|
|
|
| 556 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_4> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 560 |
|
|
|
| 561 |
|
|
|
| 562 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 575 |
|
|
|
| 576 |
|
|
|
| 577 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 578 |
|
|
|
| 579 |
|
|
|
| 580 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 584 |
|
|
|
| 585 |
|
|
|
| 586 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 587 |
|
|
|
| 588 |
|
|
|
| 589 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 590 |
|
|
|
| 591 |
|
|
|
| 592 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 593 |
|
|
|
| 594 |
|
|
|
| 595 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_4> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 599 |
|
|
|
| 600 |
|
|
|
| 601 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 602 |
|
|
|
| 603 |
|
|
|
| 604 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 605 |
|
|
|
| 606 |
|
|
|
| 607 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 611 |
|
|
|
| 612 |
|
|
|
| 613 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 617 |
|
|
|
| 618 |
|
|
|
| 619 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 620 |
|
|
|
| 621 |
|
|
|
| 622 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 623 |
|
|
|
| 624 |
|
|
|
| 625 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 626 |
|
|
|
| 627 |
|
|
|
| 628 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 629 |
|
|
|
| 630 |
|
|
|
| 631 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 632 |
|
|
|
| 633 |
|
|
|
| 634 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 635 |
|
|
|
| 636 |
|
|
|
| 637 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 638 |
|
|
|
| 639 |
|
|
|
| 640 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 641 |
|
|
|
| 642 |
|
|
|
| 643 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 653 |
|
|
|
| 654 |
|
|
|
| 655 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 656 |
|
|
|
| 657 |
|
|
|
| 658 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 659 |
|
|
|
| 660 |
|
|
|
| 661 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 665 |
|
|
|
| 666 |
|
|
|
| 667 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 668 |
|
|
|
| 669 |
|
|
|
| 670 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 671 |
|
|
|
| 672 |
|
|
|
| 673 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 674 |
|
|
|
| 675 |
|
|
|
| 676 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 677 |
|
|
|
| 678 |
|
|
|
| 679 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 680 |
|
|
|
| 681 |
|
|
|
| 682 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 683 |
|
|
|
| 684 |
|
|
|
| 685 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 686 |
|
|
|
| 687 |
|
|
|
| 688 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 689 |
|
|
|
| 690 |
|
|
|
| 691 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 695 |
|
|
|
| 696 |
|
|
|
| 697 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 698 |
|
|
|
| 699 |
|
|
|
| 700 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 701 |
|
|
|
| 702 |
|
|
|
| 703 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 704 |
|
|
|
| 705 |
|
|
|
| 706 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 710 |
|
|
|
| 711 |
|
|
|
| 712 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 713 |
|
|
|
| 714 |
|
|
|
| 715 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 719 |
|
|
|
| 720 |
|
|
|
| 721 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 722 |
|
|
|
| 723 |
|
|
|
| 724 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 740 |
|
|
|
| 741 |
|
|
|
| 742 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 743 |
|
|
|
| 744 |
|
|
|
| 745 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 746 |
|
|
|
| 747 |
|
|
|
| 748 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 749 |
|
|
|
| 750 |
|
|
|
| 751 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 752 |
|
|
|
| 753 |
|
|
|
| 754 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 755 |
|
|
|
| 756 |
|
|
|
| 757 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 761 |
|
|
|
| 762 |
|
|
|
| 763 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 767 |
|
|
|
| 768 |
|
|
|
| 769 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 770 |
|
|
|
| 771 |
|
|
|
| 772 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 773 |
|
|
|
| 774 |
|
|
|
| 775 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 776 |
|
|
|
| 777 |
|
|
|
| 778 |
|
|
Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
The FF/Latch <ID_EX_reg/pipeline_register_118> in Unit <FluidCore> is equivalent to the following FF/Latch, which will be removed : <ID_EX_reg/pipeline_register_115_BRB3>
|
| 782 |
|
|
|
| 783 |
|
|
|
| 784 |
|
|
Due to constant pushing, FF/Latch <ID_EX_reg/pipeline_register_3_BRB0> is unconnected in block <FluidCore>.
|
| 785 |
|
|
|
| 786 |
|
|
|
| 787 |
|
|
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
| 788 |
|
|
|
| 789 |
|
|
|
| 790 |
|
|
|
| 791 |
|
|
|
