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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [iseconfig/] [FC1o6.projectmgr] - Blame information for rev 4

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         /Test_Bed C:|Users|Azmath|Documents|M Tech Project|FC1o6|Test_Bed.v/FC_inst - FluidCore/EX_Stage_inst - EX_Stage
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         /Test_Bed C:|Users|Azmath|Documents|M Tech Project|FC1o6|Test_Bed.v/FC_inst - FluidCore/ID_Stage_inst - ID_Stage
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         Inst_Mem_inst - Inst_Mem (C:/Users/Azmath/Documents/M Tech Project/FC1o6/Inst_Mem.v)
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      Inst_Mem_inst - Inst_Mem (C:/Users/Azmath/Documents/M Tech Project/FC1o6/Inst_Mem.v)
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         Design Utilities/Compile HDL Simulation Libraries
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         work
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      false
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      work
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         Configure Target Device
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         Design Utilities
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         Implement Design/Place & Route/Back-annotate Pin Locations
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         Implement Design/Place & Route/Generate IBIS Model
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         Implement Design/Place & Route/Generate Post-Place & Route Static Timing
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         User Constraints
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         /Test_Bed C:|Users|Azmath|Documents|M Tech Project|FC1o6|Test_Bed.v
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         Design Utilities
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         Simulate Behavioral Model
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      false
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      Simulate Behavioral Model
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   Implementation
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         /reg_file_test C:|Users|Azmath|Documents|M Tech Project|FC1o6|reg_file_test.v
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         /tb_Reg_hist C:|Users|Azmath|Documents|M Tech Project|FC1o6|tb_Reg_hist.v
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         /tb_Test_Bed C:|Users|Azmath|Documents|M Tech Project|FC1o6|tb_Test_Bed.v
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         /tb_staller C:|Users|Azmath|Documents|M Tech Project|FC1o6|tb_staller.v
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         tb_Test_Bed (C:/Users/Azmath/Documents/M Tech Project/FC1o6/tb_Test_Bed.v)
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      tb_Test_Bed (C:/Users/Azmath/Documents/M Tech Project/FC1o6/tb_Test_Bed.v)
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         Design Utilities
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      false
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      Design Utilities
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         Simulate Post-Place & Route Model
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      Simulate Post-Place & Route Model
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