WARNING: For instance FC_inst/MEM_WB_reg/, width 1 of formal port stall is not equal to width 32 of actual constant.
6
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 40. For instance FC_inst/Reg_File_inst/, width 3 of formal port wb_reg is not equal to width 5 of actual signal wb_dst.
7
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 38. For instance FC_inst/uOP_Store_inst/, width 13 of formal port write_uop is not equal to width 32 of actual signal wb_data.
8
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 40. For instance FC_inst/interrupt_unit_inst/, width 3 of formal port intr_inx is not equal to width 5 of actual signal wb_dst.
9
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 38. For instance FC_inst/interrupt_unit_inst/, width 6 of formal port new_vector is not equal to width 32 of actual signal wb_data.
10
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/Test_Bed.v" Line 16. For instance uut/ioPort_inst/, width 4 of formal port fc_data is not equal to width 32 of actual signal MemoryData.
11
Time resolution is 1 ps
12
# onerror resume
13
# wave add /
14
# run 1000 ns
15
Simulator is doing circuit initialization process.
16
Finished circuit initialization process.
17
# restart
18
# restart
19
# run 2.00us
20
Simulator is doing circuit initialization process.
