Subversion Repositories fluid_core_2

`timescale 1ns / 1ps

module tb_Test_Bed;

        // Inputs

        reg Clk;

        reg RST;

        reg [0:3] Interrupt;

        // Instantiate the Unit Under Test (UUT)

        Test_Bed uut (

                .Clk(Clk),

                .RST(RST),

                .Interrupt(Interrupt)

        );

        initial begin

                // Initialize Inputs

                Clk = 0;

                RST = 1;

                Interrupt = 0;

                // Wait 100 ns for global reset to finish

                #60;

        RST = 0;

                // Add stimulus here

        end

        always begin

                #50 Clk = ~Clk;

   end

//      always begin

//              #3400 Interrupt[1] <= 1;

//              #100 Interrupt[1] <= 0;

//      end

endmodule