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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [tb_Test_Bed_stx_beh.prj] - Blame information for rev 4

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Line No. Rev Author Line
1 4 azmathmoos 
verilog isim_temp "int_ALU.v"
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verilog isim_temp "WB_Stage.v"
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verilog isim_temp "uOP_Store.v"
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verilog isim_temp "Staller.v"
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verilog isim_temp "Reg_Hist.v"
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verilog isim_temp "Reg_File.v"
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verilog isim_temp "P_Reg.v"
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verilog isim_temp "MEM_Stage.v"
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verilog isim_temp "interrupt_unit.v"
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verilog isim_temp "IF_Stage.v"
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verilog isim_temp "ID_Stage.v"
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verilog isim_temp "EX_Stage.v"
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verilog isim_temp "ioPort.v"
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verilog isim_temp "Inst_Mem.v"
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verilog isim_temp "FluidCore.v"
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verilog isim_temp "data_mem.v"
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verilog isim_temp "Test_Bed.v"
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verilog isim_temp "tb_Test_Bed.v"
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verilog isim_temp "C:/Xilinx/14.5/ISE_DS/ISE//verilog/src/glbl.v"

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