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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [alunit/] [alunit.v] - Blame information for rev 2

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// ALU for PATLPP
 
module alunit
(
        input                           [15:0]   op0,
        input                           [15:0]   op1,
        input                           [1:0]            op,
        output  reg     [15:0]   res
);
 
always @(op0 or op1 or op)
begin
        case (op)
                0: res <= op0 + op1;
                1: res <= op0 - op1;
                2: res <= op0 & op1;
                3: res <= op0 | op1;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// ALU for PATLPP`
2
3			`module alunit`
4			`(`
5			`input [15:0] op0,`
6			`input [15:0] op1,`
7			`input [1:0] op,`
8			`output reg [15:0] res`
9			`);`
10
11			`always @(op0 or op1 or op)`
12			`begin`
13			`case (op)`
14			`0: res <= op0 + op1;`
15			`1: res <= op0 - op1;`
16			`2: res <= op0 & op1;`
17			`3: res <= op0 \| op1;`
18			`endcase`
19			`end`
20
21			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [alunit/] [alunit.v] - Blame information for rev 2