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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [shiftr/] [gensrl.v] - Blame information for rev 2

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// Generic SRL 16 for use with V4/V5/?V6
 
module gensrl (
        input CLK,
        input D,
        input CE,
        input [3:0] A,
        output Q
);
 
reg [15:0] data;
assign Q = data[A];
 
always @(posedge CLK)
begin
        if (CE == 1'b1)
                data <= {data[14:0], D};
end
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// Generic SRL 16 for use with V4/V5/?V6`
2
3			`module gensrl (`
4			`input CLK,`
5			`input D,`
6			`input CE,`
7			`input [3:0] A,`
8			`output Q`
9			`);`
10
11			`reg [15:0] data;`
12			`assign Q = data[A];`
13
14			`always @(posedge CLK)`
15			`begin`
16			`if (CE == 1'b1)`
17			`data <= {data[14:0], D};`
18			`end`
19
20			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [shiftr/] [gensrl.v] - Blame information for rev 2