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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [shiftr/] [shiftr.v] - Blame information for rev 2

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// Shift Register
// Author: Peter Lieber
//
 
module shiftr
(
        input                           en_in,
        input                           en_out,
        input                           clk,
        input                           rst,
        input                           srst,
 
        input           [7:0]    data_in,
        output  [7:0] data_out
);
 
parameter DEPTH = 16;
parameter DEPTHLOG = 4;
 
reg     [DEPTHLOG-1:0]           size;
reg                                                     empty;
 
always @(posedge clk)
begin
        if (rst || srst)
        begin
                size <= 0;
                empty <= 1;
        end
        else if (empty == 1)
        begin
                if (en_in)
                begin
                        empty <= 0;
                end
        end
        else
        begin
                if (en_in == 1 && en_out == 0)
                begin
                        size <= size + 1;
                end
                else if (en_out == 1 && en_in == 0)
                begin
                        if (size == 0)
                                empty <= 1;
                        else
                                size <= size - 1;
                end
        end
end
 
genvar i;
generate
for (i=0; i<8; i=i+1)
begin : shiftregs
        gensrl shift_reg (
                .Q(data_out[i]),
                .A(size),
                .CE(en_in),
                .CLK(clk),
                .D(data_in[i])
        );
end
endgenerate
 
/*genvar i;
generate
for (i=0; i<8; i=i+1)
begin : shiftregs
        SRLC32E #(
                .INIT(32'h00000000)
        ) shift_reg (
                .Q(data_out[i]),
                .Q31(),
                .A(size),
                .CE(en_in),
                .CLK(clk),
                .D(data_in[i])
        );
end
endgenerate*/
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// Shift Register`
2			`// Author: Peter Lieber`
3			`//`
4
5			`module shiftr`
6			`(`
7			`input en_in,`
8			`input en_out,`
9			`input clk,`
10			`input rst,`
11			`input srst,`
12
13			`input [7:0] data_in,`
14			`output [7:0] data_out`
15			`);`
16
17			`parameter DEPTH = 16;`
18			`parameter DEPTHLOG = 4;`
19
20			`reg [DEPTHLOG-1:0] size;`
21			`reg empty;`
22
23			`always @(posedge clk)`
24			`begin`
25			`if (rst \|\| srst)`
26			`begin`
27			`size <= 0;`
28			`empty <= 1;`
29			`end`
30			`else if (empty == 1)`
31			`begin`
32			`if (en_in)`
33			`begin`
34			`empty <= 0;`
35			`end`
36			`end`
37			`else`
38			`begin`
39			`if (en_in == 1 && en_out == 0)`
40			`begin`
41			`size <= size + 1;`
42			`end`
43			`else if (en_out == 1 && en_in == 0)`
44			`begin`
45			`if (size == 0)`
46			`empty <= 1;`
47			`else`
48			`size <= size - 1;`
49			`end`
50			`end`
51			`end`
52
53			`genvar i;`
54			`generate`
55			`for (i=0; i<8; i=i+1)`
56			`begin : shiftregs`
57			`gensrl shift_reg (`
58			`.Q(data_out[i]),`
59			`.A(size),`
60			`.CE(en_in),`
61			`.CLK(clk),`
62			`.D(data_in[i])`
63			`);`
64			`end`
65			`endgenerate`
66
67			`/*genvar i;`
68			`generate`
69			`for (i=0; i<8; i=i+1)`
70			`begin : shiftregs`
71			`SRLC32E #(`
72			`.INIT(32'h00000000)`
73			`) shift_reg (`
74			`.Q(data_out[i]),`
75			`.Q31(),`
76			`.A(size),`
77			`.CE(en_in),`
78			`.CLK(clk),`
79			`.D(data_in[i])`
80			`);`
81			`end`
82			`endgenerate*/`
83
84			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [PATLPP/] [shiftr/] [shiftr.v] - Blame information for rev 2