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[/] [fpga-cf/] [trunk/] [hdl/] [channelif/] [channelif2.v] - Blame information for rev 2

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1 2 peteralieb 
// FCP Channel Interface
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module channelif2
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(
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        // To ethernet platform
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        input                                   in_sof,
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        input                                   in_eof,
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        input                                   in_src_rdy,
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        output                          in_dst_rdy,
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        input           [7:0]            in_data,
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        input           [3:0]            inport_addr,
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        output                          out_sof,
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        output                          out_eof,
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        output                          out_src_rdy,
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        input                                   out_dst_rdy,
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        output  [7:0]            out_data,
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        input           [3:0]            outport_addr,
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        // Channel 1
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        input                                   ch1_in_sof,
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        input                                   ch1_in_eof,
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        input                                   ch1_in_src_rdy,
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        output                          ch1_in_dst_rdy,
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        input           [7:0]            ch1_in_data,
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        output                          ch1_out_sof,
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        output                          ch1_out_eof,
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        output                          ch1_out_src_rdy,
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        input                                   ch1_out_dst_rdy,
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        output  [7:0]            ch1_out_data,
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        output                          ch1_wen,
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        output                          ch1_ren,
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        // Channel 2
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        input                                   ch2_in_sof,
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        input                                   ch2_in_eof,
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        input                                   ch2_in_src_rdy,
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        output                          ch2_in_dst_rdy,
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        input           [7:0]            ch2_in_data,
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        output                          ch2_out_sof,
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        output                          ch2_out_eof,
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        output                          ch2_out_src_rdy,
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        input                                   ch2_out_dst_rdy,
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        output  [7:0]            ch2_out_data,
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        output                          ch2_wen,
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        output                          ch2_ren,
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        // To user logic
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        output  [15:0]   wenables,
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        output  [15:0]   renables
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);
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//                                          Channel-Enable Decoders
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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reg [15:0]               wenables_i;
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reg [15:0]               renables_i;
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always @(inport_addr)
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begin
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        case (inport_addr)
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                4'h0 : wenables_i = 16'b0000000000000001;
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                4'h1 : wenables_i = 16'b0000000000000010;
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                4'h2 : wenables_i = 16'b0000000000000100;
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                4'h3 : wenables_i = 16'b0000000000001000;
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                4'h4 : wenables_i = 16'b0000000000010000;
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                4'h5 : wenables_i = 16'b0000000000100000;
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                4'h6 : wenables_i = 16'b0000000001000000;
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                4'h7 : wenables_i = 16'b0000000010000000;
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                4'h8 : wenables_i = 16'b0000000100000000;
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                4'h9 : wenables_i = 16'b0000001000000000;
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                4'hA : wenables_i = 16'b0000010000000000;
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                4'hB : wenables_i = 16'b0000100000000000;
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                4'hC : wenables_i = 16'b0001000000000000;
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                4'hD : wenables_i = 16'b0010000000000000;
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                4'hE : wenables_i = 16'b0100000000000000;
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                4'hF : wenables_i = 16'b1000000000000000;
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                default: wenables_i = 16'b0000000000000000;
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        endcase
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end
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always @(outport_addr)
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begin
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        case (outport_addr)
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                4'h0 : renables_i = 16'b0000000000000001;
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                4'h1 : renables_i = 16'b0000000000000010;
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                4'h2 : renables_i = 16'b0000000000000100;
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                4'h3 : renables_i = 16'b0000000000001000;
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                4'h4 : renables_i = 16'b0000000000010000;
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                4'h5 : renables_i = 16'b0000000000100000;
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                4'h6 : renables_i = 16'b0000000001000000;
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                4'h7 : renables_i = 16'b0000000010000000;
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                4'h8 : renables_i = 16'b0000000100000000;
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                4'h9 : renables_i = 16'b0000001000000000;
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                4'hA : renables_i = 16'b0000010000000000;
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                4'hB : renables_i = 16'b0000100000000000;
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                4'hC : renables_i = 16'b0001000000000000;
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                4'hD : renables_i = 16'b0010000000000000;
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                4'hE : renables_i = 16'b0100000000000000;
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                4'hF : renables_i = 16'b1000000000000000;
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                default: renables_i = 16'b0000000000000000;
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        endcase
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end
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assign wenables = wenables_i;
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assign renables = renables_i;
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//                                          Multiplexers
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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assign in_dst_rdy = (ch1_wen & ch1_out_dst_rdy) | (ch2_wen & ch2_out_dst_rdy);
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assign out_sof = (ch1_ren & ch1_in_sof) | (ch2_ren & ch2_in_sof);
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assign out_eof = (ch1_ren & ch1_in_eof) | (ch2_ren & ch2_in_eof);
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assign out_src_rdy = (ch1_ren & ch1_in_src_rdy) | (ch2_ren & ch2_in_src_rdy);
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assign out_data = ({8{ch1_ren}} & ch1_in_data) | ({8{ch2_ren}} & ch2_in_data);
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//                                          Passthroughs
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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assign ch1_in_dst_rdy = out_dst_rdy;
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assign ch1_out_src_rdy = in_src_rdy;
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assign ch1_out_sof = in_sof;
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assign ch1_out_eof = in_eof;
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assign ch1_out_data = in_data;
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assign ch1_wen = wenables_i[1];
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assign ch1_ren = renables_i[1];
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assign ch2_in_dst_rdy = out_dst_rdy;
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assign ch2_out_src_rdy = in_src_rdy;
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assign ch2_out_sof = in_sof;
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assign ch2_out_eof = in_eof;
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assign ch2_out_data = in_data;
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assign ch2_wen = wenables_i[2];
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assign ch2_ren = renables_i[2];
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endmodule

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