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[/] [fpga-cf/] [trunk/] [hdl/] [md5/] [md5.v] - Blame information for rev 2

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1 2 peteralieb
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MD5 implementation                                          ////
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////                                                              ////
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////  This file is part of the SystemC MD5                        ////
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////                                                              ////
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////  Description:                                                ////
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////  MD5 implementation                                          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - done                                                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Javier Castillo, jcastilo@opencores.org               ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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47
`timescale 1ns/100ps
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49
 
50
 
51
module md5(clk,reset,load_i,ready_o,newtext_i,data_i,data_o);
52
 
53
input clk;
54
input reset;
55
input load_i;
56
output ready_o;
57
input newtext_i;
58
 
59
 
60
//Input must be padded and in little endian mode
61
input [127:0] data_i;
62
output [127:0] data_o;
63
 
64
reg ready_o, next_ready_o;
65
reg [127:0] data_o, next_data_o;
66
 
67
reg [5:0] round64, next_round64;
68
reg [43:0] t;
69
 
70
 
71
reg [31:0] ar,br,cr,dr,func_out, next_ar,next_br, next_cr, next_dr;
72
reg [31:0] A,B,C,D,next_A,next_B, next_C, next_D;
73
reg [511:0] message, next_message;
74
reg [2:0] round,next_round;
75
reg next_generate_hash,generate_hash;
76
reg hash_generated;
77
 
78
reg [2:0] next_getdata_state, getdata_state;
79
 
80
//rom process
81
always @(round64)
82
begin
83
 
84
   case(round64)
85
         0: t = 44'hD76AA478070;
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         1: t = 44'hE8C7B7560C1;
87
         2: t = 44'h242070DB112;
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         3: t = 44'hC1BDCEEE163;
89
         4: t = 44'hF57C0FAF074;
90
         5: t = 44'h4787C62A0C5;
91
         6: t = 44'hA8304613116;
92
         7: t = 44'hFD469501167;
93
         8: t = 44'h698098D8078;
94
         9: t = 44'h8B44F7AF0C9;
95
         10: t = 44'hFFFF5BB111A;
96
         11: t = 44'h895CD7BE16B;
97
         12: t = 44'h6B90112207C;
98
         13: t = 44'hFD9871930CD;
99
         14: t = 44'hA679438E11E;
100
         15: t = 44'h49B4082116F;
101
 
102
         16: t = 44'hf61e2562051;
103
         17: t = 44'hc040b340096;
104
         18: t = 44'h265e5a510EB;
105
         19: t = 44'he9b6c7aa140;
106
         20: t = 44'hd62f105d055;
107
         21: t = 44'h0244145309A;
108
         22: t = 44'hd8a1e6810EF;
109
         23: t = 44'he7d3fbc8144;
110
         24: t = 44'h21e1cde6059;
111
         25: t = 44'hc33707d609E;
112
         26: t = 44'hf4d50d870E3;
113
         27: t = 44'h455a14ed148;
114
         28: t = 44'ha9e3e90505D;
115
         29: t = 44'hfcefa3f8092;
116
         30: t = 44'h676f02d90E7;
117
         31: t = 44'h8d2a4c8a14C;
118
 
119
         32: t = 44'hfffa3942045;
120
         33: t = 44'h8771f6810B8;
121
         34: t = 44'h6d9d612210B;
122
         35: t = 44'hfde5380c17E;
123
         36: t = 44'ha4beea44041;
124
         37: t = 44'h4bdecfa90B4;
125
         38: t = 44'hf6bb4b60107;
126
         39: t = 44'hbebfbc7017A;
127
         40: t = 44'h289b7ec604D;
128
         41: t = 44'heaa127fa0B0;
129
         42: t = 44'hd4ef3085103;
130
         43: t = 44'h04881d05176;
131
         44: t = 44'hd9d4d039049;
132
         45: t = 44'he6db99e50BC;
133
         46: t = 44'h1fa27cf810F;
134
         47: t = 44'hc4ac5665172;
135
 
136
         48: t = 44'hf4292244060;
137
         49: t = 44'h432aff970A7;
138
         50: t = 44'hab9423a70FE;
139
         51: t = 44'hfc93a039155;
140
         52: t = 44'h655b59c306C;
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         53: t = 44'h8f0ccc920A3;
142
         54: t = 44'hffeff47d0FA;
143
         55: t = 44'h85845dd1151;
144
         56: t = 44'h6fa87e4f068;
145
         57: t = 44'hfe2ce6e00AF;
146
         58: t = 44'ha30143140F6;
147
         59: t = 44'h4e0811a115D;
148
         60: t = 44'hf7537e82064;
149
         61: t = 44'hbd3af2350AB;
150
         62: t = 44'h2ad7d2bb0F2;
151
         63: t = 44'heb86d391159;
152
    endcase
153
end
154
//end process rom
155
 
156
 
157
//funcs process
158
 
159
 
160
reg [31:0] aux31,fr_var,tr_var,rotate1,rotate2;
161
reg [7:0] s_var;
162
reg [3:0] nblock;
163
reg [31:0] message_var[15:0];
164
 
165
always @(t or ar or br or cr or dr or round or message or func_out or message_var[0] or message_var[1] or message_var[2] or message_var[3]
166
         or message_var[4] or message_var[5] or message_var[6] or message_var[7] or message_var[8] or message_var[9] or message_var[10]
167
         or message_var[11] or message_var[12] or message_var[13] or message_var[14] or message_var[15])
168
begin
169
 
170
   message_var[0]=message[511:480];
171
   message_var[1]=message[479:448];
172
   message_var[2]=message[447:416];
173
   message_var[3]=message[415:384];
174
   message_var[4]=message[383:352];
175
   message_var[5]=message[351:320];
176
   message_var[6]=message[319:288];
177
   message_var[7]=message[287:256];
178
   message_var[8]=message[255:224];
179
   message_var[9]=message[223:192];
180
   message_var[10]=message[191:160];
181
   message_var[11]=message[159:128];
182
   message_var[12]=message[127:96];
183
   message_var[13]=message[95:64];
184
   message_var[14]=message[63:32];
185
   message_var[15]=message[31:0];
186
 
187
   fr_var=0;
188
 
189
   case(round)
190
      0: fr_var=((br&cr)|(~br&dr));
191
      1: fr_var=((br&dr)|(cr& (~dr)));
192
      2: fr_var=(br^cr^dr);
193
      3: fr_var=(cr^(br|~dr));
194
   endcase
195
 
196
 
197
   tr_var=t[43:12];
198
   s_var=t[11:4];
199
   nblock=t[3:0];
200
 
201
   aux31=(ar+fr_var+message_var[nblock]+tr_var);
202
 
203
   rotate1=aux31 << s_var;
204
   rotate2=aux31 >> (32-s_var);
205
   func_out=br+(rotate1 | rotate2);
206
 
207
end
208
//end process funcs
209
 
210
 
211
//process round64FSM
212
always @(newtext_i or round or round64 or ar or br or cr or dr or generate_hash or func_out or getdata_state or A or B or C or D)
213
begin
214
 
215
      next_ar=ar;
216
      next_br=br;
217
      next_cr=cr;
218
      next_dr=dr;
219
      next_round64=round64;
220
      next_round=round;
221
      hash_generated=0;
222
 
223
      if(generate_hash!=0)
224
      begin
225
        next_ar=dr;
226
        next_br=func_out;
227
        next_cr=br;
228
        next_dr=cr;
229
      end
230
 
231
      case(round64)
232
        0:
233
        begin
234
          next_round=0;
235
          if(generate_hash) next_round64=1;
236
        end
237
 
238
        15,31,47:
239
        begin
240
          next_round=round+1;
241
          next_round64=round64+1;
242
        end
243
 
244
        63:
245
        begin
246
          next_round=0;
247
          next_round64=0;
248
          hash_generated=1;
249
        end
250
 
251
        default: next_round64=round64+1;
252
 
253
    endcase
254
 
255
 
256
    if(newtext_i)
257
    begin
258
      next_ar=32'h67452301;
259
      next_br=32'hEFCDAB89;
260
      next_cr=32'h98BADCFE;
261
      next_dr=32'h10325476;
262
      next_round=0;
263
      next_round64=0;
264
    end
265
 
266
    if(!getdata_state)
267
    begin
268
      next_ar=A;
269
      next_br=B;
270
      next_cr=C;
271
      next_dr=D;
272
    end
273
 
274
end
275
//end round64FSM process
276
 
277
//regsignal process
278
always @(posedge clk or negedge reset)
279
begin
280
 
281
   if(!reset)
282
   begin
283
     ready_o=0;
284
     data_o=0;
285
     message=0;
286
 
287
     ar=32'h67452301;
288
     br=32'hEFCDAB89;
289
     cr=32'h98BADCFE;
290
     dr=32'h10325476;
291
 
292
     getdata_state=0;
293
     generate_hash=0;
294
 
295
     round=0;
296
     round64=0;
297
     A=32'h67452301;
298
     B=32'hEFCDAB89;
299
     C=32'h98BADCFE;
300
     D=32'h10325476;
301
 
302
   end
303
   else
304
   begin
305
     ready_o=next_ready_o;
306
     data_o=next_data_o;
307
     message=next_message;
308
 
309
     ar=next_ar;
310
     br=next_br;
311
     cr=next_cr;
312
     dr=next_dr;
313
 
314
     A=next_A;
315
     B=next_B;
316
     C=next_C;
317
     D=next_D;
318
 
319
     generate_hash=next_generate_hash;
320
     getdata_state=next_getdata_state;
321
 
322
     round=next_round;
323
     round64=next_round64;
324
   end
325
end
326
//end regsignals process
327
 
328
 
329
//getdata process
330
 
331
reg [127:0] data_o_var;
332
reg [511:0] aux;
333
wire [31:0] A_t,B_t,C_t,D_t;
334
 
335
assign A_t=dr+A;
336
assign B_t=func_out+B;
337
assign C_t=br+C;
338
assign D_t=cr+D;
339
 
340
always @(newtext_i or A_t or B_t or C_t or D_t or data_i or load_i or getdata_state or generate_hash or hash_generated or message or func_out or A or B or C or D or ar or br or cr or dr)
341
begin
342
 
343
   next_A=A;
344
   next_B=B;
345
   next_C=C;
346
   next_D=D;
347
 
348
   next_generate_hash=generate_hash;
349
   next_ready_o=0;
350
   next_getdata_state=getdata_state;
351
 
352
   next_data_o=0;
353
   aux=message;
354
   next_message=message;
355
 
356
   if(newtext_i)
357
   begin
358
     next_A=32'h67452301;
359
     next_B=32'hEFCDAB89;
360
     next_C=32'h98BADCFE;
361
     next_D=32'h10325476;
362
     next_getdata_state=0;
363
   end
364
 
365
   case(getdata_state)
366
 
367
 
368
      begin
369
        if(load_i)
370
        begin
371
          aux[511:384]=data_i;
372
          next_message=aux;
373
          next_getdata_state=1;
374
        end
375
      end
376
 
377
      1 :
378
      begin
379
       if(load_i)
380
       begin
381
         aux[383:256]=data_i;
382
         next_message=aux;
383
         next_getdata_state=2;
384
       end
385
      end
386
 
387
      2 :
388
      begin
389
       if(load_i)
390
       begin
391
         aux[255:128]=data_i;
392
         next_message=aux;
393
         next_getdata_state=3;
394
       end
395
      end
396
 
397
      3 :
398
      begin
399
        if(load_i)
400
        begin
401
          aux[127:0]=data_i;
402
          next_message=aux;
403
          next_getdata_state=4;
404
          next_generate_hash=1;
405
        end
406
      end
407
 
408
          4 :
409
      begin
410
 
411
            next_generate_hash=1;
412
 
413
        data_o_var[127:96]=A_t;
414
        data_o_var[95:64]=B_t;
415
        data_o_var[63:32]=C_t;
416
        data_o_var[31:0]=D_t;
417
        next_data_o=data_o_var;
418
 
419
        if(hash_generated)
420
        begin
421
                  next_A=A_t;
422
          next_B=B_t;
423
          next_C=C_t;
424
          next_D=D_t;
425
          next_getdata_state=0;
426
          next_ready_o=1;
427
          next_generate_hash=0;
428
        end
429
      end
430
   endcase
431
end
432
//end getdata process
433
 
434
 
435
endmodule

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