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[/] [fpga-cf/] [trunk/] [hdl/] [md5/] [port_md5_tb.v] - Blame information for rev 2

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// Port MD5 Testbench
 
`timescale 1ns / 100ps
 
module port_md5_tb;
 
// Input stimulus:
reg     clk;
reg     rst;
reg     en;
reg     [7:0]    in_data;
reg     in_sof;
reg     in_eof;
reg     in_src_rdy;
reg     out_dst_rdy;
 
// Output connections:
wire    [7:0]    out_data;
wire    out_sof;
wire    out_eof;
wire    out_src_rdy;
wire    in_dst_rdy;
 
 
//Instantiate the DUT (device under test):
port_md5 DUT (
        // Inputs:
        .clk ( clk ),
        .rst ( rst ),
        .wen ( en ),
        .ren ( en ),
        .in_data ( in_data ),   // Input
        .in_sof ( in_sof ),     // Input
        .in_eof ( in_eof ),     // Input
        .in_src_rdy ( in_src_rdy ),     // Input
        .out_dst_rdy ( out_dst_rdy ),   // Output
 
        // Outputs:
        .out_data ( out_data ), // Output
        .out_sof ( out_sof ),   // Output
        .out_eof ( out_eof ),   // Output
        .out_src_rdy ( out_src_rdy ),   // Output
        .in_dst_rdy ( in_dst_rdy )      // Input
);
 
        // Specify input stimulus:
 
initial begin
 
        // Initial values for input stimulus:
        clk = 1;
        rst = 1'b0;
        en = 1'b0;
        in_data = 8'b0;
        in_sof = 1'b0;
        in_eof = 1'b0;
        in_src_rdy = 1'b1;
        out_dst_rdy = 1'b0;
 
        //
        //--- INSERT YOUR INPUT STIMULUS DESCRIPTION HERE ---
        //
 
        @(posedge clk);
        rst = 1;
        @(posedge clk);
        rst = 0;
        @(posedge clk);
        en = 0;
        in_sof = 1;
        in_src_rdy = 1;
        in_data = 8'h5A;
        #1 en = 1;
        wait (in_dst_rdy);
        @(posedge clk);
        in_sof = 0;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
 
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
 
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
 
        in_data = 8'h80;
        @(posedge clk);
        in_data = 8'h00;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        in_data = 8'h80;
        @(posedge clk);
        in_data = 8'h01;
        @(posedge clk);
        in_data = 8'h00;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        in_eof = 1;
        @(posedge clk);
        in_eof = 0;
 
        wait (out_src_rdy);
        out_dst_rdy = 1;
        $stop;
 
end
 
        // Template for master clock. Uncomment and modify signal name as needed.
        // Remember to set the initial value of 'Clock' in the 'initial' block above.
always #5 clk = ~clk;
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// Port MD5 Testbench`
2
3			`timescale 1ns / 100ps
4
5			`module port_md5_tb;`
6
7			`// Input stimulus:`
8			`reg clk;`
9			`reg rst;`
10			`reg en;`
11			`reg [7:0] in_data;`
12			`reg in_sof;`
13			`reg in_eof;`
14			`reg in_src_rdy;`
15			`reg out_dst_rdy;`
16
17			`// Output connections:`
18			`wire [7:0] out_data;`
19			`wire out_sof;`
20			`wire out_eof;`
21			`wire out_src_rdy;`
22			`wire in_dst_rdy;`
23
24
25			`//Instantiate the DUT (device under test):`
26			`port_md5 DUT (`
27			`// Inputs:`
28			`.clk ( clk ),`
29			`.rst ( rst ),`
30			`.wen ( en ),`
31			`.ren ( en ),`
32			`.in_data ( in_data ), // Input`
33			`.in_sof ( in_sof ), // Input`
34			`.in_eof ( in_eof ), // Input`
35			`.in_src_rdy ( in_src_rdy ), // Input`
36			`.out_dst_rdy ( out_dst_rdy ), // Output`
37
38			`// Outputs:`
39			`.out_data ( out_data ), // Output`
40			`.out_sof ( out_sof ), // Output`
41			`.out_eof ( out_eof ), // Output`
42			`.out_src_rdy ( out_src_rdy ), // Output`
43			`.in_dst_rdy ( in_dst_rdy ) // Input`
44			`);`
45
46			`// Specify input stimulus:`
47
48			`initial begin`
49
50			`// Initial values for input stimulus:`
51			`clk = 1;`
52			`rst = 1'b0;`
53			`en = 1'b0;`
54			`in_data = 8'b0;`
55			`in_sof = 1'b0;`
56			`in_eof = 1'b0;`
57			`in_src_rdy = 1'b1;`
58			`out_dst_rdy = 1'b0;`
59
60			`//`
61			`//--- INSERT YOUR INPUT STIMULUS DESCRIPTION HERE ---`
62			`//`
63
64			`@(posedge clk);`
65			`rst = 1;`
66			`@(posedge clk);`
67			`rst = 0;`
68			`@(posedge clk);`
69			`en = 0;`
70			`in_sof = 1;`
71			`in_src_rdy = 1;`
72			`in_data = 8'h5A;`
73			`#1 en = 1;`
74			`wait (in_dst_rdy);`
75			`@(posedge clk);`
76			`in_sof = 0;`
77			`@(posedge clk);`
78			`@(posedge clk);`
79			`@(posedge clk);`
80			`@(posedge clk);`
81			`@(posedge clk);`
82			`@(posedge clk);`
83			`@(posedge clk);`
84			`@(posedge clk);`
85			`@(posedge clk);`
86			`@(posedge clk);`
87			`@(posedge clk);`
88			`@(posedge clk);`
89			`@(posedge clk);`
90			`@(posedge clk);`
91			`@(posedge clk);`
92			`@(posedge clk);`
93			`@(posedge clk);`
94
95			`@(posedge clk);`
96			`@(posedge clk);`
97			`@(posedge clk);`
98			`@(posedge clk);`
99			`@(posedge clk);`
100			`@(posedge clk);`
101			`@(posedge clk);`
102			`@(posedge clk);`
103			`@(posedge clk);`
104			`@(posedge clk);`
105			`@(posedge clk);`
106			`@(posedge clk);`
107			`@(posedge clk);`
108			`@(posedge clk);`
109			`@(posedge clk);`
110			`@(posedge clk);`
111			`@(posedge clk);`
112			`@(posedge clk);`
113
114			`@(posedge clk);`
115			`@(posedge clk);`
116			`@(posedge clk);`
117			`@(posedge clk);`
118			`@(posedge clk);`
119			`@(posedge clk);`
120			`@(posedge clk);`
121			`@(posedge clk);`
122			`@(posedge clk);`
123			`@(posedge clk);`
124			`@(posedge clk);`
125			`@(posedge clk);`
126			`@(posedge clk);`
127			`@(posedge clk);`
128			`@(posedge clk);`
129			`@(posedge clk);`
130			`@(posedge clk);`
131			`@(posedge clk);`
132
133			`in_data = 8'h80;`
134			`@(posedge clk);`
135			`in_data = 8'h00;`
136			`@(posedge clk);`
137			`@(posedge clk);`
138			`@(posedge clk);`
139			`@(posedge clk);`
140			`@(posedge clk);`
141			`@(posedge clk);`
142			`@(posedge clk);`
143			`in_data = 8'h80;`
144			`@(posedge clk);`
145			`in_data = 8'h01;`
146			`@(posedge clk);`
147			`in_data = 8'h00;`
148			`@(posedge clk);`
149			`@(posedge clk);`
150			`@(posedge clk);`
151			`@(posedge clk);`
152			`@(posedge clk);`
153			`in_eof = 1;`
154			`@(posedge clk);`
155			`in_eof = 0;`
156
157			`wait (out_src_rdy);`
158			`out_dst_rdy = 1;`
159			`$stop;`
160
161			`end`
162
163			`// Template for master clock. Uncomment and modify signal name as needed.`
164			`// Remember to set the initial value of 'Clock' in the 'initial' block above.`
165			`always #5 clk = ~clk;`
166
167			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [md5/] [port_md5_tb.v] - Blame information for rev 2