URL https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk

Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [hdl/] [port_fifo/] [sim.do] - Blame information for rev 8

Details | Compare with Previous | View Log


quit -sim
 
vlib work
 
vlog C:/Xilinx/11.1/ISE/verilog/src/glbl.v
vlog ./port_fifo.v
vlog ./port_fifo_tb.v
 
vsim -L unisims_ver -L unimacro_ver -voptargs=+acc port_fifo_tb glbl
 
add wave -hex /port_fifo_tb/*
add wave -hex /port_fifo_tb/DUT/*
 
run 400ns
 
 

Line No.	Rev	Author	Line
1	8	peteralieb	`quit -sim`
2
3			`vlib work`
4
5			`vlog C:/Xilinx/11.1/ISE/verilog/src/glbl.v`
6			`vlog ./port_fifo.v`
7			`vlog ./port_fifo_tb.v`
8
9			`vsim -L unisims_ver -L unimacro_ver -voptargs=+acc port_fifo_tb glbl`
10
11			`add wave -hex /port_fifo_tb/*`
12			`add wave -hex /port_fifo_tb/DUT/*`
13
14			`run 400ns`
15
16

Browse

Tools

Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [hdl/] [port_fifo/] [sim.do] - Blame information for rev 8