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[/] [fpga-cf/] [trunk/] [hdl/] [port_register/] [port_register.v] - Blame information for rev 2

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// 32 bit Port Register
 
`timescale 1ns/100ps
 
module port_register(
        input                                   clk,
        input                                   rst,
        input                                   wen,
        input                                   ren,
        input                                   in_sof,
        input                                   in_eof,
        input                                   in_src_rdy,
        output                          in_dst_rdy,
        input           [7:0]            in_data,
 
        output  reg             out_sof,
        output  reg             out_eof,
        input                                   out_dst_rdy,
        output                          out_src_rdy,
        output  reg [7:0]                out_data
);
 
 
reg reg_enable;
reg shift_en;
reg [1:0] rstate;
reg [1:0] nextrstate;
reg [23:0] shift_reg;
reg [31:0] word_reg;
reg [1:0] wstate;
reg [1:0] nextwstate;
 
assign in_dst_rdy = 1;
assign out_src_rdy = 1;
 
always@(wstate, wen, in_sof, in_src_rdy)
begin
        reg_enable = 0;
        shift_en = 0;
        nextwstate = wstate;
        case (wstate)
                0: // waiting byte 0
                begin
                        if (wen & in_sof & in_src_rdy)
                        begin
                                shift_en = 1;
                                nextwstate = 1;
                        end
                end
                1: // waiting byte 1 
                begin
                        if (wen & in_src_rdy)
                        begin
                                shift_en = 1;
                                nextwstate = 2;
                        end
                end
                2: // waiting byte 2
                begin
                        if (wen & in_src_rdy)
                        begin
                                shift_en = 1;
                                nextwstate = 3;
                        end
                end
                3: // waiting byte 3
                begin
                        if (wen & in_src_rdy)
                        begin
                                reg_enable = 1;
                                nextwstate = 0;
                        end
                end
        endcase
end
 
always@(posedge clk or posedge rst)
begin
        if (rst)
                wstate <= 0;
        else
                wstate <= nextwstate;
end
 
// shift register and word register
always@(posedge clk or posedge rst)
begin
        if (rst)
        begin
                shift_reg <= 0;
                word_reg <= 0;
        end
        else
        begin
                if (shift_en)
                begin
                        shift_reg <= {in_data, shift_reg[23:8]};
                end
                if (reg_enable)
                begin
                        word_reg <= {in_data, shift_reg};
                end
        end
end
 
always@(rstate or ren or out_dst_rdy)
begin
        out_data = 0;
        out_eof = 0;
        out_sof = 0;
        nextrstate = rstate;
        case (rstate)
                0: // waiting for read
                begin
                        out_data = word_reg[7:0];
                        out_sof = 1;
                        if (ren & out_dst_rdy)
                        begin
                                nextrstate = 1;
                        end
                end
                1: // waiting for read 2
                begin
                        out_data = word_reg[15:8];
                        if (ren & out_dst_rdy)
                        begin
                                nextrstate = 2;
                        end
                end
                2: // waiting for read 3
                begin
                        out_data = word_reg[23:16];
                        if (ren & out_dst_rdy)
                        begin
                                nextrstate = 3;
                        end
                end
                3: // waiting for read 4
                begin
                        out_data = word_reg[31:24];
                        out_eof = 1;
                        if (ren & out_dst_rdy)
                        begin
                                nextrstate = 0;
                        end
                end
        endcase
end
 
always@(posedge clk or posedge rst)
begin
        if (rst)
                rstate <= 0;
        else
                rstate <= nextrstate;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// 32 bit Port Register`
2
3			`timescale 1ns/100ps
4
5			`module port_register(`
6			`input clk,`
7			`input rst,`
8			`input wen,`
9			`input ren,`
10			`input in_sof,`
11			`input in_eof,`
12			`input in_src_rdy,`
13			`output in_dst_rdy,`
14			`input [7:0] in_data,`
15
16			`output reg out_sof,`
17			`output reg out_eof,`
18			`input out_dst_rdy,`
19			`output out_src_rdy,`
20			`output reg [7:0] out_data`
21			`);`
22
23
24			`reg reg_enable;`
25			`reg shift_en;`
26			`reg [1:0] rstate;`
27			`reg [1:0] nextrstate;`
28			`reg [23:0] shift_reg;`
29			`reg [31:0] word_reg;`
30			`reg [1:0] wstate;`
31			`reg [1:0] nextwstate;`
32
33			`assign in_dst_rdy = 1;`
34			`assign out_src_rdy = 1;`
35
36			`always@(wstate, wen, in_sof, in_src_rdy)`
37			`begin`
38			`reg_enable = 0;`
39			`shift_en = 0;`
40			`nextwstate = wstate;`
41			`case (wstate)`
42			`0: // waiting byte 0`
43			`begin`
44			`if (wen & in_sof & in_src_rdy)`
45			`begin`
46			`shift_en = 1;`
47			`nextwstate = 1;`
48			`end`
49			`end`
50			`1: // waiting byte 1`
51			`begin`
52			`if (wen & in_src_rdy)`
53			`begin`
54			`shift_en = 1;`
55			`nextwstate = 2;`
56			`end`
57			`end`
58			`2: // waiting byte 2`
59			`begin`
60			`if (wen & in_src_rdy)`
61			`begin`
62			`shift_en = 1;`
63			`nextwstate = 3;`
64			`end`
65			`end`
66			`3: // waiting byte 3`
67			`begin`
68			`if (wen & in_src_rdy)`
69			`begin`
70			`reg_enable = 1;`
71			`nextwstate = 0;`
72			`end`
73			`end`
74			`endcase`
75			`end`
76
77			`always@(posedge clk or posedge rst)`
78			`begin`
79			`if (rst)`
80			`wstate <= 0;`
81			`else`
82			`wstate <= nextwstate;`
83			`end`
84
85			`// shift register and word register`
86			`always@(posedge clk or posedge rst)`
87			`begin`
88			`if (rst)`
89			`begin`
90			`shift_reg <= 0;`
91			`word_reg <= 0;`
92			`end`
93			`else`
94			`begin`
95			`if (shift_en)`
96			`begin`
97			`shift_reg <= {in_data, shift_reg[23:8]};`
98			`end`
99			`if (reg_enable)`
100			`begin`
101			`word_reg <= {in_data, shift_reg};`
102			`end`
103			`end`
104			`end`
105
106			`always@(rstate or ren or out_dst_rdy)`
107			`begin`
108			`out_data = 0;`
109			`out_eof = 0;`
110			`out_sof = 0;`
111			`nextrstate = rstate;`
112			`case (rstate)`
113			`0: // waiting for read`
114			`begin`
115			`out_data = word_reg[7:0];`
116			`out_sof = 1;`
117			`if (ren & out_dst_rdy)`
118			`begin`
119			`nextrstate = 1;`
120			`end`
121			`end`
122			`1: // waiting for read 2`
123			`begin`
124			`out_data = word_reg[15:8];`
125			`if (ren & out_dst_rdy)`
126			`begin`
127			`nextrstate = 2;`
128			`end`
129			`end`
130			`2: // waiting for read 3`
131			`begin`
132			`out_data = word_reg[23:16];`
133			`if (ren & out_dst_rdy)`
134			`begin`
135			`nextrstate = 3;`
136			`end`
137			`end`
138			`3: // waiting for read 4`
139			`begin`
140			`out_data = word_reg[31:24];`
141			`out_eof = 1;`
142			`if (ren & out_dst_rdy)`
143			`begin`
144			`nextrstate = 0;`
145			`end`
146			`end`
147			`endcase`
148			`end`
149
150			`always@(posedge clk or posedge rst)`
151			`begin`
152			`if (rst)`
153			`rstate <= 0;`
154			`else`
155			`rstate <= nextrstate;`
156			`end`
157
158			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [port_register/] [port_register.v] - Blame information for rev 2