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[/] [fpu_double/] [trunk/] [fpu_sub.vhd] - Blame information for rev 8

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1 2 davidklun
---------------------------------------------------------------------
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----                                                             ----
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----  FPU                                                        ----
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----  Floating Point Unit (Double precision)                     ----
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----                                                             ----
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----  Author: David Lundgren                                     ----
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----          davidklun@gmail.com                                ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2009 David Lundgren                           ----
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----                  davidklun@gmail.com                        ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
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        LIBRARY ieee;
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        USE ieee.std_logic_1164.all;
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        USE ieee.std_logic_arith.all;
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        use ieee.std_logic_unsigned.all;
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        use ieee.std_logic_misc.all;
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        library work;
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        use work.fpupack.all;
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        ENTITY fpu_sub IS
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   PORT(
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      clk : IN     std_logic;
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      rst : IN     std_logic;
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      enable  : IN     std_logic;
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      opa : IN     std_logic_vector (63 DOWNTO 0);
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      opb : IN     std_logic_vector (63 DOWNTO 0);
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      fpu_op : IN     std_logic_vector (2 DOWNTO 0);
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      sign : OUT    std_logic;
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      diff_2 : OUT    std_logic_vector (55 DOWNTO 0);
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      exponent_2 : OUT    std_logic_vector (10 DOWNTO 0)
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   );
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        -- Declarations
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        END fpu_sub;
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        architecture rtl of fpu_sub is
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        signal   fpu_op_add : std_logic;
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        signal   diff_shift : std_logic_vector(5 downto 0);
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        signal   diff_shift_2 : std_logic_vector(5 downto 0);
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        signal   exponent_a : std_logic_vector(10 downto 0);
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        signal   exponent_b : std_logic_vector(10 downto 0);
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        signal   mantissa_a : std_logic_vector(51 downto 0);
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        signal   mantissa_b : std_logic_vector(51 downto 0);
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        signal   expa_gt_expb : std_logic;
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        signal   expa_et_expb : std_logic;
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        signal   mana_gtet_manb : std_logic;
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        signal   a_gtet_b : std_logic;
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        signal   exponent_small : std_logic_vector(10 downto 0);
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        signal   exponent_large : std_logic_vector(10 downto 0);
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        signal   mantissa_small : std_logic_vector(51 downto 0);
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        signal   mantissa_large : std_logic_vector(51 downto 0);
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        signal   small_is_denorm : std_logic;
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        signal   large_is_denorm : std_logic;
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        signal   large_norm_small_denorm : std_logic;
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        signal   small_is_nonzero : std_logic;
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        signal   exponent_diff : std_logic_vector(10 downto 0);
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        signal   minuend : std_logic_vector(54 downto 0);
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        signal   subtrahend : std_logic_vector(54 downto 0);
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        signal   subtra_shift : std_logic_vector(54 downto 0);
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        signal   subtra_shift_nonzero : std_logic;
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        signal   subtra_fraction_enable : std_logic;
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        signal   subtra_shift_2 : std_logic_vector(54 downto 0);
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        signal   subtra_shift_3 : std_logic_vector(54 downto 0);
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        signal   diff : std_logic_vector(54 downto 0);
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        signal   diffshift_gt_exponent : std_logic;
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        signal   diffshift_et_55 : std_logic; -- when the difference = 0
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        signal   diff_1 : std_logic_vector(54 downto 0);
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        signal   exponent : std_logic_vector(10 downto 0);
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        signal   in_norm_out_denorm : std_logic;
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        begin
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        subtra_shift_nonzero <= or_reduce(subtra_shift);
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        subtra_fraction_enable <= small_is_nonzero and not subtra_shift_nonzero;
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        subtra_shift_2 <= "0000000000000000000000000000000000000000000000000000001";
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        in_norm_out_denorm <= or_reduce(exponent_large) and not or_reduce(exponent);
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        fpu_op_add <= '1' when fpu_op = "000" else '0';
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process
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        begin
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        wait until clk'event and clk = '1';
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                if (rst = '1') then
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                        exponent_a <= (others =>'0');
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                        exponent_b <= (others =>'0');
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                        mantissa_a <= (others =>'0');
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                        mantissa_b <= (others =>'0');
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                        expa_gt_expb <= '0';
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                        expa_et_expb <= '0';
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                        mana_gtet_manb <= '0';
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                        a_gtet_b <= '0';
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                        exponent_small  <= (others =>'0');
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                        exponent_large  <= (others =>'0');
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                        mantissa_small  <= (others =>'0');
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                        mantissa_large  <= (others =>'0');
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                        sign <= '0';
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                        small_is_denorm <= '0';
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                        large_is_denorm <= '0';
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                        large_norm_small_denorm <= '0';
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                        small_is_nonzero <= '0';
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                        exponent_diff <= (others =>'0');
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                        minuend <= (others =>'0');
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                        subtrahend <= (others =>'0');
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                        subtra_shift <= (others =>'0');
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                        subtra_shift_3 <= (others =>'0');
132 8 davidklun
                        diff_shift <= (others =>'0');
133 2 davidklun
                        diff_shift_2 <= (others =>'0');
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                        diff <= (others =>'0');
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                        diffshift_gt_exponent <= '0';
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                        diffshift_et_55 <= '0';
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                        diff_1 <= (others =>'0');
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                        exponent <= (others =>'0');
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                        exponent_2 <= (others =>'0');
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                        diff_2 <= (others =>'0');
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                elsif (enable = '1') then
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                        exponent_a <= opa(62 downto 52);
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                        exponent_b <= opb(62 downto 52);
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                        mantissa_a <= opa(51 downto 0);
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                        mantissa_b <= opb(51 downto 0);
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                        if (exponent_a > exponent_b) then
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                                expa_gt_expb <= '1';
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                        else
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                                expa_gt_expb <= '0';
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                        end if;
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                        if (exponent_a = exponent_b) then
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                                expa_et_expb <= '1';
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                        else
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                                expa_et_expb <= '0';
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                        end if;
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                        if (mantissa_a >= mantissa_b) then
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                                mana_gtet_manb <= '1';
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                        else
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                                mana_gtet_manb <= '0';
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                        end if;
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                        a_gtet_b <= expa_gt_expb or (expa_et_expb and mana_gtet_manb);
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                        if (a_gtet_b = '1') then
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                                exponent_small <= exponent_b;
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                                exponent_large <= exponent_a;
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                                mantissa_small <= mantissa_b;
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                                mantissa_large <= mantissa_a;
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                                sign <= opa(63);
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                        else
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                                exponent_small <= exponent_a;
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                                exponent_large <= exponent_b;
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                                mantissa_small <= mantissa_a;
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                                mantissa_large <= mantissa_b;
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                                sign <= (not opb(63)) xor fpu_op_add;
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                        end if;
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                        if (exponent_small > 0) then
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                                small_is_denorm <= '0';
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                        else
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                                small_is_denorm <= '1';
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                        end if;
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                        if (exponent_large > 0) then
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                                large_is_denorm <= '0';
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                        else
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                                large_is_denorm <= '1';
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                        end if;
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                        if (small_is_denorm = '1' and large_is_denorm = '0') then
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                                large_norm_small_denorm <= '1';
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                        else
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                                large_norm_small_denorm <= '0';
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                        end if;
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                        small_is_nonzero <= (not small_is_denorm) or or_reduce(mantissa_small);
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                        exponent_diff <= exponent_large - exponent_small - large_norm_small_denorm;
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                        minuend <= not large_is_denorm & mantissa_large & "00";
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                        subtrahend <= not small_is_denorm & mantissa_small & "00";
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                        subtra_shift <= shr(subtrahend,  exponent_diff);
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                        if (subtra_fraction_enable = '1') then
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                                subtra_shift_3 <= subtra_shift_2;
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                        else
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                                subtra_shift_3 <= subtra_shift;
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                        end if;
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                        diff <= minuend - subtra_shift_3;
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                        diff_shift <= count_l_zeros(diff(54 downto 0));
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                        diff_shift_2 <= diff_shift;
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                        if (diff_shift_2 > exponent_large) then
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                                diffshift_gt_exponent <= '1';
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                        else
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                                diffshift_gt_exponent <= '0';
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                        end if;
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                        if (diff_shift_2 = "0110111") then -- 55
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                                diffshift_et_55 <= '1';
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                        else
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                                diffshift_et_55 <= '0';
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                        end if;
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                        if (diffshift_gt_exponent = '1') then
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                                diff_1 <= shl(diff, exponent_large);
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                                exponent <= "00000000000";
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                        else
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                                diff_1 <= shl(diff, diff_shift_2);
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                                exponent <= exponent_large - diff_shift_2;
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                        end if;
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                        if (diffshift_et_55 = '1') then
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                                exponent_2 <= "00000000000";
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                        else
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                                exponent_2 <=  exponent;
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                        end if;
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                        if (in_norm_out_denorm = '1') then
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                                diff_2 <= '0' & shr(diff_1,conv_std_logic_vector('1', 55));
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                        else
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                                diff_2 <= '0' & diff_1;
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                        end if;
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                end if;
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        end process;
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        end rtl;
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