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fabiop |
-- FPz8 simple timer
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-- By Fabio Pereira
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all ;
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entity fpz8_timer IS
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port
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(
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RAB : in std_logic_vector(11 downto 0);
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RIDB : in std_logic_vector(7 downto 0);
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RODB : out std_logic_vector(7 downto 0);
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SIDB : in std_logic_vector(7 downto 0);
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REG_SEL : in std_logic;
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WR : in std_logic;
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CLK_IN : in std_logic;
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STOP : in std_logic;
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INT : out std_logic;
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TMR_OUT : out std_logic;
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TMR_IN : in std_logic;
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TMR_ID : in std_logic_vector(1 downto 0);
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RESET : in std_logic
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);
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end fpz8_timer;
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architecture timer of fpz8_timer is
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shared variable TMR_EN : std_logic;
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shared variable TMR_CMP : std_logic_vector(15 downto 0);
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shared variable TMR_TEMP : std_logic_vector(7 downto 0);
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shared variable TMR_PRESEL : std_logic_vector(2 downto 0);
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shared variable TMR_CNT : std_logic_vector(15 downto 0);
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shared variable TMR_PRE : std_logic_vector(7 downto 0);
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shared variable INT_OUT : std_logic;
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shared variable BASE_ADDR : std_logic_vector(11 downto 0);
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begin
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control: process(CLK_IN,REG_SEL,RESET)
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begin
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INT <= INT_OUT;
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case TMR_ID is
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when "00" => BASE_ADDR := x"F00";
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when "01" => BASE_ADDR := x"F08";
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when "10" => BASE_ADDR := x"F10";
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when "11" => BASE_ADDR := x"F18";
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end case;
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if (RESET='1') then
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TMR_EN := '0';
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TMR_CMP := x"0000";
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TMR_TEMP := x"00";
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elsif (rising_edge(CLK_IN) and REG_SEL='1') then
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if (WR='0') then -- it is a reading operation
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if (RAB=(BASE_ADDR+7)) then ------ register TMR_CTL
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RODB<=TMR_EN&'0'&TMR_PRESEL&"000";
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elsif (RAB=BASE_ADDR+2) then -- register TMR_CMPH
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RODB<=TMR_CMP(15 downto 8);
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elsif (RAB=BASE_ADDR+3) then -- register TMR_CMPL
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RODB<=TMR_CMP(7 downto 0);
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else RODB<=SIDB;
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end if;
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else -- it is a writing operation
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if (RAB=BASE_ADDR+7) then ----- register TMR_CTL
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TMR_EN:=RIDB(7);
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TMR_PRESEL:=RIDB(5 downto 3);
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elsif (RAB=BASE_ADDR+2) then -- register TMR_RLH
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TMR_TEMP := RIDB;
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elsif (RAB=BASE_ADDR+3) then -- register TMR_RLL
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TMR_CMP(7 downto 0) := RIDB;
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TMR_CMP(15 downto 8) := TMR_TEMP;
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end if;
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end if;
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end if;
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end process control; -- control process
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counter: process(CLK_IN,RESET,STOP)
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variable TMR_PRECP : std_logic_vector(7 downto 0);
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begin
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if (RESET='1') then
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TMR_CNT := x"0000";
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TMR_PRE := x"00";
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TMR_PRECP := x"00";
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INT_OUT := '0';
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elsif (rising_edge(CLK_IN)) then
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if (STOP='0') then
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if (TMR_EN='1') then
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case TMR_PRESEL is
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when "000" => TMR_PRECP:=x"01"; -- prescaler divide by 1
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when "001" => TMR_PRECP:=x"02"; -- prescaler divide by 2
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when "010" => TMR_PRECP:=x"04"; -- prescaler divide by 4
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when "011" => TMR_PRECP:=x"08"; -- prescaler divide by 8
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when "100" => TMR_PRECP:=x"10"; -- prescaler divide by 16
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when "101" => TMR_PRECP:=x"20"; -- prescaler divide by 32
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when "110" => TMR_PRECP:=x"40"; -- prescaler divide by 64
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when others => TMR_PRECP:=x"80"; -- prescaler divide by 128
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end case;
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TMR_PRE := TMR_PRE + 1;
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if (TMR_PRE=TMR_PRECP) then
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TMR_PRE:=x"00";
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TMR_CNT:=TMR_CNT+1;
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if (TMR_CNT=TMR_CMP) then
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TMR_CNT:=x"0000";
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INT_OUT := not INT_OUT;
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end if;
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end if;
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else
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TMR_CNT:=x"0000";
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TMR_PRE:=x"00";
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end if; -- if TMR_EN=1
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end if; -- if STOP=0
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end if; -- rising edge of CLK_IN
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end process; -- counter process
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end timer;
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