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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [2.0/] [hdl/] [nios2_sdram.qsys] - Blame information for rev 177

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Line No. Rev Author Line
1 177 lanttu
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   name="$${FILENAME}"
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   displayName="$${FILENAME}"
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   version="1.0"
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   description=""
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   tags=""
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   categories="System" />
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{
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   element $${FILENAME}
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   {
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   }
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   element jtag_uart_1.avalon_jtag_slave
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   {
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      datum baseAddress
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      {
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         value = "12872";
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         type = "String";
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      }
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   }
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   element hibi_pe_dma_0.avalon_slave_0
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   {
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      datum _lockedAddress
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      {
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         value = "0";
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         type = "boolean";
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      }
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      datum baseAddress
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      {
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         value = "12288";
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         type = "String";
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      }
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   }
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   element clk_0
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   {
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      datum _sortIndex
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      {
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         value = "0";
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         type = "int";
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      }
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   }
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   element sysid_qsys_1.control_slave
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   {
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      datum baseAddress
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      {
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         value = "12864";
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         type = "String";
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      }
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   }
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   element hibi_pe_dma_0
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   {
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      datum _sortIndex
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      {
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         value = "8";
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         type = "int";
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      }
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   }
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   element nios2_qsys_1.jtag_debug_module
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   {
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      datum baseAddress
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      {
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         value = "10240";
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         type = "String";
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      }
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   }
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   element jtag_uart_1
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   {
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      datum _sortIndex
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      {
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         value = "7";
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         type = "int";
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      }
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   }
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   element nios2_qsys_1
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   {
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      datum _sortIndex
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      {
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         value = "1";
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         type = "int";
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      }
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   }
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   element onchip_memory2_1
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   {
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      datum _sortIndex
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      {
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         value = "2";
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         type = "int";
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      }
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   }
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   element sdram_0.s1
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   {
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      datum baseAddress
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      {
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         value = "33554432";
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         type = "String";
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      }
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   }
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   element onchip_memory2_1.s1
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   {
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      datum _lockedAddress
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      {
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         value = "1";
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         type = "boolean";
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      }
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      datum baseAddress
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      {
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         value = "0";
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         type = "String";
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      }
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   }
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   element timer_0.s1
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   {
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      datum baseAddress
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      {
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         value = "12800";
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         type = "String";
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      }
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   }
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   element timer_1.s1
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   {
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      datum baseAddress
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      {
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         value = "12832";
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         type = "String";
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      }
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   }
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   element onchip_memory2_1.s2
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   {
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      datum _lockedAddress
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      {
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         value = "1";
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         type = "boolean";
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      }
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      datum baseAddress
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      {
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         value = "0";
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         type = "String";
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      }
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   }
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   element sdram_0
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   {
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      datum _sortIndex
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      {
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         value = "3";
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         type = "int";
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      }
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      datum megawizard_uipreferences
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      {
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         value = "{output_language=VERILOG, output_directory=D:\\user\\matilail\\repos\\opencores_lib\\Altera\\ip.hwp.cpu\\nios_ii_sdram\\1.2\\hdl}";
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         type = "String";
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      }
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   }
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   element sysid_qsys_1
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   {
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      datum _sortIndex
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      {
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         value = "4";
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         type = "int";
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      }
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   }
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   element timer_0
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   {
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      datum _sortIndex
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      {
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         value = "5";
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         type = "int";
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      }
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   }
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   element timer_1
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   {
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      datum _sortIndex
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      {
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         value = "6";
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         type = "int";
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      }
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   }
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}
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]]>
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   name="hibi_pe_dma"
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   internal="hibi_pe_dma_0.conduit_end"
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   type="conduit"
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   dir="end" />
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   kind="altera_nios2_qsys"
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   version="12.1"
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   enabled="1"
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   name="nios2_qsys_1">
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  nios2_qsys_1.jtag_debug_module
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  ]]>
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  ]]>
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  NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
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   kind="altera_avalon_onchip_memory2"
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   version="12.1"
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   enabled="1"
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   name="onchip_memory2_1">
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  $${FILENAME}_onchip_memory2_1
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   kind="altera_avalon_jtag_uart"
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   version="12.1"
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   enabled="1"
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   name="jtag_uart_1">
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  INTERACTIVE_ASCII_OUTPUT
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   kind="altera_avalon_sysid_qsys"
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   version="12.1"
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   enabled="1"
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   name="sysid_qsys_1">
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   kind="altera_avalon_new_sdram_controller"
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   version="12.1"
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   enabled="1"
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   name="sdram_0">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.instruction_master"
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   end="nios2_qsys_1.jtag_debug_module">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="nios2_qsys_1.jtag_debug_module">
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="sdram_0.reset" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="timer_1.reset" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="timer_0.reset" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="sysid_qsys_1.reset" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="jtag_uart_1.reset" />
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   kind="clock"
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   version="12.1"
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   start="clk_0.clk"
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   end="onchip_memory2_1.clk2" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="onchip_memory2_1.reset2" />
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   kind="clock"
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   version="12.1"
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   start="clk_0.clk"
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   end="onchip_memory2_1.clk1" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="onchip_memory2_1.reset1" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="nios2_qsys_1.reset_n" />
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   kind="interrupt"
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   version="12.1"
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   start="nios2_qsys_1.d_irq"
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   end="jtag_uart_1.irq">
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   kind="interrupt"
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   version="12.1"
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   start="nios2_qsys_1.d_irq"
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   end="timer_1.irq">
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   kind="interrupt"
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   version="12.1"
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   start="nios2_qsys_1.d_irq"
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   end="timer_0.irq">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="jtag_uart_1.avalon_jtag_slave">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="timer_1.s1">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="timer_0.s1">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="sysid_qsys_1.control_slave">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="sdram_0.s1">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.instruction_master"
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   end="sdram_0.s1">
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="onchip_memory2_1.s1">
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   kind="clock"
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   version="12.1"
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   start="clk_0.clk"
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   end="hibi_pe_dma_0.clock" />
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   kind="reset"
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   version="12.1"
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   start="clk_0.clk_reset"
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   end="hibi_pe_dma_0.clock_sink_reset" />
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   kind="avalon"
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   version="12.1"
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   start="nios2_qsys_1.data_master"
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   end="hibi_pe_dma_0.avalon_slave_0">
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   kind="interrupt"
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   version="12.1"
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   start="nios2_qsys_1.d_irq"
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   end="hibi_pe_dma_0.interrupt_sender">
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   kind="avalon"
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   version="12.1"
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   start="hibi_pe_dma_0.avalon_master"
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   end="onchip_memory2_1.s2">
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   kind="avalon"
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   version="12.1"
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   start="hibi_pe_dma_0.avalon_master_1"
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   end="onchip_memory2_1.s2">
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