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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [hdl/] [jtag_uart_1.v] - Blame information for rev 147

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//Legal Notice: (C)2012 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_log_module (
                                // inputs:
                                 clk,
                                 data,
                                 strobe,
                                 valid
                              )
;
 
  input            clk;
  input   [  7: 0] data;
  input            strobe;
  input            valid;
 
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
   reg [31:0] text_handle; // for $fopen
   initial text_handle = $fopen ("jtag_uart_1_output_stream.dat");
 
   always @(posedge clk) begin
      if (valid && strobe) begin
         $fwrite (text_handle, "%b\n", data);
          // echo raw binary strings to file as ascii to screen
         $write("%s", ((data == 8'hd) ? 8'ha : data));
 
         // non-standard; poorly documented; required to get real data stream.
         $fflush (text_handle);
      end
   end // clk
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_sim_scfifo_w (
                                  // inputs:
                                   clk,
                                   fifo_wdata,
                                   fifo_wr,
 
                                  // outputs:
                                   fifo_FF,
                                   r_dat,
                                   wfifo_empty,
                                   wfifo_used
                                )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart_1_log, which is an e_log
  jtag_uart_1_log_module jtag_uart_1_log
    (
      .clk    (clk),
      .data   (fifo_wdata),
      .strobe (fifo_wr),
      .valid  (fifo_wr)
    );
 
  assign wfifo_used = {6{1'b0}};
  assign r_dat = {8{1'b0}};
  assign fifo_FF = 1'b0;
  assign wfifo_empty = 1'b1;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_scfifo_w (
                              // inputs:
                               clk,
                               fifo_clear,
                               fifo_wdata,
                               fifo_wr,
                               rd_wfifo,
 
                              // outputs:
                               fifo_FF,
                               r_dat,
                               wfifo_empty,
                               wfifo_used
                            )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input            fifo_clear;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
  input            rd_wfifo;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  jtag_uart_1_sim_scfifo_w the_jtag_uart_1_sim_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo wfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (fifo_wdata),
//      .empty (wfifo_empty),
//      .full (fifo_FF),
//      .q (r_dat),
//      .rdreq (rd_wfifo),
//      .usedw (wfifo_used),
//      .wrreq (fifo_wr)
//    );
//
//  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           wfifo.lpm_numwords = 64,
//           wfifo.lpm_showahead = "OFF",
//           wfifo.lpm_type = "scfifo",
//           wfifo.lpm_width = 8,
//           wfifo.lpm_widthu = 6,
//           wfifo.overflow_checking = "OFF",
//           wfifo.underflow_checking = "OFF",
//           wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_drom_module (
                                 // inputs:
                                  clk,
                                  incr_addr,
                                  reset_n,
 
                                 // outputs:
                                  new_rom,
                                  num_bytes,
                                  q,
                                  safe
                               )
;
 
  parameter POLL_RATE = 100;
 
 
  output           new_rom;
  output  [ 31: 0] num_bytes;
  output  [  7: 0] q;
  output           safe;
  input            clk;
  input            incr_addr;
  input            reset_n;
 
  reg     [ 11: 0] address;
  reg              d1_pre;
  reg              d2_pre;
  reg              d3_pre;
  reg              d4_pre;
  reg              d5_pre;
  reg              d6_pre;
  reg              d7_pre;
  reg              d8_pre;
  reg              d9_pre;
  reg     [  7: 0] mem_array [2047: 0];
  reg     [ 31: 0] mutex [  1: 0];
  reg              new_rom;
  wire    [ 31: 0] num_bytes;
  reg              pre;
  wire    [  7: 0] q;
  wire             safe;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  assign q = mem_array[address];
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          d1_pre <= 0;
          d2_pre <= 0;
          d3_pre <= 0;
          d4_pre <= 0;
          d5_pre <= 0;
          d6_pre <= 0;
          d7_pre <= 0;
          d8_pre <= 0;
          d9_pre <= 0;
          new_rom <= 0;
        end
      else
        begin
          d1_pre <= pre;
          d2_pre <= d1_pre;
          d3_pre <= d2_pre;
          d4_pre <= d3_pre;
          d5_pre <= d4_pre;
          d6_pre <= d5_pre;
          d7_pre <= d6_pre;
          d8_pre <= d7_pre;
          d9_pre <= d8_pre;
          new_rom <= d9_pre;
        end
    end
 
 
 
   assign     num_bytes = mutex[1];
                   reg        safe_delay;
   reg [31:0] poll_count;
   reg [31:0] mutex_handle;
   wire       interactive = 1'b0 ; // '
   assign     safe = (address < mutex[1]);
 
   initial poll_count = POLL_RATE;
 
   always @(posedge clk or negedge reset_n) begin
      if (reset_n !== 1) begin
         safe_delay <= 0;
      end else begin
         safe_delay <= safe;
      end
   end // safe_delay
 
   always @(posedge clk or negedge reset_n) begin
      if (reset_n !== 1) begin  // dont worry about null _stream.dat file
         address <= 0;
         mem_array[0] <= 0;
         mutex[0] <= 0;
         mutex[1] <= 0;
         pre <= 0;
      end else begin            // deal with the non-reset case
         pre <= 0;
         if (incr_addr && safe) address <= address + 1;
         if (mutex[0] && !safe && safe_delay) begin
            // and blast the mutex after falling edge of safe if interactive
            if (interactive) begin
               mutex_handle = $fopen ("jtag_uart_1_input_mutex.dat");
               $fdisplay (mutex_handle, "0");
               $fclose (mutex_handle);
               // $display ($stime, "\t%m:\n\t\tMutex cleared!");
            end else begin
               // sleep until next reset, do not bash mutex.
               wait (!reset_n);
            end
         end // OK to bash mutex.
         if (poll_count < POLL_RATE) begin // wait
            poll_count = poll_count + 1;
         end else begin         // do the interesting stuff.
            poll_count = 0;
            if (mutex_handle) begin
            $readmemh ("jtag_uart_1_input_mutex.dat", mutex);
            end
            if (mutex[0] && !safe) begin
            // read stream into mem_array after current characters are gone!
               // save mutex[0] value to compare to address (generates 'safe')
               mutex[1] <= mutex[0];
               // $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
               $readmemb("jtag_uart_1_input_stream.dat", mem_array);
               // bash address and send pulse outside to send the char:
               address <= 0;
               pre <= -1;
            end // else mutex miss...
         end // poll_count
      end // reset
   end // posedge clk
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_sim_scfifo_r (
                                  // inputs:
                                   clk,
                                   fifo_rd,
                                   rst_n,
 
                                  // outputs:
                                   fifo_EF,
                                   fifo_rdata,
                                   rfifo_full,
                                   rfifo_used
                                )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_rd;
  input            rst_n;
 
  reg     [ 31: 0] bytes_left;
  wire             fifo_EF;
  reg              fifo_rd_d;
  wire    [  7: 0] fifo_rdata;
  wire             new_rom;
  wire    [ 31: 0] num_bytes;
  wire    [  6: 0] rfifo_entries;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
  wire             safe;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart_1_drom, which is an e_drom
  jtag_uart_1_drom_module jtag_uart_1_drom
    (
      .clk       (clk),
      .incr_addr (fifo_rd_d),
      .new_rom   (new_rom),
      .num_bytes (num_bytes),
      .q         (fifo_rdata),
      .reset_n   (rst_n),
      .safe      (safe)
    );
 
  // Generate rfifo_entries for simulation
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          bytes_left <= 32'h0;
          fifo_rd_d <= 1'b0;
        end
      else
        begin
          fifo_rd_d <= fifo_rd;
          // decrement on read
          if (fifo_rd_d)
              bytes_left <= bytes_left - 1'b1;
          // catch new contents
          if (new_rom)
              bytes_left <= num_bytes;
        end
    end
 
 
  assign fifo_EF = bytes_left == 32'b0;
  assign rfifo_full = bytes_left > 7'h40;
  assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
  assign rfifo_used = rfifo_entries[5 : 0];
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1_scfifo_r (
                              // inputs:
                               clk,
                               fifo_clear,
                               fifo_rd,
                               rst_n,
                               t_dat,
                               wr_rfifo,
 
                              // outputs:
                               fifo_EF,
                               fifo_rdata,
                               rfifo_full,
                               rfifo_used
                            )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_clear;
  input            fifo_rd;
  input            rst_n;
  input   [  7: 0] t_dat;
  input            wr_rfifo;
 
  wire             fifo_EF;
  wire    [  7: 0] fifo_rdata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  jtag_uart_1_sim_scfifo_r the_jtag_uart_1_sim_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo rfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (t_dat),
//      .empty (fifo_EF),
//      .full (rfifo_full),
//      .q (fifo_rdata),
//      .rdreq (fifo_rd),
//      .usedw (rfifo_used),
//      .wrreq (wr_rfifo)
//    );
//
//  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           rfifo.lpm_numwords = 64,
//           rfifo.lpm_showahead = "OFF",
//           rfifo.lpm_type = "scfifo",
//           rfifo.lpm_width = 8,
//           rfifo.lpm_widthu = 6,
//           rfifo.overflow_checking = "OFF",
//           rfifo.underflow_checking = "OFF",
//           rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module jtag_uart_1 (
                     // inputs:
                      av_address,
                      av_chipselect,
                      av_read_n,
                      av_write_n,
                      av_writedata,
                      clk,
                      rst_n,
 
                     // outputs:
                      av_irq,
                      av_readdata,
                      av_waitrequest,
                      dataavailable,
                      readyfordata
                   )
  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
 
  output           av_irq;
  output  [ 31: 0] av_readdata;
  output           av_waitrequest;
  output           dataavailable;
  output           readyfordata;
  input            av_address;
  input            av_chipselect;
  input            av_read_n;
  input            av_write_n;
  input   [ 31: 0] av_writedata;
  input            clk;
  input            rst_n;
 
  reg              ac;
  wire             activity;
  wire             av_irq;
  wire    [ 31: 0] av_readdata;
  reg              av_waitrequest;
  reg              dataavailable;
  reg              fifo_AE;
  reg              fifo_AF;
  wire             fifo_EF;
  wire             fifo_FF;
  wire             fifo_clear;
  wire             fifo_rd;
  wire    [  7: 0] fifo_rdata;
  wire    [  7: 0] fifo_wdata;
  reg              fifo_wr;
  reg              ien_AE;
  reg              ien_AF;
  wire             ipen_AE;
  wire             ipen_AF;
  reg              pause_irq;
  wire    [  7: 0] r_dat;
  wire             r_ena;
  reg              r_val;
  wire             rd_wfifo;
  reg              read_0;
  reg              readyfordata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
  reg              rvalid;
  reg              sim_r_ena;
  reg              sim_t_dat;
  reg              sim_t_ena;
  reg              sim_t_pause;
  wire    [  7: 0] t_dat;
  reg              t_dav;
  wire             t_ena;
  wire             t_pause;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
  reg              woverflow;
  wire             wr_rfifo;
  //avalon_jtag_slave, which is an e_avalon_slave
  assign rd_wfifo = r_ena & ~wfifo_empty;
  assign wr_rfifo = t_ena & ~rfifo_full;
  assign fifo_clear = ~rst_n;
  jtag_uart_1_scfifo_w the_jtag_uart_1_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_clear  (fifo_clear),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .rd_wfifo    (rd_wfifo),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
  jtag_uart_1_scfifo_r the_jtag_uart_1_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_clear (fifo_clear),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n),
      .t_dat      (t_dat),
      .wr_rfifo   (wr_rfifo)
    );
 
  assign ipen_AE = ien_AE & fifo_AE;
  assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
  assign av_irq = ipen_AE | ipen_AF;
  assign activity = t_pause | t_ena;
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          pause_irq <= 1'b0;
      else // only if fifo is not empty...
      if (t_pause & ~fifo_EF)
          pause_irq <= 1'b1;
      else if (read_0)
          pause_irq <= 1'b0;
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          r_val <= 1'b0;
          t_dav <= 1'b1;
        end
      else
        begin
          r_val <= r_ena & ~wfifo_empty;
          t_dav <= ~rfifo_full;
        end
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          fifo_AE <= 1'b0;
          fifo_AF <= 1'b0;
          fifo_wr <= 1'b0;
          rvalid <= 1'b0;
          read_0 <= 1'b0;
          ien_AE <= 1'b0;
          ien_AF <= 1'b0;
          ac <= 1'b0;
          woverflow <= 1'b0;
          av_waitrequest <= 1'b1;
        end
      else
        begin
          fifo_AE <= {fifo_FF,wfifo_used} <= 8;
          fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
          fifo_wr <= 1'b0;
          read_0 <= 1'b0;
          av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
          if (activity)
              ac <= 1'b1;
          // write
          if (av_chipselect & ~av_write_n & av_waitrequest)
              // addr 1 is control; addr 0 is data
              if (av_address)
                begin
                  ien_AF <= av_writedata[0];
                  ien_AE <= av_writedata[1];
                  if (av_writedata[10] & ~activity)
                      ac <= 1'b0;
                end
              else
                begin
                  fifo_wr <= ~fifo_FF;
                  woverflow <= fifo_FF;
                end
          // read
          if (av_chipselect & ~av_read_n & av_waitrequest)
            begin
              // addr 1 is interrupt; addr 0 is data
              if (~av_address)
                  rvalid <= ~fifo_EF;
              read_0 <= ~av_address;
            end
        end
    end
 
 
  assign fifo_wdata = av_writedata[7 : 0];
  assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
  assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          readyfordata <= 0;
      else
        readyfordata <= ~fifo_FF;
    end
 
 
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  // Tie off Atlantic Interface signals not used for simulation
  always @(posedge clk)
    begin
      sim_t_pause <= 1'b0;
      sim_t_ena <= 1'b0;
      sim_t_dat <= t_dav ? r_dat : {8{r_val}};
      sim_r_ena <= 1'b0;
    end
 
 
  assign r_ena = sim_r_ena;
  assign t_ena = sim_t_ena;
  assign t_dat = sim_t_dat;
  assign t_pause = sim_t_pause;
  always @(fifo_EF)
    begin
      dataavailable = ~fifo_EF;
    end
 
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  alt_jtag_atlantic jtag_uart_1_alt_jtag_atlantic
//    (
//      .clk (clk),
//      .r_dat (r_dat),
//      .r_ena (r_ena),
//      .r_val (r_val),
//      .rst_n (rst_n),
//      .t_dat (t_dat),
//      .t_dav (t_dav),
//      .t_ena (t_ena),
//      .t_pause (t_pause)
//    );
//
//  defparam jtag_uart_1_alt_jtag_atlantic.INSTANCE_ID = 0,
//           jtag_uart_1_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
//           jtag_uart_1_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
//           jtag_uart_1_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
//  always @(posedge clk or negedge rst_n)
//    begin
//      if (rst_n == 0)
//          dataavailable <= 0;
//      else 
//        dataavailable <= ~fifo_EF;
//    end
//
//
//synthesis read_comments_as_HDL off
 
endmodule
 

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1	147	lanttu	`//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`// synthesis translate_off`
14			`timescale 1ns / 1ps
15			`// synthesis translate_on`
16
17			`// turn off superfluous verilog processor warnings`
18			`// altera message_level Level1`
19			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
20
21			`module jtag_uart_1_log_module (`
22			`// inputs:`
23			`clk,`
24			`data,`
25			`strobe,`
26			`valid`
27			`)`
28			`;`
29
30			`input clk;`
31			`input [ 7: 0] data;`
32			`input strobe;`
33			`input valid;`
34
35
36			`//synthesis translate_off`
37			`//////////////// SIMULATION-ONLY CONTENTS`
38			`reg [31:0] text_handle; // for $fopen`
39			`initial text_handle = $fopen ("jtag_uart_1_output_stream.dat");`
40
41			`always @(posedge clk) begin`
42			`if (valid && strobe) begin`
43			`$fwrite (text_handle, "%b\n", data);`
44			`// echo raw binary strings to file as ascii to screen`
45			`$write("%s", ((data == 8'hd) ? 8'ha : data));`
46
47			`// non-standard; poorly documented; required to get real data stream.`
48			`$fflush (text_handle);`
49			`end`
50			`end // clk`
51
52
53			`//////////////// END SIMULATION-ONLY CONTENTS`
54
55			`//synthesis translate_on`
56
57			`endmodule`
58
59
60			`// synthesis translate_off`
61			`timescale 1ns / 1ps
62			`// synthesis translate_on`
63
64			`// turn off superfluous verilog processor warnings`
65			`// altera message_level Level1`
66			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
67
68			`module jtag_uart_1_sim_scfifo_w (`
69			`// inputs:`
70			`clk,`
71			`fifo_wdata,`
72			`fifo_wr,`
73
74			`// outputs:`
75			`fifo_FF,`
76			`r_dat,`
77			`wfifo_empty,`
78			`wfifo_used`
79			`)`
80			`;`
81
82			`output fifo_FF;`
83			`output [ 7: 0] r_dat;`
84			`output wfifo_empty;`
85			`output [ 5: 0] wfifo_used;`
86			`input clk;`
87			`input [ 7: 0] fifo_wdata;`
88			`input fifo_wr;`
89
90			`wire fifo_FF;`
91			`wire [ 7: 0] r_dat;`
92			`wire wfifo_empty;`
93			`wire [ 5: 0] wfifo_used;`
94
95			`//synthesis translate_off`
96			`//////////////// SIMULATION-ONLY CONTENTS`
97			`//jtag_uart_1_log, which is an e_log`
98			`jtag_uart_1_log_module jtag_uart_1_log`
99			`(`
100			`.clk (clk),`
101			`.data (fifo_wdata),`
102			`.strobe (fifo_wr),`
103			`.valid (fifo_wr)`
104			`);`
105
106			`assign wfifo_used = {6{1'b0}};`
107			`assign r_dat = {8{1'b0}};`
108			`assign fifo_FF = 1'b0;`
109			`assign wfifo_empty = 1'b1;`
110
111			`//////////////// END SIMULATION-ONLY CONTENTS`
112
113			`//synthesis translate_on`
114
115			`endmodule`
116
117
118			`// synthesis translate_off`
119			`timescale 1ns / 1ps
120			`// synthesis translate_on`
121
122			`// turn off superfluous verilog processor warnings`
123			`// altera message_level Level1`
124			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
125
126			`module jtag_uart_1_scfifo_w (`
127			`// inputs:`
128			`clk,`
129			`fifo_clear,`
130			`fifo_wdata,`
131			`fifo_wr,`
132			`rd_wfifo,`
133
134			`// outputs:`
135			`fifo_FF,`
136			`r_dat,`
137			`wfifo_empty,`
138			`wfifo_used`
139			`)`
140			`;`
141
142			`output fifo_FF;`
143			`output [ 7: 0] r_dat;`
144			`output wfifo_empty;`
145			`output [ 5: 0] wfifo_used;`
146			`input clk;`
147			`input fifo_clear;`
148			`input [ 7: 0] fifo_wdata;`
149			`input fifo_wr;`
150			`input rd_wfifo;`
151
152			`wire fifo_FF;`
153			`wire [ 7: 0] r_dat;`
154			`wire wfifo_empty;`
155			`wire [ 5: 0] wfifo_used;`
156
157			`//synthesis translate_off`
158			`//////////////// SIMULATION-ONLY CONTENTS`
159			`jtag_uart_1_sim_scfifo_w the_jtag_uart_1_sim_scfifo_w`
160			`(`
161			`.clk (clk),`
162			`.fifo_FF (fifo_FF),`
163			`.fifo_wdata (fifo_wdata),`
164			`.fifo_wr (fifo_wr),`
165			`.r_dat (r_dat),`
166			`.wfifo_empty (wfifo_empty),`
167			`.wfifo_used (wfifo_used)`
168			`);`
169
170
171			`//////////////// END SIMULATION-ONLY CONTENTS`
172
173			`//synthesis translate_on`
174			`//synthesis read_comments_as_HDL on`
175			`// scfifo wfifo`
176			`// (`
177			`// .aclr (fifo_clear),`
178			`// .clock (clk),`
179			`// .data (fifo_wdata),`
180			`// .empty (wfifo_empty),`
181			`// .full (fifo_FF),`
182			`// .q (r_dat),`
183			`// .rdreq (rd_wfifo),`
184			`// .usedw (wfifo_used),`
185			`// .wrreq (fifo_wr)`
186			`// );`
187			`//`
188			`// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
189			`// wfifo.lpm_numwords = 64,`
190			`// wfifo.lpm_showahead = "OFF",`
191			`// wfifo.lpm_type = "scfifo",`
192			`// wfifo.lpm_width = 8,`
193			`// wfifo.lpm_widthu = 6,`
194			`// wfifo.overflow_checking = "OFF",`
195			`// wfifo.underflow_checking = "OFF",`
196			`// wfifo.use_eab = "ON";`
197			`//`
198			`//synthesis read_comments_as_HDL off`
199
200			`endmodule`
201
202
203			`// synthesis translate_off`
204			`timescale 1ns / 1ps
205			`// synthesis translate_on`
206
207			`// turn off superfluous verilog processor warnings`
208			`// altera message_level Level1`
209			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
210
211			`module jtag_uart_1_drom_module (`
212			`// inputs:`
213			`clk,`
214			`incr_addr,`
215			`reset_n,`
216
217			`// outputs:`
218			`new_rom,`
219			`num_bytes,`
220			`q,`
221			`safe`
222			`)`
223			`;`
224
225			`parameter POLL_RATE = 100;`
226
227
228			`output new_rom;`
229			`output [ 31: 0] num_bytes;`
230			`output [ 7: 0] q;`
231			`output safe;`
232			`input clk;`
233			`input incr_addr;`
234			`input reset_n;`
235
236			`reg [ 11: 0] address;`
237			`reg d1_pre;`
238			`reg d2_pre;`
239			`reg d3_pre;`
240			`reg d4_pre;`
241			`reg d5_pre;`
242			`reg d6_pre;`
243			`reg d7_pre;`
244			`reg d8_pre;`
245			`reg d9_pre;`
246			`reg [ 7: 0] mem_array [2047: 0];`
247			`reg [ 31: 0] mutex [ 1: 0];`
248			`reg new_rom;`
249			`wire [ 31: 0] num_bytes;`
250			`reg pre;`
251			`wire [ 7: 0] q;`
252			`wire safe;`
253
254			`//synthesis translate_off`
255			`//////////////// SIMULATION-ONLY CONTENTS`
256			`assign q = mem_array[address];`
257			`always @(posedge clk or negedge reset_n)`
258			`begin`
259			`if (reset_n == 0)`
260			`begin`
261			`d1_pre <= 0;`
262			`d2_pre <= 0;`
263			`d3_pre <= 0;`
264			`d4_pre <= 0;`
265			`d5_pre <= 0;`
266			`d6_pre <= 0;`
267			`d7_pre <= 0;`
268			`d8_pre <= 0;`
269			`d9_pre <= 0;`
270			`new_rom <= 0;`
271			`end`
272			`else`
273			`begin`
274			`d1_pre <= pre;`
275			`d2_pre <= d1_pre;`
276			`d3_pre <= d2_pre;`
277			`d4_pre <= d3_pre;`
278			`d5_pre <= d4_pre;`
279			`d6_pre <= d5_pre;`
280			`d7_pre <= d6_pre;`
281			`d8_pre <= d7_pre;`
282			`d9_pre <= d8_pre;`
283			`new_rom <= d9_pre;`
284			`end`
285			`end`
286
287
288
289			`assign num_bytes = mutex[1];`
290			`reg safe_delay;`
291			`reg [31:0] poll_count;`
292			`reg [31:0] mutex_handle;`
293			`wire interactive = 1'b0 ; // '`
294			`assign safe = (address < mutex[1]);`
295
296			`initial poll_count = POLL_RATE;`
297
298			`always @(posedge clk or negedge reset_n) begin`
299			`if (reset_n !== 1) begin`
300			`safe_delay <= 0;`
301			`end else begin`
302			`safe_delay <= safe;`
303			`end`
304			`end // safe_delay`
305
306			`always @(posedge clk or negedge reset_n) begin`
307			`if (reset_n !== 1) begin // dont worry about null _stream.dat file`
308			`address <= 0;`
309			`mem_array[0] <= 0;`
310			`mutex[0] <= 0;`
311			`mutex[1] <= 0;`
312			`pre <= 0;`
313			`end else begin // deal with the non-reset case`
314			`pre <= 0;`
315			`if (incr_addr && safe) address <= address + 1;`
316			`if (mutex[0] && !safe && safe_delay) begin`
317			`// and blast the mutex after falling edge of safe if interactive`
318			`if (interactive) begin`
319			`mutex_handle = $fopen ("jtag_uart_1_input_mutex.dat");`
320			`$fdisplay (mutex_handle, "0");`
321			`$fclose (mutex_handle);`
322			`// $display ($stime, "\t%m:\n\t\tMutex cleared!");`
323			`end else begin`
324			`// sleep until next reset, do not bash mutex.`
325			`wait (!reset_n);`
326			`end`
327			`end // OK to bash mutex.`
328			`if (poll_count < POLL_RATE) begin // wait`
329			`poll_count = poll_count + 1;`
330			`end else begin // do the interesting stuff.`
331			`poll_count = 0;`
332			`if (mutex_handle) begin`
333			`$readmemh ("jtag_uart_1_input_mutex.dat", mutex);`
334			`end`
335			`if (mutex[0] && !safe) begin`
336			`// read stream into mem_array after current characters are gone!`
337			`// save mutex[0] value to compare to address (generates 'safe')`
338			`mutex[1] <= mutex[0];`
339			`// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);`
340			`$readmemb("jtag_uart_1_input_stream.dat", mem_array);`
341			`// bash address and send pulse outside to send the char:`
342			`address <= 0;`
343			`pre <= -1;`
344			`end // else mutex miss...`
345			`end // poll_count`
346			`end // reset`
347			`end // posedge clk`
348
349
350			`//////////////// END SIMULATION-ONLY CONTENTS`
351
352			`//synthesis translate_on`
353
354			`endmodule`
355
356
357			`// synthesis translate_off`
358			`timescale 1ns / 1ps
359			`// synthesis translate_on`
360
361			`// turn off superfluous verilog processor warnings`
362			`// altera message_level Level1`
363			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
364
365			`module jtag_uart_1_sim_scfifo_r (`
366			`// inputs:`
367			`clk,`
368			`fifo_rd,`
369			`rst_n,`
370
371			`// outputs:`
372			`fifo_EF,`
373			`fifo_rdata,`
374			`rfifo_full,`
375			`rfifo_used`
376			`)`
377			`;`
378
379			`output fifo_EF;`
380			`output [ 7: 0] fifo_rdata;`
381			`output rfifo_full;`
382			`output [ 5: 0] rfifo_used;`
383			`input clk;`
384			`input fifo_rd;`
385			`input rst_n;`
386
387			`reg [ 31: 0] bytes_left;`
388			`wire fifo_EF;`
389			`reg fifo_rd_d;`
390			`wire [ 7: 0] fifo_rdata;`
391			`wire new_rom;`
392			`wire [ 31: 0] num_bytes;`
393			`wire [ 6: 0] rfifo_entries;`
394			`wire rfifo_full;`
395			`wire [ 5: 0] rfifo_used;`
396			`wire safe;`
397
398			`//synthesis translate_off`
399			`//////////////// SIMULATION-ONLY CONTENTS`
400			`//jtag_uart_1_drom, which is an e_drom`
401			`jtag_uart_1_drom_module jtag_uart_1_drom`
402			`(`
403			`.clk (clk),`
404			`.incr_addr (fifo_rd_d),`
405			`.new_rom (new_rom),`
406			`.num_bytes (num_bytes),`
407			`.q (fifo_rdata),`
408			`.reset_n (rst_n),`
409			`.safe (safe)`
410			`);`
411
412			`// Generate rfifo_entries for simulation`
413			`always @(posedge clk or negedge rst_n)`
414			`begin`
415			`if (rst_n == 0)`
416			`begin`
417			`bytes_left <= 32'h0;`
418			`fifo_rd_d <= 1'b0;`
419			`end`
420			`else`
421			`begin`
422			`fifo_rd_d <= fifo_rd;`
423			`// decrement on read`
424			`if (fifo_rd_d)`
425			`bytes_left <= bytes_left - 1'b1;`
426			`// catch new contents`
427			`if (new_rom)`
428			`bytes_left <= num_bytes;`
429			`end`
430			`end`
431
432
433			`assign fifo_EF = bytes_left == 32'b0;`
434			`assign rfifo_full = bytes_left > 7'h40;`
435			`assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;`
436			`assign rfifo_used = rfifo_entries[5 : 0];`
437
438			`//////////////// END SIMULATION-ONLY CONTENTS`
439
440			`//synthesis translate_on`
441
442			`endmodule`
443
444
445			`// synthesis translate_off`
446			`timescale 1ns / 1ps
447			`// synthesis translate_on`
448
449			`// turn off superfluous verilog processor warnings`
450			`// altera message_level Level1`
451			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
452
453			`module jtag_uart_1_scfifo_r (`
454			`// inputs:`
455			`clk,`
456			`fifo_clear,`
457			`fifo_rd,`
458			`rst_n,`
459			`t_dat,`
460			`wr_rfifo,`
461
462			`// outputs:`
463			`fifo_EF,`
464			`fifo_rdata,`
465			`rfifo_full,`
466			`rfifo_used`
467			`)`
468			`;`
469
470			`output fifo_EF;`
471			`output [ 7: 0] fifo_rdata;`
472			`output rfifo_full;`
473			`output [ 5: 0] rfifo_used;`
474			`input clk;`
475			`input fifo_clear;`
476			`input fifo_rd;`
477			`input rst_n;`
478			`input [ 7: 0] t_dat;`
479			`input wr_rfifo;`
480
481			`wire fifo_EF;`
482			`wire [ 7: 0] fifo_rdata;`
483			`wire rfifo_full;`
484			`wire [ 5: 0] rfifo_used;`
485
486			`//synthesis translate_off`
487			`//////////////// SIMULATION-ONLY CONTENTS`
488			`jtag_uart_1_sim_scfifo_r the_jtag_uart_1_sim_scfifo_r`
489			`(`
490			`.clk (clk),`
491			`.fifo_EF (fifo_EF),`
492			`.fifo_rd (fifo_rd),`
493			`.fifo_rdata (fifo_rdata),`
494			`.rfifo_full (rfifo_full),`
495			`.rfifo_used (rfifo_used),`
496			`.rst_n (rst_n)`
497			`);`
498
499
500			`//////////////// END SIMULATION-ONLY CONTENTS`
501
502			`//synthesis translate_on`
503			`//synthesis read_comments_as_HDL on`
504			`// scfifo rfifo`
505			`// (`
506			`// .aclr (fifo_clear),`
507			`// .clock (clk),`
508			`// .data (t_dat),`
509			`// .empty (fifo_EF),`
510			`// .full (rfifo_full),`
511			`// .q (fifo_rdata),`
512			`// .rdreq (fifo_rd),`
513			`// .usedw (rfifo_used),`
514			`// .wrreq (wr_rfifo)`
515			`// );`
516			`//`
517			`// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
518			`// rfifo.lpm_numwords = 64,`
519			`// rfifo.lpm_showahead = "OFF",`
520			`// rfifo.lpm_type = "scfifo",`
521			`// rfifo.lpm_width = 8,`
522			`// rfifo.lpm_widthu = 6,`
523			`// rfifo.overflow_checking = "OFF",`
524			`// rfifo.underflow_checking = "OFF",`
525			`// rfifo.use_eab = "ON";`
526			`//`
527			`//synthesis read_comments_as_HDL off`
528
529			`endmodule`
530
531
532			`// synthesis translate_off`
533			`timescale 1ns / 1ps
534			`// synthesis translate_on`
535
536			`// turn off superfluous verilog processor warnings`
537			`// altera message_level Level1`
538			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
539
540			`module jtag_uart_1 (`
541			`// inputs:`
542			`av_address,`
543			`av_chipselect,`
544			`av_read_n,`
545			`av_write_n,`
546			`av_writedata,`
547			`clk,`
548			`rst_n,`
549
550			`// outputs:`
551			`av_irq,`
552			`av_readdata,`
553			`av_waitrequest,`
554			`dataavailable,`
555			`readyfordata`
556			`)`
557			`/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;`
558
559			`output av_irq;`
560			`output [ 31: 0] av_readdata;`
561			`output av_waitrequest;`
562			`output dataavailable;`
563			`output readyfordata;`
564			`input av_address;`
565			`input av_chipselect;`
566			`input av_read_n;`
567			`input av_write_n;`
568			`input [ 31: 0] av_writedata;`
569			`input clk;`
570			`input rst_n;`
571
572			`reg ac;`
573			`wire activity;`
574			`wire av_irq;`
575			`wire [ 31: 0] av_readdata;`
576			`reg av_waitrequest;`
577			`reg dataavailable;`
578			`reg fifo_AE;`
579			`reg fifo_AF;`
580			`wire fifo_EF;`
581			`wire fifo_FF;`
582			`wire fifo_clear;`
583			`wire fifo_rd;`
584			`wire [ 7: 0] fifo_rdata;`
585			`wire [ 7: 0] fifo_wdata;`
586			`reg fifo_wr;`
587			`reg ien_AE;`
588			`reg ien_AF;`
589			`wire ipen_AE;`
590			`wire ipen_AF;`
591			`reg pause_irq;`
592			`wire [ 7: 0] r_dat;`
593			`wire r_ena;`
594			`reg r_val;`
595			`wire rd_wfifo;`
596			`reg read_0;`
597			`reg readyfordata;`
598			`wire rfifo_full;`
599			`wire [ 5: 0] rfifo_used;`
600			`reg rvalid;`
601			`reg sim_r_ena;`
602			`reg sim_t_dat;`
603			`reg sim_t_ena;`
604			`reg sim_t_pause;`
605			`wire [ 7: 0] t_dat;`
606			`reg t_dav;`
607			`wire t_ena;`
608			`wire t_pause;`
609			`wire wfifo_empty;`
610			`wire [ 5: 0] wfifo_used;`
611			`reg woverflow;`
612			`wire wr_rfifo;`
613			`//avalon_jtag_slave, which is an e_avalon_slave`
614			`assign rd_wfifo = r_ena & ~wfifo_empty;`
615			`assign wr_rfifo = t_ena & ~rfifo_full;`
616			`assign fifo_clear = ~rst_n;`
617			`jtag_uart_1_scfifo_w the_jtag_uart_1_scfifo_w`
618			`(`
619			`.clk (clk),`
620			`.fifo_FF (fifo_FF),`
621			`.fifo_clear (fifo_clear),`
622			`.fifo_wdata (fifo_wdata),`
623			`.fifo_wr (fifo_wr),`
624			`.r_dat (r_dat),`
625			`.rd_wfifo (rd_wfifo),`
626			`.wfifo_empty (wfifo_empty),`
627			`.wfifo_used (wfifo_used)`
628			`);`
629
630			`jtag_uart_1_scfifo_r the_jtag_uart_1_scfifo_r`
631			`(`
632			`.clk (clk),`
633			`.fifo_EF (fifo_EF),`
634			`.fifo_clear (fifo_clear),`
635			`.fifo_rd (fifo_rd),`
636			`.fifo_rdata (fifo_rdata),`
637			`.rfifo_full (rfifo_full),`
638			`.rfifo_used (rfifo_used),`
639			`.rst_n (rst_n),`
640			`.t_dat (t_dat),`
641			`.wr_rfifo (wr_rfifo)`
642			`);`
643
644			`assign ipen_AE = ien_AE & fifo_AE;`
645			`assign ipen_AF = ien_AF & (pause_irq \| fifo_AF);`
646			`assign av_irq = ipen_AE \| ipen_AF;`
647			`assign activity = t_pause \| t_ena;`
648			`always @(posedge clk or negedge rst_n)`
649			`begin`
650			`if (rst_n == 0)`
651			`pause_irq <= 1'b0;`
652			`else // only if fifo is not empty...`
653			`if (t_pause & ~fifo_EF)`
654			`pause_irq <= 1'b1;`
655			`else if (read_0)`
656			`pause_irq <= 1'b0;`
657			`end`
658
659
660			`always @(posedge clk or negedge rst_n)`
661			`begin`
662			`if (rst_n == 0)`
663			`begin`
664			`r_val <= 1'b0;`
665			`t_dav <= 1'b1;`
666			`end`
667			`else`
668			`begin`
669			`r_val <= r_ena & ~wfifo_empty;`
670			`t_dav <= ~rfifo_full;`
671			`end`
672			`end`
673
674
675			`always @(posedge clk or negedge rst_n)`
676			`begin`
677			`if (rst_n == 0)`
678			`begin`
679			`fifo_AE <= 1'b0;`
680			`fifo_AF <= 1'b0;`
681			`fifo_wr <= 1'b0;`
682			`rvalid <= 1'b0;`
683			`read_0 <= 1'b0;`
684			`ien_AE <= 1'b0;`
685			`ien_AF <= 1'b0;`
686			`ac <= 1'b0;`
687			`woverflow <= 1'b0;`
688			`av_waitrequest <= 1'b1;`
689			`end`
690			`else`
691			`begin`
692			`fifo_AE <= {fifo_FF,wfifo_used} <= 8;`
693			`fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;`
694			`fifo_wr <= 1'b0;`
695			`read_0 <= 1'b0;`
696			`av_waitrequest <= ~(av_chipselect & (~av_write_n \| ~av_read_n) & av_waitrequest);`
697			`if (activity)`
698			`ac <= 1'b1;`
699			`// write`
700			`if (av_chipselect & ~av_write_n & av_waitrequest)`
701			`// addr 1 is control; addr 0 is data`
702			`if (av_address)`
703			`begin`
704			`ien_AF <= av_writedata[0];`
705			`ien_AE <= av_writedata[1];`
706			`if (av_writedata[10] & ~activity)`
707			`ac <= 1'b0;`
708			`end`
709			`else`
710			`begin`
711			`fifo_wr <= ~fifo_FF;`
712			`woverflow <= fifo_FF;`
713			`end`
714			`// read`
715			`if (av_chipselect & ~av_read_n & av_waitrequest)`
716			`begin`
717			`// addr 1 is interrupt; addr 0 is data`
718			`if (~av_address)`
719			`rvalid <= ~fifo_EF;`
720			`read_0 <= ~av_address;`
721			`end`
722			`end`
723			`end`
724
725
726			`assign fifo_wdata = av_writedata[7 : 0];`
727			`assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;`
728			`assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };`
729			`always @(posedge clk or negedge rst_n)`
730			`begin`
731			`if (rst_n == 0)`
732			`readyfordata <= 0;`
733			`else`
734			`readyfordata <= ~fifo_FF;`
735			`end`
736
737
738
739			`//synthesis translate_off`
740			`//////////////// SIMULATION-ONLY CONTENTS`
741			`// Tie off Atlantic Interface signals not used for simulation`
742			`always @(posedge clk)`
743			`begin`
744			`sim_t_pause <= 1'b0;`
745			`sim_t_ena <= 1'b0;`
746			`sim_t_dat <= t_dav ? r_dat : {8{r_val}};`
747			`sim_r_ena <= 1'b0;`
748			`end`
749
750
751			`assign r_ena = sim_r_ena;`
752			`assign t_ena = sim_t_ena;`
753			`assign t_dat = sim_t_dat;`
754			`assign t_pause = sim_t_pause;`
755			`always @(fifo_EF)`
756			`begin`
757			`dataavailable = ~fifo_EF;`
758			`end`
759
760
761
762			`//////////////// END SIMULATION-ONLY CONTENTS`
763
764			`//synthesis translate_on`
765			`//synthesis read_comments_as_HDL on`
766			`// alt_jtag_atlantic jtag_uart_1_alt_jtag_atlantic`
767			`// (`
768			`// .clk (clk),`
769			`// .r_dat (r_dat),`
770			`// .r_ena (r_ena),`
771			`// .r_val (r_val),`
772			`// .rst_n (rst_n),`
773			`// .t_dat (t_dat),`
774			`// .t_dav (t_dav),`
775			`// .t_ena (t_ena),`
776			`// .t_pause (t_pause)`
777			`// );`
778			`//`
779			`// defparam jtag_uart_1_alt_jtag_atlantic.INSTANCE_ID = 0,`
780			`// jtag_uart_1_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,`
781			`// jtag_uart_1_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,`
782			`// jtag_uart_1_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";`
783			`//`
784			`// always @(posedge clk or negedge rst_n)`
785			`// begin`
786			`// if (rst_n == 0)`
787			`// dataavailable <= 0;`
788			`// else`
789			`// dataavailable <= ~fifo_EF;`
790			`// end`
791			`//`
792			`//`
793			`//synthesis read_comments_as_HDL off`
794
795			`endmodule`
796