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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [hdl/] [sdram_1.v] - Blame information for rev 147

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//Legal Notice: (C)2012 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module sdram_1_input_efifo_module (
                                    // inputs:
                                     clk,
                                     rd,
                                     reset_n,
                                     wr,
                                     wr_data,
 
                                    // outputs:
                                     almost_empty,
                                     almost_full,
                                     empty,
                                     full,
                                     rd_data
                                  )
;
 
  output           almost_empty;
  output           almost_full;
  output           empty;
  output           full;
  output  [ 40: 0] rd_data;
  input            clk;
  input            rd;
  input            reset_n;
  input            wr;
  input   [ 40: 0] wr_data;
 
  wire             almost_empty;
  wire             almost_full;
  wire             empty;
  reg     [  1: 0] entries;
  reg     [ 40: 0] entry_0;
  reg     [ 40: 0] entry_1;
  wire             full;
  reg              rd_address;
  reg     [ 40: 0] rd_data;
  wire    [  1: 0] rdwr;
  reg              wr_address;
  assign rdwr = {rd, wr};
  assign full = entries == 2;
  assign almost_full = entries >= 1;
  assign empty = entries == 0;
  assign almost_empty = entries <= 1;
  always @(entry_0 or entry_1 or rd_address)
    begin
      case (rd_address) // synthesis parallel_case full_case
 
          1'd0: begin
              rd_data = entry_0;
          end // 1'd0 
 
          1'd1: begin
              rd_data = entry_1;
          end // 1'd1 
 
          default: begin
          end // default
 
      endcase // rd_address
    end
 
 
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          wr_address <= 0;
          rd_address <= 0;
          entries <= 0;
        end
      else
        case (rdwr) // synthesis parallel_case full_case
 
            2'd1: begin
                // Write data
                if (!full)
                  begin
                    entries <= entries + 1;
                    wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
                  end
            end // 2'd1 
 
            2'd2: begin
                // Read data
                if (!empty)
                  begin
                    entries <= entries - 1;
                    rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
                  end
            end // 2'd2 
 
            2'd3: begin
                wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
                rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
            end // 2'd3 
 
            default: begin
            end // default
 
        endcase // rdwr
    end
 
 
  always @(posedge clk)
    begin
      //Write data
      if (wr & !full)
          case (wr_address) // synthesis parallel_case full_case
 
              1'd0: begin
                  entry_0 <= wr_data;
              end // 1'd0 
 
              1'd1: begin
                  entry_1 <= wr_data;
              end // 1'd1 
 
              default: begin
              end // default
 
          endcase // wr_address
    end
 
 
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module sdram_1 (
                 // inputs:
                  az_addr,
                  az_be_n,
                  az_cs,
                  az_data,
                  az_rd_n,
                  az_wr_n,
                  clk,
                  reset_n,
 
                 // outputs:
                  za_data,
                  za_valid,
                  za_waitrequest,
                  zs_addr,
                  zs_ba,
                  zs_cas_n,
                  zs_cke,
                  zs_cs_n,
                  zs_dq,
                  zs_dqm,
                  zs_ras_n,
                  zs_we_n
               )
;
 
  output  [ 15: 0] za_data;
  output           za_valid;
  output           za_waitrequest;
  output  [ 11: 0] zs_addr;
  output  [  1: 0] zs_ba;
  output           zs_cas_n;
  output           zs_cke;
  output           zs_cs_n;
  inout   [ 15: 0] zs_dq;
  output  [  1: 0] zs_dqm;
  output           zs_ras_n;
  output           zs_we_n;
  input   [ 21: 0] az_addr;
  input   [  1: 0] az_be_n;
  input            az_cs;
  input   [ 15: 0] az_data;
  input            az_rd_n;
  input            az_wr_n;
  input            clk;
  input            reset_n;
 
  wire    [ 23: 0] CODE;
  reg              ack_refresh_request;
  reg     [ 21: 0] active_addr;
  wire    [  1: 0] active_bank;
  reg              active_cs_n;
  reg     [ 15: 0] active_data;
  reg     [  1: 0] active_dqm;
  reg              active_rnw;
  wire             almost_empty;
  wire             almost_full;
  wire             bank_match;
  wire    [  7: 0] cas_addr;
  wire             clk_en;
  wire    [  3: 0] cmd_all;
  wire    [  2: 0] cmd_code;
  wire             cs_n;
  wire             csn_decode;
  wire             csn_match;
  wire    [ 21: 0] f_addr;
  wire    [  1: 0] f_bank;
  wire             f_cs_n;
  wire    [ 15: 0] f_data;
  wire    [  1: 0] f_dqm;
  wire             f_empty;
  reg              f_pop;
  wire             f_rnw;
  wire             f_select;
  wire    [ 40: 0] fifo_read_data;
  reg     [ 11: 0] i_addr;
  reg     [  3: 0] i_cmd;
  reg     [  2: 0] i_count;
  reg     [  2: 0] i_next;
  reg     [  2: 0] i_refs;
  reg     [  2: 0] i_state;
  reg              init_done;
  reg     [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg     [  1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg     [  3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg     [  2: 0] m_count;
  reg     [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON"  */;
  reg     [  1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg     [  8: 0] m_next;
  reg     [  8: 0] m_state;
  reg              oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON"  */;
  wire             pending;
  wire             rd_strobe;
  reg     [  2: 0] rd_valid;
  reg     [ 12: 0] refresh_counter;
  reg              refresh_request;
  wire             rnw_match;
  wire             row_match;
  wire    [ 23: 0] txt_code;
  reg              za_cannotrefresh;
  reg     [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON"  */;
  reg              za_valid;
  wire             za_waitrequest;
  wire    [ 11: 0] zs_addr;
  wire    [  1: 0] zs_ba;
  wire             zs_cas_n;
  wire             zs_cke;
  wire             zs_cs_n;
  wire    [ 15: 0] zs_dq;
  wire    [  1: 0] zs_dqm;
  wire             zs_ras_n;
  wire             zs_we_n;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
  assign zs_addr = m_addr;
  assign zs_cke = clk_en;
  assign zs_dq = oe?m_data:{16{1'bz}};
  assign zs_dqm = m_dqm;
  assign zs_ba = m_bank;
  assign f_select = f_pop & pending;
  assign f_cs_n = 1'b0;
  assign cs_n = f_select ? f_cs_n : active_cs_n;
  assign csn_decode = cs_n;
  assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
  sdram_1_input_efifo_module the_sdram_1_input_efifo_module
    (
      .almost_empty (almost_empty),
      .almost_full  (almost_full),
      .clk          (clk),
      .empty        (f_empty),
      .full         (za_waitrequest),
      .rd           (f_select),
      .rd_data      (fifo_read_data),
      .reset_n      (reset_n),
      .wr           ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
      .wr_data      ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
    );
 
  assign f_bank = {f_addr[21],f_addr[8]};
  // Refresh/init counter.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          refresh_counter <= 5000;
      else if (refresh_counter == 0)
          refresh_counter <= 781;
      else
        refresh_counter <= refresh_counter - 1'b1;
    end
 
 
  // Refresh request signal.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          refresh_request <= 0;
      else if (1)
          refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
    end
 
 
  // Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          za_cannotrefresh <= 0;
      else if (1)
          za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
    end
 
 
  // Initialization-done flag.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          init_done <= 0;
      else if (1)
          init_done <= init_done | (i_state == 3'b101);
    end
 
 
  // **** Init FSM ****
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          i_state <= 3'b000;
          i_next <= 3'b000;
          i_cmd <= 4'b1111;
          i_addr <= {12{1'b1}};
          i_count <= {3{1'b0}};
        end
      else
        begin
          i_addr <= {12{1'b1}};
          case (i_state) // synthesis parallel_case full_case
 
              3'b000: begin
                  i_cmd <= 4'b1111;
                  i_refs <= 3'b0;
                  //Wait for refresh count-down after reset
                  if (refresh_counter == 0)
                      i_state <= 3'b001;
              end // 3'b000 
 
              3'b001: begin
                  i_state <= 3'b011;
                  i_cmd <= {{1{1'b0}},3'h2};
                  i_count <= 0;
                  i_next <= 3'b010;
              end // 3'b001 
 
              3'b010: begin
                  i_cmd <= {{1{1'b0}},3'h1};
                  i_refs <= i_refs + 1'b1;
                  i_state <= 3'b011;
                  i_count <= 3;
                  // Count up init_refresh_commands
                  if (i_refs == 3'h1)
                      i_next <= 3'b111;
                  else
                    i_next <= 3'b010;
              end // 3'b010 
 
              3'b011: begin
                  i_cmd <= {{1{1'b0}},3'h7};
                  //WAIT til safe to Proceed...
                  if (i_count > 1)
                      i_count <= i_count - 1'b1;
                  else
                    i_state <= i_next;
              end // 3'b011 
 
              3'b101: begin
                  i_state <= 3'b101;
              end // 3'b101 
 
              3'b111: begin
                  i_state <= 3'b011;
                  i_cmd <= {{1{1'b0}},3'h0};
                  i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
                  i_count <= 4;
                  i_next <= 3'b101;
              end // 3'b111 
 
              default: begin
                  i_state <= 3'b000;
              end // default
 
          endcase // i_state
        end
    end
 
 
  assign active_bank = {active_addr[21],active_addr[8]};
  assign csn_match = active_cs_n == f_cs_n;
  assign rnw_match = active_rnw == f_rnw;
  assign bank_match = active_bank == f_bank;
  assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
  assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
  assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
  // **** Main FSM ****
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          m_state <= 9'b000000001;
          m_next <= 9'b000000001;
          m_cmd <= 4'b1111;
          m_bank <= 2'b00;
          m_addr <= 12'b000000000000;
          m_data <= 16'b0000000000000000;
          m_dqm <= 2'b00;
          m_count <= 3'b000;
          ack_refresh_request <= 1'b0;
          f_pop <= 1'b0;
          oe <= 1'b0;
        end
      else
        begin
          f_pop <= 1'b0;
          oe <= 1'b0;
          case (m_state) // synthesis parallel_case full_case
 
              9'b000000001: begin
                  //Wait for init-fsm to be done...
                  if (init_done)
                    begin
                      //Hold bus if another cycle ended to arf.
                      if (refresh_request)
                          m_cmd <= {{1{1'b0}},3'h7};
                      else
                        m_cmd <= 4'b1111;
                      ack_refresh_request <= 1'b0;
                      //Wait for a read/write request.
                      if (refresh_request)
                        begin
                          m_state <= 9'b001000000;
                          m_next <= 9'b010000000;
                          m_count <= 0;
                          active_cs_n <= 1'b1;
                        end
                      else if (!f_empty)
                        begin
                          f_pop <= 1'b1;
                          active_cs_n <= f_cs_n;
                          active_rnw <= f_rnw;
                          active_addr <= f_addr;
                          active_data <= f_data;
                          active_dqm <= f_dqm;
                          m_state <= 9'b000000010;
                        end
                    end
                  else
                    begin
                      m_addr <= i_addr;
                      m_state <= 9'b000000001;
                      m_next <= 9'b000000001;
                      m_cmd <= i_cmd;
                    end
              end // 9'b000000001 
 
              9'b000000010: begin
                  m_state <= 9'b000000100;
                  m_cmd <= {csn_decode,3'h3};
                  m_bank <= active_bank;
                  m_addr <= active_addr[20 : 9];
                  m_data <= active_data;
                  m_dqm <= active_dqm;
                  m_count <= 1;
                  m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
              end // 9'b000000010 
 
              9'b000000100: begin
                  // precharge all if arf, else precharge csn_decode
                  if (m_next == 9'b010000000)
                      m_cmd <= {{1{1'b0}},3'h7};
                  else
                    m_cmd <= {csn_decode,3'h7};
                  //Count down til safe to Proceed...
                  if (m_count > 1)
                      m_count <= m_count - 1'b1;
                  else
                    m_state <= m_next;
              end // 9'b000000100 
 
              9'b000001000: begin
                  m_cmd <= {csn_decode,3'h5};
                  m_bank <= f_select ? f_bank : active_bank;
                  m_dqm <= f_select ? f_dqm  : active_dqm;
                  m_addr <= cas_addr;
                  //Do we have a transaction pending?
                  if (pending)
                    begin
                      //if we need to ARF, bail, else spin
                      if (refresh_request)
                        begin
                          m_state <= 9'b000000100;
                          m_next <= 9'b000000001;
                          m_count <= 2;
                        end
                      else
                        begin
                          f_pop <= 1'b1;
                          active_cs_n <= f_cs_n;
                          active_rnw <= f_rnw;
                          active_addr <= f_addr;
                          active_data <= f_data;
                          active_dqm <= f_dqm;
                        end
                    end
                  else
                    begin
                      //correctly end RD spin cycle if fifo mt
                      if (~pending & f_pop)
                          m_cmd <= {csn_decode,3'h7};
                      m_state <= 9'b100000000;
                    end
              end // 9'b000001000 
 
              9'b000010000: begin
                  m_cmd <= {csn_decode,3'h4};
                  oe <= 1'b1;
                  m_data <= f_select ? f_data : active_data;
                  m_dqm <= f_select ? f_dqm  : active_dqm;
                  m_bank <= f_select ? f_bank : active_bank;
                  m_addr <= cas_addr;
                  //Do we have a transaction pending?
                  if (pending)
                    begin
                      //if we need to ARF, bail, else spin
                      if (refresh_request)
                        begin
                          m_state <= 9'b000000100;
                          m_next <= 9'b000000001;
                          m_count <= 1;
                        end
                      else
                        begin
                          f_pop <= 1'b1;
                          active_cs_n <= f_cs_n;
                          active_rnw <= f_rnw;
                          active_addr <= f_addr;
                          active_data <= f_data;
                          active_dqm <= f_dqm;
                        end
                    end
                  else
                    begin
                      //correctly end WR spin cycle if fifo empty
                      if (~pending & f_pop)
                        begin
                          m_cmd <= {csn_decode,3'h7};
                          oe <= 1'b0;
                        end
                      m_state <= 9'b100000000;
                    end
              end // 9'b000010000 
 
              9'b000100000: begin
                  m_cmd <= {csn_decode,3'h7};
                  //Count down til safe to Proceed...
                  if (m_count > 1)
                      m_count <= m_count - 1'b1;
                  else
                    begin
                      m_state <= 9'b001000000;
                      m_count <= 0;
                    end
              end // 9'b000100000 
 
              9'b001000000: begin
                  m_state <= 9'b000000100;
                  m_addr <= {12{1'b1}};
                  // precharge all if arf, else precharge csn_decode
                  if (refresh_request)
                      m_cmd <= {{1{1'b0}},3'h2};
                  else
                    m_cmd <= {csn_decode,3'h2};
              end // 9'b001000000 
 
              9'b010000000: begin
                  ack_refresh_request <= 1'b1;
                  m_state <= 9'b000000100;
                  m_cmd <= {{1{1'b0}},3'h1};
                  m_count <= 3;
                  m_next <= 9'b000000001;
              end // 9'b010000000 
 
              9'b100000000: begin
                  m_cmd <= {csn_decode,3'h7};
                  //if we need to ARF, bail, else spin
                  if (refresh_request)
                    begin
                      m_state <= 9'b000000100;
                      m_next <= 9'b000000001;
                      m_count <= 1;
                    end
                  else //wait for fifo to have contents
                  if (!f_empty)
                      //Are we 'pending' yet?
                      if (csn_match && rnw_match && bank_match && row_match)
                        begin
                          m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
                          f_pop <= 1'b1;
                          active_cs_n <= f_cs_n;
                          active_rnw <= f_rnw;
                          active_addr <= f_addr;
                          active_data <= f_data;
                          active_dqm <= f_dqm;
                        end
                      else
                        begin
                          m_state <= 9'b000100000;
                          m_next <= 9'b000000001;
                          m_count <= 1;
                        end
              end // 9'b100000000 
 
              // synthesis translate_off
 
              default: begin
                  m_state <= m_state;
                  m_cmd <= 4'b1111;
                  f_pop <= 1'b0;
                  oe <= 1'b0;
              end // default
 
              // synthesis translate_on
          endcase // m_state
        end
    end
 
 
  assign rd_strobe = m_cmd[2 : 0] == 3'h5;
  //Track RD Req's based on cas_latency w/shift reg
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          rd_valid <= {3{1'b0}};
      else
        rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
    end
 
 
  // Register dq data.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          za_data <= 0;
      else
        za_data <= zs_dq;
    end
 
 
  // Delay za_valid to match registered data.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          za_valid <= 0;
      else if (1)
          za_valid <= rd_valid[2];
    end
 
 
  assign cmd_code = m_cmd[2 : 0];
  assign cmd_all = m_cmd;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
  begin
    $write("\n");
    $write("This reference design requires a vendor simulation model.\n");
    $write("To simulate accesses to SDRAM, you must:\n");
    $write("     - Download the vendor model\n");
    $write("     - Install the model in the system_sim directory\n");
    $write("     - `include the vendor model in the the top-level system file,\n");
    $write("     - Instantiate sdram simulation models and wire them to testbench signals\n");
    $write("     - Be aware that you may have to disable some timing checks in the vendor model\n");
    $write("               (because this simulation is zero-delay based)\n");
    $write("\n");
  end
  assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
    (cmd_code == 3'h1)? 24'h415246 :
    (cmd_code == 3'h2)? 24'h505245 :
    (cmd_code == 3'h3)? 24'h414354 :
    (cmd_code == 3'h4)? 24'h205752 :
    (cmd_code == 3'h5)? 24'h205244 :
    (cmd_code == 3'h6)? 24'h425354 :
    (cmd_code == 3'h7)? 24'h4e4f50 :
    24'h424144;
 
  assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 

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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [hdl/] [sdram_1.v] - Blame information for rev 147

Line No.	Rev	Author	Line
1	147	lanttu	`//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`// synthesis translate_off`
14			`timescale 1ns / 1ps
15			`// synthesis translate_on`
16
17			`// turn off superfluous verilog processor warnings`
18			`// altera message_level Level1`
19			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
20
21			`module sdram_1_input_efifo_module (`
22			`// inputs:`
23			`clk,`
24			`rd,`
25			`reset_n,`
26			`wr,`
27			`wr_data,`
28
29			`// outputs:`
30			`almost_empty,`
31			`almost_full,`
32			`empty,`
33			`full,`
34			`rd_data`
35			`)`
36			`;`
37
38			`output almost_empty;`
39			`output almost_full;`
40			`output empty;`
41			`output full;`
42			`output [ 40: 0] rd_data;`
43			`input clk;`
44			`input rd;`
45			`input reset_n;`
46			`input wr;`
47			`input [ 40: 0] wr_data;`
48
49			`wire almost_empty;`
50			`wire almost_full;`
51			`wire empty;`
52			`reg [ 1: 0] entries;`
53			`reg [ 40: 0] entry_0;`
54			`reg [ 40: 0] entry_1;`
55			`wire full;`
56			`reg rd_address;`
57			`reg [ 40: 0] rd_data;`
58			`wire [ 1: 0] rdwr;`
59			`reg wr_address;`
60			`assign rdwr = {rd, wr};`
61			`assign full = entries == 2;`
62			`assign almost_full = entries >= 1;`
63			`assign empty = entries == 0;`
64			`assign almost_empty = entries <= 1;`
65			`always @(entry_0 or entry_1 or rd_address)`
66			`begin`
67			`case (rd_address) // synthesis parallel_case full_case`
68
69			`1'd0: begin`
70			`rd_data = entry_0;`
71			`end // 1'd0`
72
73			`1'd1: begin`
74			`rd_data = entry_1;`
75			`end // 1'd1`
76
77			`default: begin`
78			`end // default`
79
80			`endcase // rd_address`
81			`end`
82
83
84			`always @(posedge clk or negedge reset_n)`
85			`begin`
86			`if (reset_n == 0)`
87			`begin`
88			`wr_address <= 0;`
89			`rd_address <= 0;`
90			`entries <= 0;`
91			`end`
92			`else`
93			`case (rdwr) // synthesis parallel_case full_case`
94
95			`2'd1: begin`
96			`// Write data`
97			`if (!full)`
98			`begin`
99			`entries <= entries + 1;`
100			`wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);`
101			`end`
102			`end // 2'd1`
103
104			`2'd2: begin`
105			`// Read data`
106			`if (!empty)`
107			`begin`
108			`entries <= entries - 1;`
109			`rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);`
110			`end`
111			`end // 2'd2`
112
113			`2'd3: begin`
114			`wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);`
115			`rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);`
116			`end // 2'd3`
117
118			`default: begin`
119			`end // default`
120
121			`endcase // rdwr`
122			`end`
123
124
125			`always @(posedge clk)`
126			`begin`
127			`//Write data`
128			`if (wr & !full)`
129			`case (wr_address) // synthesis parallel_case full_case`
130
131			`1'd0: begin`
132			`entry_0 <= wr_data;`
133			`end // 1'd0`
134
135			`1'd1: begin`
136			`entry_1 <= wr_data;`
137			`end // 1'd1`
138
139			`default: begin`
140			`end // default`
141
142			`endcase // wr_address`
143			`end`
144
145
146
147			`endmodule`
148
149
150			`// synthesis translate_off`
151			`timescale 1ns / 1ps
152			`// synthesis translate_on`
153
154			`// turn off superfluous verilog processor warnings`
155			`// altera message_level Level1`
156			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
157
158			`module sdram_1 (`
159			`// inputs:`
160			`az_addr,`
161			`az_be_n,`
162			`az_cs,`
163			`az_data,`
164			`az_rd_n,`
165			`az_wr_n,`
166			`clk,`
167			`reset_n,`
168
169			`// outputs:`
170			`za_data,`
171			`za_valid,`
172			`za_waitrequest,`
173			`zs_addr,`
174			`zs_ba,`
175			`zs_cas_n,`
176			`zs_cke,`
177			`zs_cs_n,`
178			`zs_dq,`
179			`zs_dqm,`
180			`zs_ras_n,`
181			`zs_we_n`
182			`)`
183			`;`
184
185			`output [ 15: 0] za_data;`
186			`output za_valid;`
187			`output za_waitrequest;`
188			`output [ 11: 0] zs_addr;`
189			`output [ 1: 0] zs_ba;`
190			`output zs_cas_n;`
191			`output zs_cke;`
192			`output zs_cs_n;`
193			`inout [ 15: 0] zs_dq;`
194			`output [ 1: 0] zs_dqm;`
195			`output zs_ras_n;`
196			`output zs_we_n;`
197			`input [ 21: 0] az_addr;`
198			`input [ 1: 0] az_be_n;`
199			`input az_cs;`
200			`input [ 15: 0] az_data;`
201			`input az_rd_n;`
202			`input az_wr_n;`
203			`input clk;`
204			`input reset_n;`
205
206			`wire [ 23: 0] CODE;`
207			`reg ack_refresh_request;`
208			`reg [ 21: 0] active_addr;`
209			`wire [ 1: 0] active_bank;`
210			`reg active_cs_n;`
211			`reg [ 15: 0] active_data;`
212			`reg [ 1: 0] active_dqm;`
213			`reg active_rnw;`
214			`wire almost_empty;`
215			`wire almost_full;`
216			`wire bank_match;`
217			`wire [ 7: 0] cas_addr;`
218			`wire clk_en;`
219			`wire [ 3: 0] cmd_all;`
220			`wire [ 2: 0] cmd_code;`
221			`wire cs_n;`
222			`wire csn_decode;`
223			`wire csn_match;`
224			`wire [ 21: 0] f_addr;`
225			`wire [ 1: 0] f_bank;`
226			`wire f_cs_n;`
227			`wire [ 15: 0] f_data;`
228			`wire [ 1: 0] f_dqm;`
229			`wire f_empty;`
230			`reg f_pop;`
231			`wire f_rnw;`
232			`wire f_select;`
233			`wire [ 40: 0] fifo_read_data;`
234			`reg [ 11: 0] i_addr;`
235			`reg [ 3: 0] i_cmd;`
236			`reg [ 2: 0] i_count;`
237			`reg [ 2: 0] i_next;`
238			`reg [ 2: 0] i_refs;`
239			`reg [ 2: 0] i_state;`
240			`reg init_done;`
241			`reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;`
242			`reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;`
243			`reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;`
244			`reg [ 2: 0] m_count;`
245			`reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;`
246			`reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;`
247			`reg [ 8: 0] m_next;`
248			`reg [ 8: 0] m_state;`
249			`reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;`
250			`wire pending;`
251			`wire rd_strobe;`
252			`reg [ 2: 0] rd_valid;`
253			`reg [ 12: 0] refresh_counter;`
254			`reg refresh_request;`
255			`wire rnw_match;`
256			`wire row_match;`
257			`wire [ 23: 0] txt_code;`
258			`reg za_cannotrefresh;`
259			`reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;`
260			`reg za_valid;`
261			`wire za_waitrequest;`
262			`wire [ 11: 0] zs_addr;`
263			`wire [ 1: 0] zs_ba;`
264			`wire zs_cas_n;`
265			`wire zs_cke;`
266			`wire zs_cs_n;`
267			`wire [ 15: 0] zs_dq;`
268			`wire [ 1: 0] zs_dqm;`
269			`wire zs_ras_n;`
270			`wire zs_we_n;`
271			`assign clk_en = 1;`
272			`//s1, which is an e_avalon_slave`
273			`assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;`
274			`assign zs_addr = m_addr;`
275			`assign zs_cke = clk_en;`
276			`assign zs_dq = oe?m_data:{16{1'bz}};`
277			`assign zs_dqm = m_dqm;`
278			`assign zs_ba = m_bank;`
279			`assign f_select = f_pop & pending;`
280			`assign f_cs_n = 1'b0;`
281			`assign cs_n = f_select ? f_cs_n : active_cs_n;`
282			`assign csn_decode = cs_n;`
283			`assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;`
284			`sdram_1_input_efifo_module the_sdram_1_input_efifo_module`
285			`(`
286			`.almost_empty (almost_empty),`
287			`.almost_full (almost_full),`
288			`.clk (clk),`
289			`.empty (f_empty),`
290			`.full (za_waitrequest),`
291			`.rd (f_select),`
292			`.rd_data (fifo_read_data),`
293			`.reset_n (reset_n),`
294			`.wr ((~az_wr_n \| ~az_rd_n) & !za_waitrequest),`
295			`.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})`
296			`);`
297
298			`assign f_bank = {f_addr[21],f_addr[8]};`
299			`// Refresh/init counter.`
300			`always @(posedge clk or negedge reset_n)`
301			`begin`
302			`if (reset_n == 0)`
303			`refresh_counter <= 5000;`
304			`else if (refresh_counter == 0)`
305			`refresh_counter <= 781;`
306			`else`
307			`refresh_counter <= refresh_counter - 1'b1;`
308			`end`
309
310
311			`// Refresh request signal.`
312			`always @(posedge clk or negedge reset_n)`
313			`begin`
314			`if (reset_n == 0)`
315			`refresh_request <= 0;`
316			`else if (1)`
317			`refresh_request <= ((refresh_counter == 0) \| refresh_request) & ~ack_refresh_request & init_done;`
318			`end`
319
320
321			`// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request`
322			`always @(posedge clk or negedge reset_n)`
323			`begin`
324			`if (reset_n == 0)`
325			`za_cannotrefresh <= 0;`
326			`else if (1)`
327			`za_cannotrefresh <= (refresh_counter == 0) & refresh_request;`
328			`end`
329
330
331			`// Initialization-done flag.`
332			`always @(posedge clk or negedge reset_n)`
333			`begin`
334			`if (reset_n == 0)`
335			`init_done <= 0;`
336			`else if (1)`
337			`init_done <= init_done \| (i_state == 3'b101);`
338			`end`
339
340
341			`// ** Init FSM **`
342			`always @(posedge clk or negedge reset_n)`
343			`begin`
344			`if (reset_n == 0)`
345			`begin`
346			`i_state <= 3'b000;`
347			`i_next <= 3'b000;`
348			`i_cmd <= 4'b1111;`
349			`i_addr <= {12{1'b1}};`
350			`i_count <= {3{1'b0}};`
351			`end`
352			`else`
353			`begin`
354			`i_addr <= {12{1'b1}};`
355			`case (i_state) // synthesis parallel_case full_case`
356
357			`3'b000: begin`
358			`i_cmd <= 4'b1111;`
359			`i_refs <= 3'b0;`
360			`//Wait for refresh count-down after reset`
361			`if (refresh_counter == 0)`
362			`i_state <= 3'b001;`
363			`end // 3'b000`
364
365			`3'b001: begin`
366			`i_state <= 3'b011;`
367			`i_cmd <= {{1{1'b0}},3'h2};`
368			`i_count <= 0;`
369			`i_next <= 3'b010;`
370			`end // 3'b001`
371
372			`3'b010: begin`
373			`i_cmd <= {{1{1'b0}},3'h1};`
374			`i_refs <= i_refs + 1'b1;`
375			`i_state <= 3'b011;`
376			`i_count <= 3;`
377			`// Count up init_refresh_commands`
378			`if (i_refs == 3'h1)`
379			`i_next <= 3'b111;`
380			`else`
381			`i_next <= 3'b010;`
382			`end // 3'b010`
383
384			`3'b011: begin`
385			`i_cmd <= {{1{1'b0}},3'h7};`
386			`//WAIT til safe to Proceed...`
387			`if (i_count > 1)`
388			`i_count <= i_count - 1'b1;`
389			`else`
390			`i_state <= i_next;`
391			`end // 3'b011`
392
393			`3'b101: begin`
394			`i_state <= 3'b101;`
395			`end // 3'b101`
396
397			`3'b111: begin`
398			`i_state <= 3'b011;`
399			`i_cmd <= {{1{1'b0}},3'h0};`
400			`i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};`
401			`i_count <= 4;`
402			`i_next <= 3'b101;`
403			`end // 3'b111`
404
405			`default: begin`
406			`i_state <= 3'b000;`
407			`end // default`
408
409			`endcase // i_state`
410			`end`
411			`end`
412
413
414			`assign active_bank = {active_addr[21],active_addr[8]};`
415			`assign csn_match = active_cs_n == f_cs_n;`
416			`assign rnw_match = active_rnw == f_rnw;`
417			`assign bank_match = active_bank == f_bank;`
418			`assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};`
419			`assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;`
420			`assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };`
421			`// ** Main FSM **`
422			`always @(posedge clk or negedge reset_n)`
423			`begin`
424			`if (reset_n == 0)`
425			`begin`
426			`m_state <= 9'b000000001;`
427			`m_next <= 9'b000000001;`
428			`m_cmd <= 4'b1111;`
429			`m_bank <= 2'b00;`
430			`m_addr <= 12'b000000000000;`
431			`m_data <= 16'b0000000000000000;`
432			`m_dqm <= 2'b00;`
433			`m_count <= 3'b000;`
434			`ack_refresh_request <= 1'b0;`
435			`f_pop <= 1'b0;`
436			`oe <= 1'b0;`
437			`end`
438			`else`
439			`begin`
440			`f_pop <= 1'b0;`
441			`oe <= 1'b0;`
442			`case (m_state) // synthesis parallel_case full_case`
443
444			`9'b000000001: begin`
445			`//Wait for init-fsm to be done...`
446			`if (init_done)`
447			`begin`
448			`//Hold bus if another cycle ended to arf.`
449			`if (refresh_request)`
450			`m_cmd <= {{1{1'b0}},3'h7};`
451			`else`
452			`m_cmd <= 4'b1111;`
453			`ack_refresh_request <= 1'b0;`
454			`//Wait for a read/write request.`
455			`if (refresh_request)`
456			`begin`
457			`m_state <= 9'b001000000;`
458			`m_next <= 9'b010000000;`
459			`m_count <= 0;`
460			`active_cs_n <= 1'b1;`
461			`end`
462			`else if (!f_empty)`
463			`begin`
464			`f_pop <= 1'b1;`
465			`active_cs_n <= f_cs_n;`
466			`active_rnw <= f_rnw;`
467			`active_addr <= f_addr;`
468			`active_data <= f_data;`
469			`active_dqm <= f_dqm;`
470			`m_state <= 9'b000000010;`
471			`end`
472			`end`
473			`else`
474			`begin`
475			`m_addr <= i_addr;`
476			`m_state <= 9'b000000001;`
477			`m_next <= 9'b000000001;`
478			`m_cmd <= i_cmd;`
479			`end`
480			`end // 9'b000000001`
481
482			`9'b000000010: begin`
483			`m_state <= 9'b000000100;`
484			`m_cmd <= {csn_decode,3'h3};`
485			`m_bank <= active_bank;`
486			`m_addr <= active_addr[20 : 9];`
487			`m_data <= active_data;`
488			`m_dqm <= active_dqm;`
489			`m_count <= 1;`
490			`m_next <= active_rnw ? 9'b000001000 : 9'b000010000;`
491			`end // 9'b000000010`
492
493			`9'b000000100: begin`
494			`// precharge all if arf, else precharge csn_decode`
495			`if (m_next == 9'b010000000)`
496			`m_cmd <= {{1{1'b0}},3'h7};`
497			`else`
498			`m_cmd <= {csn_decode,3'h7};`
499			`//Count down til safe to Proceed...`
500			`if (m_count > 1)`
501			`m_count <= m_count - 1'b1;`
502			`else`
503			`m_state <= m_next;`
504			`end // 9'b000000100`
505
506			`9'b000001000: begin`
507			`m_cmd <= {csn_decode,3'h5};`
508			`m_bank <= f_select ? f_bank : active_bank;`
509			`m_dqm <= f_select ? f_dqm : active_dqm;`
510			`m_addr <= cas_addr;`
511			`//Do we have a transaction pending?`
512			`if (pending)`
513			`begin`
514			`//if we need to ARF, bail, else spin`
515			`if (refresh_request)`
516			`begin`
517			`m_state <= 9'b000000100;`
518			`m_next <= 9'b000000001;`
519			`m_count <= 2;`
520			`end`
521			`else`
522			`begin`
523			`f_pop <= 1'b1;`
524			`active_cs_n <= f_cs_n;`
525			`active_rnw <= f_rnw;`
526			`active_addr <= f_addr;`
527			`active_data <= f_data;`
528			`active_dqm <= f_dqm;`
529			`end`
530			`end`
531			`else`
532			`begin`
533			`//correctly end RD spin cycle if fifo mt`
534			`if (~pending & f_pop)`
535			`m_cmd <= {csn_decode,3'h7};`
536			`m_state <= 9'b100000000;`
537			`end`
538			`end // 9'b000001000`
539
540			`9'b000010000: begin`
541			`m_cmd <= {csn_decode,3'h4};`
542			`oe <= 1'b1;`
543			`m_data <= f_select ? f_data : active_data;`
544			`m_dqm <= f_select ? f_dqm : active_dqm;`
545			`m_bank <= f_select ? f_bank : active_bank;`
546			`m_addr <= cas_addr;`
547			`//Do we have a transaction pending?`
548			`if (pending)`
549			`begin`
550			`//if we need to ARF, bail, else spin`
551			`if (refresh_request)`
552			`begin`
553			`m_state <= 9'b000000100;`
554			`m_next <= 9'b000000001;`
555			`m_count <= 1;`
556			`end`
557			`else`
558			`begin`
559			`f_pop <= 1'b1;`
560			`active_cs_n <= f_cs_n;`
561			`active_rnw <= f_rnw;`
562			`active_addr <= f_addr;`
563			`active_data <= f_data;`
564			`active_dqm <= f_dqm;`
565			`end`
566			`end`
567			`else`
568			`begin`
569			`//correctly end WR spin cycle if fifo empty`
570			`if (~pending & f_pop)`
571			`begin`
572			`m_cmd <= {csn_decode,3'h7};`
573			`oe <= 1'b0;`
574			`end`
575			`m_state <= 9'b100000000;`
576			`end`
577			`end // 9'b000010000`
578
579			`9'b000100000: begin`
580			`m_cmd <= {csn_decode,3'h7};`
581			`//Count down til safe to Proceed...`
582			`if (m_count > 1)`
583			`m_count <= m_count - 1'b1;`
584			`else`
585			`begin`
586			`m_state <= 9'b001000000;`
587			`m_count <= 0;`
588			`end`
589			`end // 9'b000100000`
590
591			`9'b001000000: begin`
592			`m_state <= 9'b000000100;`
593			`m_addr <= {12{1'b1}};`
594			`// precharge all if arf, else precharge csn_decode`
595			`if (refresh_request)`
596			`m_cmd <= {{1{1'b0}},3'h2};`
597			`else`
598			`m_cmd <= {csn_decode,3'h2};`
599			`end // 9'b001000000`
600
601			`9'b010000000: begin`
602			`ack_refresh_request <= 1'b1;`
603			`m_state <= 9'b000000100;`
604			`m_cmd <= {{1{1'b0}},3'h1};`
605			`m_count <= 3;`
606			`m_next <= 9'b000000001;`
607			`end // 9'b010000000`
608
609			`9'b100000000: begin`
610			`m_cmd <= {csn_decode,3'h7};`
611			`//if we need to ARF, bail, else spin`
612			`if (refresh_request)`
613			`begin`
614			`m_state <= 9'b000000100;`
615			`m_next <= 9'b000000001;`
616			`m_count <= 1;`
617			`end`
618			`else //wait for fifo to have contents`
619			`if (!f_empty)`
620			`//Are we 'pending' yet?`
621			`if (csn_match && rnw_match && bank_match && row_match)`
622			`begin`
623			`m_state <= f_rnw ? 9'b000001000 : 9'b000010000;`
624			`f_pop <= 1'b1;`
625			`active_cs_n <= f_cs_n;`
626			`active_rnw <= f_rnw;`
627			`active_addr <= f_addr;`
628			`active_data <= f_data;`
629			`active_dqm <= f_dqm;`
630			`end`
631			`else`
632			`begin`
633			`m_state <= 9'b000100000;`
634			`m_next <= 9'b000000001;`
635			`m_count <= 1;`
636			`end`
637			`end // 9'b100000000`
638
639			`// synthesis translate_off`
640
641			`default: begin`
642			`m_state <= m_state;`
643			`m_cmd <= 4'b1111;`
644			`f_pop <= 1'b0;`
645			`oe <= 1'b0;`
646			`end // default`
647
648			`// synthesis translate_on`
649			`endcase // m_state`
650			`end`
651			`end`
652
653
654			`assign rd_strobe = m_cmd[2 : 0] == 3'h5;`
655			`//Track RD Req's based on cas_latency w/shift reg`
656			`always @(posedge clk or negedge reset_n)`
657			`begin`
658			`if (reset_n == 0)`
659			`rd_valid <= {3{1'b0}};`
660			`else`
661			`rd_valid <= (rd_valid << 1) \| { {2{1'b0}}, rd_strobe };`
662			`end`
663
664
665			`// Register dq data.`
666			`always @(posedge clk or negedge reset_n)`
667			`begin`
668			`if (reset_n == 0)`
669			`za_data <= 0;`
670			`else`
671			`za_data <= zs_dq;`
672			`end`
673
674
675			`// Delay za_valid to match registered data.`
676			`always @(posedge clk or negedge reset_n)`
677			`begin`
678			`if (reset_n == 0)`
679			`za_valid <= 0;`
680			`else if (1)`
681			`za_valid <= rd_valid[2];`
682			`end`
683
684
685			`assign cmd_code = m_cmd[2 : 0];`
686			`assign cmd_all = m_cmd;`
687
688			`//synthesis translate_off`
689			`//////////////// SIMULATION-ONLY CONTENTS`
690			`initial`
691			`begin`
692			`$write("\n");`
693			`$write("This reference design requires a vendor simulation model.\n");`
694			`$write("To simulate accesses to SDRAM, you must:\n");`
695			`$write(" - Download the vendor model\n");`
696			`$write(" - Install the model in the system_sim directory\n");`
697			$write(" - `include the vendor model in the the top-level system file,\n");
698			`$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");`
699			`$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");`
700			`$write(" (because this simulation is zero-delay based)\n");`
701			`$write("\n");`
702			`end`
703			`assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :`
704			`(cmd_code == 3'h1)? 24'h415246 :`
705			`(cmd_code == 3'h2)? 24'h505245 :`
706			`(cmd_code == 3'h3)? 24'h414354 :`
707			`(cmd_code == 3'h4)? 24'h205752 :`
708			`(cmd_code == 3'h5)? 24'h205244 :`
709			`(cmd_code == 3'h6)? 24'h425354 :`
710			`(cmd_code == 3'h7)? 24'h4e4f50 :`
711			`24'h424144;`
712
713			`assign CODE = &(cmd_all\|4'h7) ? 24'h494e48 : txt_code;`
714
715			`//////////////// END SIMULATION-ONLY CONTENTS`
716
717			`//synthesis translate_on`
718
719			`endmodule`
720