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lanttu |
// nios2_sram.v
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// Generated using ACDS version 12.1 177 at 2013.06.11.15:57:38
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`timescale 1 ps / 1 ps
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module nios2_sram (
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input wire [31:0] hibi_pe_dma_data_in, // hibi_pe_dma.data_in
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input wire hibi_pe_dma_av_in, // .av_in
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input wire hibi_pe_dma_empty_in, // .empty_in
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input wire [4:0] hibi_pe_dma_comm_in, // .comm_in
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output wire hibi_pe_dma_re_out, // .re_out
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output wire [31:0] hibi_pe_dma_data_out, // .data_out
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output wire hibi_pe_dma_av_out, // .av_out
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input wire hibi_pe_dma_full_in, // .full_in
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output wire [4:0] hibi_pe_dma_comm_out, // .comm_out
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output wire hibi_pe_dma_we_out, // .we_out
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inout wire [15:0] sram_DQ, // sram.DQ
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output wire [17:0] sram_ADDR, // .ADDR
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output wire sram_LB_N, // .LB_N
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output wire sram_UB_N, // .UB_N
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output wire sram_CE_N, // .CE_N
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output wire sram_OE_N, // .OE_N
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output wire sram_WE_N, // .WE_N
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input wire reset_reset_n, // reset.reset_n
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input wire clk_clk // clk.clk
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);
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wire nios2_qsys_0_instruction_master_waitrequest; // nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
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wire [20:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
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wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
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wire [31:0] nios2_qsys_0_instruction_master_readdata; // nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
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wire nios2_qsys_0_instruction_master_readdatavalid; // nios2_qsys_0_instruction_master_translator:av_readdatavalid -> nios2_qsys_0:i_readdatavalid
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wire nios2_qsys_0_data_master_waitrequest; // nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
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wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
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wire [20:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
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wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
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wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
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wire [31:0] nios2_qsys_0_data_master_readdata; // nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
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wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
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wire nios2_qsys_0_data_master_readdatavalid; // nios2_qsys_0_data_master_translator:av_readdatavalid -> nios2_qsys_0:d_readdatavalid
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wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
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wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
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wire [8:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // nios2_qsys_0_jtag_debug_module_translator:av_chipselect -> nios2_qsys_0:jtag_debug_module_select
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
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wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // nios2_qsys_0_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_0:jtag_debug_module_begintransfer
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
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wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
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wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata; // sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
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wire [17:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address; // sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
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wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write; // sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
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wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read; // sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
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wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata; // sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
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wire [1:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable; // sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
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wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
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wire [10:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_address; // onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
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wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
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wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken; // onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
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wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_write; // onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
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wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
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wire [3:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
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wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
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wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n
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wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
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wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata
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wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address
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wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect
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wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n
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wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata
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wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
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wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest; // hibi_pe_dma_0:avalon_cfg_waitrequest_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_waitrequest
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wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator:av_writedata -> hibi_pe_dma_0:avalon_cfg_writedata_in
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wire [6:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address; // hibi_pe_dma_0_avalon_slave_0_translator:av_address -> hibi_pe_dma_0:avalon_cfg_addr_in
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect; // hibi_pe_dma_0_avalon_slave_0_translator:av_chipselect -> hibi_pe_dma_0:avalon_cfg_cs_in
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write; // hibi_pe_dma_0_avalon_slave_0_translator:av_write -> hibi_pe_dma_0:avalon_cfg_we_in
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // hibi_pe_dma_0_avalon_slave_0_translator:av_read -> hibi_pe_dma_0:avalon_cfg_re_in
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wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // hibi_pe_dma_0:avalon_cfg_readdata_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_readdata
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wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_writedata; // timer_1_s1_translator:av_writedata -> timer_1:writedata
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wire [2:0] timer_1_s1_translator_avalon_anti_slave_0_address; // timer_1_s1_translator:av_address -> timer_1:address
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wire timer_1_s1_translator_avalon_anti_slave_0_chipselect; // timer_1_s1_translator:av_chipselect -> timer_1:chipselect
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wire timer_1_s1_translator_avalon_anti_slave_0_write; // timer_1_s1_translator:av_write -> timer_1:write_n
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wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_readdata; // timer_1:readdata -> timer_1_s1_translator:av_readdata
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wire hibi_pe_dma_0_avalon_master_waitrequest; // hibi_pe_dma_0_avalon_master_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_rx
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wire [31:0] hibi_pe_dma_0_avalon_master_writedata; // hibi_pe_dma_0:avalon_writedata_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_writedata
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wire [31:0] hibi_pe_dma_0_avalon_master_address; // hibi_pe_dma_0:avalon_addr_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_address
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wire hibi_pe_dma_0_avalon_master_write; // hibi_pe_dma_0:avalon_we_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_write
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wire [3:0] hibi_pe_dma_0_avalon_master_byteenable; // hibi_pe_dma_0:avalon_be_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_byteenable
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wire hibi_pe_dma_0_avalon_master_1_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_tx
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wire [31:0] hibi_pe_dma_0_avalon_master_1_address; // hibi_pe_dma_0:avalon_addr_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_address
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wire hibi_pe_dma_0_avalon_master_1_read; // hibi_pe_dma_0:avalon_re_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_read
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wire [31:0] hibi_pe_dma_0_avalon_master_1_readdata; // hibi_pe_dma_0_avalon_master_1_translator:av_readdata -> hibi_pe_dma_0:avalon_readdata_in_tx
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wire hibi_pe_dma_0_avalon_master_1_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator:av_readdatavalid -> hibi_pe_dma_0:avalon_readdatavalid_in_tx
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wire [31:0] onchip_memory2_0_s2_translator_avalon_anti_slave_0_writedata; // onchip_memory2_0_s2_translator:av_writedata -> onchip_memory2_0:writedata2
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wire [10:0] onchip_memory2_0_s2_translator_avalon_anti_slave_0_address; // onchip_memory2_0_s2_translator:av_address -> onchip_memory2_0:address2
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wire onchip_memory2_0_s2_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_0_s2_translator:av_chipselect -> onchip_memory2_0:chipselect2
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wire onchip_memory2_0_s2_translator_avalon_anti_slave_0_clken; // onchip_memory2_0_s2_translator:av_clken -> onchip_memory2_0:clken2
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wire onchip_memory2_0_s2_translator_avalon_anti_slave_0_write; // onchip_memory2_0_s2_translator:av_write -> onchip_memory2_0:write2
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wire [31:0] onchip_memory2_0_s2_translator_avalon_anti_slave_0_readdata; // onchip_memory2_0:readdata2 -> onchip_memory2_0_s2_translator:av_readdata
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wire [3:0] onchip_memory2_0_s2_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_0_s2_translator:av_byteenable -> onchip_memory2_0:byteenable2
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
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wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
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wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
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wire [20:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
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wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
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wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
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wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
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wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
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wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
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120 |
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wire [20:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
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121 |
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
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122 |
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
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123 |
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
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124 |
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wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
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125 |
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
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126 |
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wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
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127 |
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wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
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128 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
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129 |
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wire [2:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
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130 |
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wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
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131 |
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wire [20:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
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132 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
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133 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
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134 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
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135 |
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wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
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136 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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137 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
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138 |
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wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
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139 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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140 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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141 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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142 |
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wire [94:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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143 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
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144 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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145 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
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146 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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147 |
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wire [94:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
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148 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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149 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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150 |
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wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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151 |
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wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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152 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
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153 |
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wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
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154 |
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wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
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155 |
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wire [20:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
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156 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
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157 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
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158 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
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159 |
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wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
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160 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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161 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
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162 |
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wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
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163 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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164 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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165 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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166 |
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wire [76:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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167 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
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168 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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169 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
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170 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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171 |
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wire [76:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
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172 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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173 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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174 |
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wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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175 |
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wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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176 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
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177 |
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wire [2:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
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178 |
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wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
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179 |
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wire [20:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
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180 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
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181 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
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182 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
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183 |
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wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
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184 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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185 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
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186 |
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wire [3:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
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187 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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188 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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189 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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190 |
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wire [94:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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191 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
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192 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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193 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
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194 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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195 |
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wire [94:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
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196 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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197 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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198 |
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wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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199 |
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wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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200 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
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201 |
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wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
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202 |
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wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
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203 |
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wire [20:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
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204 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
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205 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
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206 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
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207 |
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wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
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208 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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209 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
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210 |
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wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
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211 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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212 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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213 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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214 |
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wire [94:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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215 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
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216 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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217 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
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218 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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219 |
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wire [94:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
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220 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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221 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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222 |
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wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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223 |
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wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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224 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
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225 |
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wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
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226 |
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wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
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227 |
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wire [20:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
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228 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
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229 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
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230 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
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231 |
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wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
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232 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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233 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
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234 |
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wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
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235 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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236 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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237 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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238 |
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wire [94:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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239 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
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240 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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241 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
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242 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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243 |
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wire [94:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
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244 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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245 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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246 |
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wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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247 |
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wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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248 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
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249 |
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wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
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250 |
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wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
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251 |
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wire [20:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
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252 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
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253 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
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254 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
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255 |
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wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
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256 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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257 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
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258 |
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wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
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259 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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260 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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261 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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262 |
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wire [94:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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263 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
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264 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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265 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
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266 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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267 |
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wire [94:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
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268 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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269 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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270 |
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wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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271 |
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wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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272 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hibi_pe_dma_0_avalon_slave_0_translator:uav_waitrequest -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
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273 |
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wire [2:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hibi_pe_dma_0_avalon_slave_0_translator:uav_burstcount
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274 |
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wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hibi_pe_dma_0_avalon_slave_0_translator:uav_writedata
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275 |
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wire [20:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hibi_pe_dma_0_avalon_slave_0_translator:uav_address
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276 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hibi_pe_dma_0_avalon_slave_0_translator:uav_write
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277 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hibi_pe_dma_0_avalon_slave_0_translator:uav_lock
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278 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hibi_pe_dma_0_avalon_slave_0_translator:uav_read
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279 |
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wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdata -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
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280 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdatavalid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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281 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hibi_pe_dma_0_avalon_slave_0_translator:uav_debugaccess
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282 |
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wire [3:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hibi_pe_dma_0_avalon_slave_0_translator:uav_byteenable
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283 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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284 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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285 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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286 |
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wire [94:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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287 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
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288 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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289 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
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290 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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291 |
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wire [94:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
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292 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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293 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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294 |
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wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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295 |
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wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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296 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_1_s1_translator:uav_waitrequest -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
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297 |
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wire [2:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_1_s1_translator:uav_burstcount
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298 |
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wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_1_s1_translator:uav_writedata
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299 |
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wire [20:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_1_s1_translator:uav_address
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300 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_1_s1_translator:uav_write
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301 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_1_s1_translator:uav_lock
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302 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_1_s1_translator:uav_read
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303 |
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wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_1_s1_translator:uav_readdata -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
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304 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_1_s1_translator:uav_readdatavalid -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
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305 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_1_s1_translator:uav_debugaccess
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306 |
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wire [3:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_1_s1_translator:uav_byteenable
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307 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
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308 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
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309 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
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310 |
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wire [94:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
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311 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
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312 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
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313 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
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314 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
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315 |
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wire [94:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
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316 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
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317 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
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318 |
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wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
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319 |
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wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
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320 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_translator:uav_waitrequest
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321 |
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wire [2:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
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322 |
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wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
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323 |
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wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_translator:uav_address -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
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324 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_translator:uav_lock -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
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325 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_translator:uav_write -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
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326 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_translator:uav_read -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
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327 |
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wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_translator:uav_readdata
|
328 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
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329 |
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wire [3:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
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330 |
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wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_translator:uav_readdatavalid
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331 |
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_1_translator:uav_waitrequest
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332 |
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wire [2:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_1_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_burstcount
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333 |
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wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_1_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_writedata
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334 |
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wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_1_translator:uav_address -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_address
|
335 |
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_1_translator:uav_lock -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_lock
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336 |
|
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_1_translator:uav_write -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_write
|
337 |
|
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_1_translator:uav_read -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_read
|
338 |
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wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdata
|
339 |
|
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_1_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_debugaccess
|
340 |
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wire [3:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_1_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_byteenable
|
341 |
|
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wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdatavalid
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342 |
|
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wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_0_s2_translator:uav_waitrequest -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_waitrequest
|
343 |
|
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wire [2:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s2_translator:uav_burstcount
|
344 |
|
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wire [31:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s2_translator:uav_writedata
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345 |
|
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wire [31:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s2_translator:uav_address
|
346 |
|
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wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s2_translator:uav_write
|
347 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s2_translator:uav_lock
|
348 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s2_translator:uav_read
|
349 |
|
|
wire [31:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_0_s2_translator:uav_readdata -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_readdata
|
350 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_0_s2_translator:uav_readdatavalid -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_readdatavalid
|
351 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s2_translator:uav_debugaccess
|
352 |
|
|
wire [3:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s2_translator:uav_byteenable
|
353 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
|
354 |
|
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wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
|
355 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
|
356 |
|
|
wire [101:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
|
357 |
|
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wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_source_ready
|
358 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
|
359 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_sink_valid
|
360 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
|
361 |
|
|
wire [101:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_sink_data
|
362 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
|
363 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
|
364 |
|
|
wire [31:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
|
365 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
|
366 |
|
|
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
|
367 |
|
|
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
|
368 |
|
|
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
|
369 |
|
|
wire [93:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
|
370 |
|
|
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
|
371 |
|
|
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
|
372 |
|
|
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
|
373 |
|
|
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
|
374 |
|
|
wire [93:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
|
375 |
|
|
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
|
376 |
|
|
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
|
377 |
|
|
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
|
378 |
|
|
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
|
379 |
|
|
wire [93:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
|
380 |
|
|
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
|
381 |
|
|
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
|
382 |
|
|
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
|
383 |
|
|
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
|
384 |
|
|
wire [75:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
|
385 |
|
|
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
|
386 |
|
|
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
|
387 |
|
|
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
|
388 |
|
|
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
|
389 |
|
|
wire [93:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
|
390 |
|
|
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
|
391 |
|
|
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
|
392 |
|
|
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
|
393 |
|
|
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
|
394 |
|
|
wire [93:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
|
395 |
|
|
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
|
396 |
|
|
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
|
397 |
|
|
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
|
398 |
|
|
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
|
399 |
|
|
wire [93:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
|
400 |
|
|
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
|
401 |
|
|
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
|
402 |
|
|
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
|
403 |
|
|
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
|
404 |
|
|
wire [93:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
|
405 |
|
|
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
|
406 |
|
|
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
|
407 |
|
|
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
|
408 |
|
|
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
|
409 |
|
|
wire [93:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
|
410 |
|
|
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
|
411 |
|
|
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
|
412 |
|
|
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
|
413 |
|
|
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
|
414 |
|
|
wire [93:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
|
415 |
|
|
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rp_ready
|
416 |
|
|
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
|
417 |
|
|
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
|
418 |
|
|
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
|
419 |
|
|
wire [100:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
|
420 |
|
|
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
|
421 |
|
|
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
|
422 |
|
|
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
|
423 |
|
|
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
|
424 |
|
|
wire [100:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
|
425 |
|
|
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_003:sink_ready -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_ready
|
426 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
|
427 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
|
428 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
|
429 |
|
|
wire [100:0] onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
|
430 |
|
|
wire onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:rp_ready
|
431 |
|
|
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
|
432 |
|
|
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
|
433 |
|
|
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
|
434 |
|
|
wire [93:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
|
435 |
|
|
wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
|
436 |
|
|
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
|
437 |
|
|
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
|
438 |
|
|
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
|
439 |
|
|
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
|
440 |
|
|
wire [93:0] limiter_rsp_src_data; // limiter:rsp_src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
|
441 |
|
|
wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
|
442 |
|
|
wire limiter_rsp_src_ready; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
|
443 |
|
|
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
|
444 |
|
|
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
|
445 |
|
|
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
|
446 |
|
|
wire [93:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
|
447 |
|
|
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
|
448 |
|
|
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
|
449 |
|
|
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
|
450 |
|
|
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
|
451 |
|
|
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
|
452 |
|
|
wire [93:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
|
453 |
|
|
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
|
454 |
|
|
wire limiter_001_rsp_src_ready; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
|
455 |
|
|
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
456 |
|
|
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
|
457 |
|
|
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
458 |
|
|
wire [75:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
|
459 |
|
|
wire burst_adapter_source0_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
|
460 |
|
|
wire [7:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
|
461 |
|
|
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_008:reset, hibi_pe_dma_0:rst_n, hibi_pe_dma_0_avalon_master_1_translator:reset, hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_master_translator:reset, hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_0:reset_n, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0:reset2, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0_s2_translator:reset, onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_1:reset_n, timer_1_s1_translator:reset, timer_1_s1_translator_avalon_universal_slave_0_agent:reset, timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset]
|
462 |
|
|
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
|
463 |
|
|
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
|
464 |
|
|
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
|
465 |
|
|
wire [93:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
|
466 |
|
|
wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
|
467 |
|
|
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
|
468 |
|
|
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
|
469 |
|
|
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
|
470 |
|
|
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
|
471 |
|
|
wire [93:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
|
472 |
|
|
wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
|
473 |
|
|
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
|
474 |
|
|
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
|
475 |
|
|
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
|
476 |
|
|
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
|
477 |
|
|
wire [93:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
|
478 |
|
|
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
|
479 |
|
|
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
|
480 |
|
|
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
|
481 |
|
|
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
|
482 |
|
|
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
|
483 |
|
|
wire [93:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
|
484 |
|
|
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
|
485 |
|
|
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
|
486 |
|
|
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
487 |
|
|
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
|
488 |
|
|
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
489 |
|
|
wire [93:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
|
490 |
|
|
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
|
491 |
|
|
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
492 |
|
|
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
|
493 |
|
|
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
494 |
|
|
wire [93:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
|
495 |
|
|
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
|
496 |
|
|
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
497 |
|
|
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
|
498 |
|
|
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
499 |
|
|
wire [93:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
|
500 |
|
|
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
|
501 |
|
|
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
502 |
|
|
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
|
503 |
|
|
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
504 |
|
|
wire [93:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
|
505 |
|
|
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
|
506 |
|
|
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
507 |
|
|
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
|
508 |
|
|
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
509 |
|
|
wire [93:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
|
510 |
|
|
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
|
511 |
|
|
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
512 |
|
|
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_valid
|
513 |
|
|
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
514 |
|
|
wire [93:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_data
|
515 |
|
|
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_channel
|
516 |
|
|
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
|
517 |
|
|
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
|
518 |
|
|
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
|
519 |
|
|
wire [93:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
|
520 |
|
|
wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
|
521 |
|
|
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
|
522 |
|
|
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
|
523 |
|
|
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
|
524 |
|
|
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
|
525 |
|
|
wire [93:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
|
526 |
|
|
wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
|
527 |
|
|
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
|
528 |
|
|
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
|
529 |
|
|
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
|
530 |
|
|
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
|
531 |
|
|
wire [93:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
|
532 |
|
|
wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
|
533 |
|
|
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
|
534 |
|
|
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
|
535 |
|
|
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
|
536 |
|
|
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
|
537 |
|
|
wire [93:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
|
538 |
|
|
wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
|
539 |
|
|
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
|
540 |
|
|
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
|
541 |
|
|
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
|
542 |
|
|
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
|
543 |
|
|
wire [93:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
|
544 |
|
|
wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
|
545 |
|
|
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
|
546 |
|
|
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
|
547 |
|
|
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
|
548 |
|
|
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
|
549 |
|
|
wire [93:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
|
550 |
|
|
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
|
551 |
|
|
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
|
552 |
|
|
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
|
553 |
|
|
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
|
554 |
|
|
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
|
555 |
|
|
wire [93:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
|
556 |
|
|
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
|
557 |
|
|
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
|
558 |
|
|
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
|
559 |
|
|
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
|
560 |
|
|
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
|
561 |
|
|
wire [93:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
|
562 |
|
|
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
|
563 |
|
|
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
|
564 |
|
|
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
|
565 |
|
|
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
|
566 |
|
|
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
|
567 |
|
|
wire [93:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
|
568 |
|
|
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
|
569 |
|
|
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
|
570 |
|
|
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
|
571 |
|
|
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
|
572 |
|
|
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
|
573 |
|
|
wire [93:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
|
574 |
|
|
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
|
575 |
|
|
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
|
576 |
|
|
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
|
577 |
|
|
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
|
578 |
|
|
wire [93:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
|
579 |
|
|
wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
|
580 |
|
|
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
|
581 |
|
|
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
|
582 |
|
|
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
|
583 |
|
|
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
|
584 |
|
|
wire [93:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
|
585 |
|
|
wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
|
586 |
|
|
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
|
587 |
|
|
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
|
588 |
|
|
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
|
589 |
|
|
wire [93:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
|
590 |
|
|
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
|
591 |
|
|
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
|
592 |
|
|
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
|
593 |
|
|
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
|
594 |
|
|
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
|
595 |
|
|
wire [93:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
|
596 |
|
|
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
|
597 |
|
|
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
|
598 |
|
|
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
599 |
|
|
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
|
600 |
|
|
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
601 |
|
|
wire [93:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
|
602 |
|
|
wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
|
603 |
|
|
wire cmd_xbar_mux_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
|
604 |
|
|
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
|
605 |
|
|
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
|
606 |
|
|
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
|
607 |
|
|
wire [93:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
|
608 |
|
|
wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
|
609 |
|
|
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
|
610 |
|
|
wire cmd_xbar_demux_001_src2_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
|
611 |
|
|
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
|
612 |
|
|
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
|
613 |
|
|
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
|
614 |
|
|
wire [93:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
|
615 |
|
|
wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
|
616 |
|
|
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
|
617 |
|
|
wire cmd_xbar_demux_001_src3_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
|
618 |
|
|
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
|
619 |
|
|
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
|
620 |
|
|
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
|
621 |
|
|
wire [93:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
|
622 |
|
|
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
|
623 |
|
|
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
|
624 |
|
|
wire cmd_xbar_demux_001_src4_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
|
625 |
|
|
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
|
626 |
|
|
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
|
627 |
|
|
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
|
628 |
|
|
wire [93:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
|
629 |
|
|
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
|
630 |
|
|
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
|
631 |
|
|
wire cmd_xbar_demux_001_src5_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
|
632 |
|
|
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
|
633 |
|
|
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
|
634 |
|
|
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
|
635 |
|
|
wire [93:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
|
636 |
|
|
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
|
637 |
|
|
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
|
638 |
|
|
wire cmd_xbar_demux_001_src6_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
|
639 |
|
|
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
|
640 |
|
|
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
|
641 |
|
|
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
|
642 |
|
|
wire [93:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
|
643 |
|
|
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
|
644 |
|
|
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
|
645 |
|
|
wire cmd_xbar_demux_001_src7_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
|
646 |
|
|
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
|
647 |
|
|
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
|
648 |
|
|
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
|
649 |
|
|
wire [93:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
|
650 |
|
|
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
|
651 |
|
|
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
|
652 |
|
|
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_008:sink0_endofpacket
|
653 |
|
|
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_008:sink0_valid
|
654 |
|
|
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_008:sink0_startofpacket
|
655 |
|
|
wire [100:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_008:sink0_data
|
656 |
|
|
wire [1:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_008:sink0_channel
|
657 |
|
|
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_008:sink0_ready -> cmd_xbar_demux_002:src0_ready
|
658 |
|
|
wire cmd_xbar_demux_003_src0_endofpacket; // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_008:sink1_endofpacket
|
659 |
|
|
wire cmd_xbar_demux_003_src0_valid; // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_008:sink1_valid
|
660 |
|
|
wire cmd_xbar_demux_003_src0_startofpacket; // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_008:sink1_startofpacket
|
661 |
|
|
wire [100:0] cmd_xbar_demux_003_src0_data; // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_008:sink1_data
|
662 |
|
|
wire [1:0] cmd_xbar_demux_003_src0_channel; // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_008:sink1_channel
|
663 |
|
|
wire cmd_xbar_demux_003_src0_ready; // cmd_xbar_mux_008:sink1_ready -> cmd_xbar_demux_003:src0_ready
|
664 |
|
|
wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
|
665 |
|
|
wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
|
666 |
|
|
wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
|
667 |
|
|
wire [100:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
|
668 |
|
|
wire [1:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
|
669 |
|
|
wire rsp_xbar_demux_008_src1_endofpacket; // rsp_xbar_demux_008:src1_endofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_endofpacket
|
670 |
|
|
wire rsp_xbar_demux_008_src1_valid; // rsp_xbar_demux_008:src1_valid -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_valid
|
671 |
|
|
wire rsp_xbar_demux_008_src1_startofpacket; // rsp_xbar_demux_008:src1_startofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_startofpacket
|
672 |
|
|
wire [100:0] rsp_xbar_demux_008_src1_data; // rsp_xbar_demux_008:src1_data -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_data
|
673 |
|
|
wire [1:0] rsp_xbar_demux_008_src1_channel; // rsp_xbar_demux_008:src1_channel -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_channel
|
674 |
|
|
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
|
675 |
|
|
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
|
676 |
|
|
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
|
677 |
|
|
wire [100:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
|
678 |
|
|
wire [1:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
|
679 |
|
|
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
|
680 |
|
|
wire rsp_xbar_demux_008_src0_ready; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src0_ready
|
681 |
|
|
wire addr_router_003_src_endofpacket; // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
|
682 |
|
|
wire addr_router_003_src_valid; // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
|
683 |
|
|
wire addr_router_003_src_startofpacket; // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
|
684 |
|
|
wire [100:0] addr_router_003_src_data; // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
|
685 |
|
|
wire [1:0] addr_router_003_src_channel; // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
|
686 |
|
|
wire addr_router_003_src_ready; // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
|
687 |
|
|
wire rsp_xbar_demux_008_src1_ready; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src1_ready
|
688 |
|
|
wire cmd_xbar_mux_008_src_endofpacket; // cmd_xbar_mux_008:src_endofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_endofpacket
|
689 |
|
|
wire cmd_xbar_mux_008_src_valid; // cmd_xbar_mux_008:src_valid -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_valid
|
690 |
|
|
wire cmd_xbar_mux_008_src_startofpacket; // cmd_xbar_mux_008:src_startofpacket -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_startofpacket
|
691 |
|
|
wire [100:0] cmd_xbar_mux_008_src_data; // cmd_xbar_mux_008:src_data -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_data
|
692 |
|
|
wire [1:0] cmd_xbar_mux_008_src_channel; // cmd_xbar_mux_008:src_channel -> onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_channel
|
693 |
|
|
wire cmd_xbar_mux_008_src_ready; // onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_008:src_ready
|
694 |
|
|
wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
|
695 |
|
|
wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
|
696 |
|
|
wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
|
697 |
|
|
wire [100:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
|
698 |
|
|
wire [1:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
|
699 |
|
|
wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
|
700 |
|
|
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
|
701 |
|
|
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
|
702 |
|
|
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
|
703 |
|
|
wire [93:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter:in_data
|
704 |
|
|
wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
|
705 |
|
|
wire cmd_xbar_mux_001_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
|
706 |
|
|
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
|
707 |
|
|
wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid
|
708 |
|
|
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
|
709 |
|
|
wire [75:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data
|
710 |
|
|
wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready
|
711 |
|
|
wire [7:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel
|
712 |
|
|
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
|
713 |
|
|
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid
|
714 |
|
|
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
|
715 |
|
|
wire [75:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data
|
716 |
|
|
wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel
|
717 |
|
|
wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready
|
718 |
|
|
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
|
719 |
|
|
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
|
720 |
|
|
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
|
721 |
|
|
wire [93:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
|
722 |
|
|
wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
|
723 |
|
|
wire [7:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
|
724 |
|
|
wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
|
725 |
|
|
wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
|
726 |
|
|
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
|
727 |
|
|
wire irq_mapper_receiver1_irq; // timer_0:irq -> irq_mapper:receiver1_irq
|
728 |
|
|
wire irq_mapper_receiver2_irq; // hibi_pe_dma_0:rx_irq_out -> irq_mapper:receiver2_irq
|
729 |
|
|
wire irq_mapper_receiver3_irq; // timer_1:irq -> irq_mapper:receiver3_irq
|
730 |
|
|
wire [31:0] nios2_qsys_0_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:d_irq
|
731 |
|
|
|
732 |
|
|
nios2_sram_nios2_qsys_0 nios2_qsys_0 (
|
733 |
|
|
.clk (clk_clk), // clk.clk
|
734 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
|
735 |
|
|
.d_address (nios2_qsys_0_data_master_address), // data_master.address
|
736 |
|
|
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
|
737 |
|
|
.d_read (nios2_qsys_0_data_master_read), // .read
|
738 |
|
|
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
|
739 |
|
|
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
|
740 |
|
|
.d_write (nios2_qsys_0_data_master_write), // .write
|
741 |
|
|
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
|
742 |
|
|
.d_readdatavalid (nios2_qsys_0_data_master_readdatavalid), // .readdatavalid
|
743 |
|
|
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
|
744 |
|
|
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
|
745 |
|
|
.i_read (nios2_qsys_0_instruction_master_read), // .read
|
746 |
|
|
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
|
747 |
|
|
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
|
748 |
|
|
.i_readdatavalid (nios2_qsys_0_instruction_master_readdatavalid), // .readdatavalid
|
749 |
|
|
.d_irq (nios2_qsys_0_d_irq_irq), // d_irq.irq
|
750 |
|
|
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
|
751 |
|
|
.jtag_debug_module_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
|
752 |
|
|
.jtag_debug_module_begintransfer (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
|
753 |
|
|
.jtag_debug_module_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
754 |
|
|
.jtag_debug_module_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
|
755 |
|
|
.jtag_debug_module_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
|
756 |
|
|
.jtag_debug_module_select (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
757 |
|
|
.jtag_debug_module_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
|
758 |
|
|
.jtag_debug_module_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
|
759 |
|
|
.no_ci_readra () // custom_instruction_master.readra
|
760 |
|
|
);
|
761 |
|
|
|
762 |
|
|
nios2_sram_onchip_memory2_0 onchip_memory2_0 (
|
763 |
|
|
.clk (clk_clk), // clk1.clk
|
764 |
|
|
.address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // s1.address
|
765 |
|
|
.chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
766 |
|
|
.clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken
|
767 |
|
|
.readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
768 |
|
|
.write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write
|
769 |
|
|
.writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
770 |
|
|
.byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
771 |
|
|
.reset (rst_controller_reset_out_reset), // reset1.reset
|
772 |
|
|
.address2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_address), // s2.address
|
773 |
|
|
.chipselect2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
774 |
|
|
.clken2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_clken), // .clken
|
775 |
|
|
.readdata2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_readdata), // .readdata
|
776 |
|
|
.write2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_write), // .write
|
777 |
|
|
.writedata2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_writedata), // .writedata
|
778 |
|
|
.byteenable2 (onchip_memory2_0_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
779 |
|
|
.clk2 (clk_clk), // clk2.clk
|
780 |
|
|
.reset2 (rst_controller_reset_out_reset) // reset2.reset
|
781 |
|
|
);
|
782 |
|
|
|
783 |
|
|
nios2_sram_jtag_uart_0 jtag_uart_0 (
|
784 |
|
|
.clk (clk_clk), // clk.clk
|
785 |
|
|
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
|
786 |
|
|
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
|
787 |
|
|
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
|
788 |
|
|
.av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
|
789 |
|
|
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
|
790 |
|
|
.av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
|
791 |
|
|
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
|
792 |
|
|
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
|
793 |
|
|
.av_irq (irq_mapper_receiver0_irq) // irq.irq
|
794 |
|
|
);
|
795 |
|
|
|
796 |
|
|
nios2_sram_timer_0 timer_0 (
|
797 |
|
|
.clk (clk_clk), // clk.clk
|
798 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
799 |
|
|
.address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address
|
800 |
|
|
.writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
801 |
|
|
.readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
802 |
|
|
.chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
803 |
|
|
.write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n
|
804 |
|
|
.irq (irq_mapper_receiver1_irq) // irq.irq
|
805 |
|
|
);
|
806 |
|
|
|
807 |
|
|
nios2_sram_sysid_qsys_0 sysid_qsys_0 (
|
808 |
|
|
.clock (clk_clk), // clk.clk
|
809 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
810 |
|
|
.readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
|
811 |
|
|
.address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address
|
812 |
|
|
);
|
813 |
|
|
|
814 |
|
|
hibi_pe_dma #(
|
815 |
|
|
.data_width_g (32),
|
816 |
|
|
.addr_width_g (32),
|
817 |
|
|
.words_width_g (16),
|
818 |
|
|
.n_stream_chans_g (2),
|
819 |
|
|
.n_packet_chans_g (2),
|
820 |
|
|
.n_chans_bits_g (3),
|
821 |
|
|
.hibi_addr_cmp_lo_g (0),
|
822 |
|
|
.hibi_addr_cmp_hi_g (31)
|
823 |
|
|
) hibi_pe_dma_0 (
|
824 |
|
|
.avalon_cfg_addr_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_slave_0.address
|
825 |
|
|
.avalon_cfg_we_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
|
826 |
|
|
.avalon_cfg_re_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
|
827 |
|
|
.avalon_cfg_cs_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
828 |
|
|
.avalon_cfg_waitrequest_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
|
829 |
|
|
.avalon_cfg_writedata_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
|
830 |
|
|
.avalon_cfg_readdata_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
|
831 |
|
|
.hibi_data_in (hibi_pe_dma_data_in), // conduit_end.export
|
832 |
|
|
.hibi_av_in (hibi_pe_dma_av_in), // .export
|
833 |
|
|
.hibi_empty_in (hibi_pe_dma_empty_in), // .export
|
834 |
|
|
.hibi_comm_in (hibi_pe_dma_comm_in), // .export
|
835 |
|
|
.hibi_re_out (hibi_pe_dma_re_out), // .export
|
836 |
|
|
.hibi_data_out (hibi_pe_dma_data_out), // .export
|
837 |
|
|
.hibi_av_out (hibi_pe_dma_av_out), // .export
|
838 |
|
|
.hibi_full_in (hibi_pe_dma_full_in), // .export
|
839 |
|
|
.hibi_comm_out (hibi_pe_dma_comm_out), // .export
|
840 |
|
|
.hibi_we_out (hibi_pe_dma_we_out), // .export
|
841 |
|
|
.rst_n (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n
|
842 |
|
|
.rx_irq_out (irq_mapper_receiver2_irq), // interrupt_sender.irq
|
843 |
|
|
.avalon_addr_out_rx (hibi_pe_dma_0_avalon_master_address), // avalon_master.address
|
844 |
|
|
.avalon_we_out_rx (hibi_pe_dma_0_avalon_master_write), // .write
|
845 |
|
|
.avalon_be_out_rx (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable
|
846 |
|
|
.avalon_writedata_out_rx (hibi_pe_dma_0_avalon_master_writedata), // .writedata
|
847 |
|
|
.avalon_waitrequest_in_rx (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest
|
848 |
|
|
.avalon_readdatavalid_in_tx (hibi_pe_dma_0_avalon_master_1_readdatavalid), // avalon_master_1.readdatavalid
|
849 |
|
|
.avalon_waitrequest_in_tx (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest
|
850 |
|
|
.avalon_readdata_in_tx (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata
|
851 |
|
|
.avalon_re_out_tx (hibi_pe_dma_0_avalon_master_1_read), // .read
|
852 |
|
|
.avalon_addr_out_tx (hibi_pe_dma_0_avalon_master_1_address), // .address
|
853 |
|
|
.clk (clk_clk) // clock.clk
|
854 |
|
|
);
|
855 |
|
|
|
856 |
|
|
nios2_sram_timer_0 timer_1 (
|
857 |
|
|
.clk (clk_clk), // clk.clk
|
858 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
859 |
|
|
.address (timer_1_s1_translator_avalon_anti_slave_0_address), // s1.address
|
860 |
|
|
.writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
861 |
|
|
.readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
862 |
|
|
.chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
863 |
|
|
.write_n (~timer_1_s1_translator_avalon_anti_slave_0_write), // .write_n
|
864 |
|
|
.irq (irq_mapper_receiver3_irq) // irq.irq
|
865 |
|
|
);
|
866 |
|
|
|
867 |
|
|
nios2_sram_sram_0 sram_0 (
|
868 |
|
|
.clk (clk_clk), // clock_reset.clk
|
869 |
|
|
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
|
870 |
|
|
.SRAM_DQ (sram_DQ), // external_interface.export
|
871 |
|
|
.SRAM_ADDR (sram_ADDR), // .export
|
872 |
|
|
.SRAM_LB_N (sram_LB_N), // .export
|
873 |
|
|
.SRAM_UB_N (sram_UB_N), // .export
|
874 |
|
|
.SRAM_CE_N (sram_CE_N), // .export
|
875 |
|
|
.SRAM_OE_N (sram_OE_N), // .export
|
876 |
|
|
.SRAM_WE_N (sram_WE_N), // .export
|
877 |
|
|
.address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_sram_slave.address
|
878 |
|
|
.byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
879 |
|
|
.read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
|
880 |
|
|
.write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
|
881 |
|
|
.writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
|
882 |
|
|
.readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata) // .readdata
|
883 |
|
|
);
|
884 |
|
|
|
885 |
|
|
altera_merlin_master_translator #(
|
886 |
|
|
.AV_ADDRESS_W (21),
|
887 |
|
|
.AV_DATA_W (32),
|
888 |
|
|
.AV_BURSTCOUNT_W (1),
|
889 |
|
|
.AV_BYTEENABLE_W (4),
|
890 |
|
|
.UAV_ADDRESS_W (21),
|
891 |
|
|
.UAV_BURSTCOUNT_W (3),
|
892 |
|
|
.USE_READ (1),
|
893 |
|
|
.USE_WRITE (0),
|
894 |
|
|
.USE_BEGINBURSTTRANSFER (0),
|
895 |
|
|
.USE_BEGINTRANSFER (0),
|
896 |
|
|
.USE_CHIPSELECT (0),
|
897 |
|
|
.USE_BURSTCOUNT (0),
|
898 |
|
|
.USE_READDATAVALID (1),
|
899 |
|
|
.USE_WAITREQUEST (1),
|
900 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
901 |
|
|
.AV_ADDRESS_SYMBOLS (1),
|
902 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
903 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
904 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
905 |
|
|
.AV_LINEWRAPBURSTS (1),
|
906 |
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
907 |
|
|
) nios2_qsys_0_instruction_master_translator (
|
908 |
|
|
.clk (clk_clk), // clk.clk
|
909 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
910 |
|
|
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
911 |
|
|
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
912 |
|
|
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
|
913 |
|
|
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
|
914 |
|
|
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
915 |
|
|
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
916 |
|
|
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
917 |
|
|
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
|
918 |
|
|
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
|
919 |
|
|
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
|
920 |
|
|
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
921 |
|
|
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
|
922 |
|
|
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
|
923 |
|
|
.av_read (nios2_qsys_0_instruction_master_read), // .read
|
924 |
|
|
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
|
925 |
|
|
.av_readdatavalid (nios2_qsys_0_instruction_master_readdatavalid), // .readdatavalid
|
926 |
|
|
.av_burstcount (1'b1), // (terminated)
|
927 |
|
|
.av_byteenable (4'b1111), // (terminated)
|
928 |
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
929 |
|
|
.av_begintransfer (1'b0), // (terminated)
|
930 |
|
|
.av_chipselect (1'b0), // (terminated)
|
931 |
|
|
.av_write (1'b0), // (terminated)
|
932 |
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
933 |
|
|
.av_lock (1'b0), // (terminated)
|
934 |
|
|
.av_debugaccess (1'b0), // (terminated)
|
935 |
|
|
.uav_clken (), // (terminated)
|
936 |
|
|
.av_clken (1'b1) // (terminated)
|
937 |
|
|
);
|
938 |
|
|
|
939 |
|
|
altera_merlin_master_translator #(
|
940 |
|
|
.AV_ADDRESS_W (21),
|
941 |
|
|
.AV_DATA_W (32),
|
942 |
|
|
.AV_BURSTCOUNT_W (1),
|
943 |
|
|
.AV_BYTEENABLE_W (4),
|
944 |
|
|
.UAV_ADDRESS_W (21),
|
945 |
|
|
.UAV_BURSTCOUNT_W (3),
|
946 |
|
|
.USE_READ (1),
|
947 |
|
|
.USE_WRITE (1),
|
948 |
|
|
.USE_BEGINBURSTTRANSFER (0),
|
949 |
|
|
.USE_BEGINTRANSFER (0),
|
950 |
|
|
.USE_CHIPSELECT (0),
|
951 |
|
|
.USE_BURSTCOUNT (0),
|
952 |
|
|
.USE_READDATAVALID (1),
|
953 |
|
|
.USE_WAITREQUEST (1),
|
954 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
955 |
|
|
.AV_ADDRESS_SYMBOLS (1),
|
956 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
957 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
958 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
959 |
|
|
.AV_LINEWRAPBURSTS (0),
|
960 |
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
961 |
|
|
) nios2_qsys_0_data_master_translator (
|
962 |
|
|
.clk (clk_clk), // clk.clk
|
963 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
964 |
|
|
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
965 |
|
|
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
966 |
|
|
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
|
967 |
|
|
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
|
968 |
|
|
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
969 |
|
|
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
970 |
|
|
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
971 |
|
|
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
|
972 |
|
|
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
|
973 |
|
|
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
|
974 |
|
|
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
975 |
|
|
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
|
976 |
|
|
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
|
977 |
|
|
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
|
978 |
|
|
.av_read (nios2_qsys_0_data_master_read), // .read
|
979 |
|
|
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
|
980 |
|
|
.av_readdatavalid (nios2_qsys_0_data_master_readdatavalid), // .readdatavalid
|
981 |
|
|
.av_write (nios2_qsys_0_data_master_write), // .write
|
982 |
|
|
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
|
983 |
|
|
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
|
984 |
|
|
.av_burstcount (1'b1), // (terminated)
|
985 |
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
986 |
|
|
.av_begintransfer (1'b0), // (terminated)
|
987 |
|
|
.av_chipselect (1'b0), // (terminated)
|
988 |
|
|
.av_lock (1'b0), // (terminated)
|
989 |
|
|
.uav_clken (), // (terminated)
|
990 |
|
|
.av_clken (1'b1) // (terminated)
|
991 |
|
|
);
|
992 |
|
|
|
993 |
|
|
altera_merlin_slave_translator #(
|
994 |
|
|
.AV_ADDRESS_W (9),
|
995 |
|
|
.AV_DATA_W (32),
|
996 |
|
|
.UAV_DATA_W (32),
|
997 |
|
|
.AV_BURSTCOUNT_W (1),
|
998 |
|
|
.AV_BYTEENABLE_W (4),
|
999 |
|
|
.UAV_BYTEENABLE_W (4),
|
1000 |
|
|
.UAV_ADDRESS_W (21),
|
1001 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1002 |
|
|
.AV_READLATENCY (0),
|
1003 |
|
|
.USE_READDATAVALID (0),
|
1004 |
|
|
.USE_WAITREQUEST (0),
|
1005 |
|
|
.USE_UAV_CLKEN (0),
|
1006 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1007 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1008 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1009 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1010 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1011 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1012 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1013 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1014 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1015 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1016 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1017 |
|
|
) nios2_qsys_0_jtag_debug_module_translator (
|
1018 |
|
|
.clk (clk_clk), // clk.clk
|
1019 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1020 |
|
|
.uav_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1021 |
|
|
.uav_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1022 |
|
|
.uav_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1023 |
|
|
.uav_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1024 |
|
|
.uav_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1025 |
|
|
.uav_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1026 |
|
|
.uav_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1027 |
|
|
.uav_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1028 |
|
|
.uav_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1029 |
|
|
.uav_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1030 |
|
|
.uav_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1031 |
|
|
.av_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1032 |
|
|
.av_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
|
1033 |
|
|
.av_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
|
1034 |
|
|
.av_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
|
1035 |
|
|
.av_begintransfer (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
|
1036 |
|
|
.av_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
1037 |
|
|
.av_chipselect (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1038 |
|
|
.av_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
|
1039 |
|
|
.av_read (), // (terminated)
|
1040 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1041 |
|
|
.av_burstcount (), // (terminated)
|
1042 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1043 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1044 |
|
|
.av_writebyteenable (), // (terminated)
|
1045 |
|
|
.av_lock (), // (terminated)
|
1046 |
|
|
.av_clken (), // (terminated)
|
1047 |
|
|
.uav_clken (1'b0), // (terminated)
|
1048 |
|
|
.av_outputenable () // (terminated)
|
1049 |
|
|
);
|
1050 |
|
|
|
1051 |
|
|
altera_merlin_slave_translator #(
|
1052 |
|
|
.AV_ADDRESS_W (18),
|
1053 |
|
|
.AV_DATA_W (16),
|
1054 |
|
|
.UAV_DATA_W (16),
|
1055 |
|
|
.AV_BURSTCOUNT_W (1),
|
1056 |
|
|
.AV_BYTEENABLE_W (2),
|
1057 |
|
|
.UAV_BYTEENABLE_W (2),
|
1058 |
|
|
.UAV_ADDRESS_W (21),
|
1059 |
|
|
.UAV_BURSTCOUNT_W (2),
|
1060 |
|
|
.AV_READLATENCY (2),
|
1061 |
|
|
.USE_READDATAVALID (0),
|
1062 |
|
|
.USE_WAITREQUEST (0),
|
1063 |
|
|
.USE_UAV_CLKEN (0),
|
1064 |
|
|
.AV_SYMBOLS_PER_WORD (2),
|
1065 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1066 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1067 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1068 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1069 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1070 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1071 |
|
|
.AV_READ_WAIT_CYCLES (0),
|
1072 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1073 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1074 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1075 |
|
|
) sram_0_avalon_sram_slave_translator (
|
1076 |
|
|
.clk (clk_clk), // clk.clk
|
1077 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1078 |
|
|
.uav_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1079 |
|
|
.uav_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1080 |
|
|
.uav_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1081 |
|
|
.uav_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1082 |
|
|
.uav_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1083 |
|
|
.uav_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1084 |
|
|
.uav_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1085 |
|
|
.uav_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1086 |
|
|
.uav_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1087 |
|
|
.uav_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1088 |
|
|
.uav_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1089 |
|
|
.av_address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1090 |
|
|
.av_write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
|
1091 |
|
|
.av_read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
|
1092 |
|
|
.av_readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
|
1093 |
|
|
.av_writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
|
1094 |
|
|
.av_byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
1095 |
|
|
.av_begintransfer (), // (terminated)
|
1096 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1097 |
|
|
.av_burstcount (), // (terminated)
|
1098 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1099 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1100 |
|
|
.av_writebyteenable (), // (terminated)
|
1101 |
|
|
.av_lock (), // (terminated)
|
1102 |
|
|
.av_chipselect (), // (terminated)
|
1103 |
|
|
.av_clken (), // (terminated)
|
1104 |
|
|
.uav_clken (1'b0), // (terminated)
|
1105 |
|
|
.av_debugaccess (), // (terminated)
|
1106 |
|
|
.av_outputenable () // (terminated)
|
1107 |
|
|
);
|
1108 |
|
|
|
1109 |
|
|
altera_merlin_slave_translator #(
|
1110 |
|
|
.AV_ADDRESS_W (11),
|
1111 |
|
|
.AV_DATA_W (32),
|
1112 |
|
|
.UAV_DATA_W (32),
|
1113 |
|
|
.AV_BURSTCOUNT_W (1),
|
1114 |
|
|
.AV_BYTEENABLE_W (4),
|
1115 |
|
|
.UAV_BYTEENABLE_W (4),
|
1116 |
|
|
.UAV_ADDRESS_W (21),
|
1117 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1118 |
|
|
.AV_READLATENCY (1),
|
1119 |
|
|
.USE_READDATAVALID (0),
|
1120 |
|
|
.USE_WAITREQUEST (0),
|
1121 |
|
|
.USE_UAV_CLKEN (0),
|
1122 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1123 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1124 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1125 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1126 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1127 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1128 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1129 |
|
|
.AV_READ_WAIT_CYCLES (0),
|
1130 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1131 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1132 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1133 |
|
|
) onchip_memory2_0_s1_translator (
|
1134 |
|
|
.clk (clk_clk), // clk.clk
|
1135 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1136 |
|
|
.uav_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1137 |
|
|
.uav_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1138 |
|
|
.uav_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1139 |
|
|
.uav_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1140 |
|
|
.uav_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1141 |
|
|
.uav_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1142 |
|
|
.uav_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1143 |
|
|
.uav_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1144 |
|
|
.uav_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1145 |
|
|
.uav_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1146 |
|
|
.uav_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1147 |
|
|
.av_address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1148 |
|
|
.av_write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write
|
1149 |
|
|
.av_readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
1150 |
|
|
.av_writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
1151 |
|
|
.av_byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
1152 |
|
|
.av_chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1153 |
|
|
.av_clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken
|
1154 |
|
|
.av_read (), // (terminated)
|
1155 |
|
|
.av_begintransfer (), // (terminated)
|
1156 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1157 |
|
|
.av_burstcount (), // (terminated)
|
1158 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1159 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1160 |
|
|
.av_writebyteenable (), // (terminated)
|
1161 |
|
|
.av_lock (), // (terminated)
|
1162 |
|
|
.uav_clken (1'b0), // (terminated)
|
1163 |
|
|
.av_debugaccess (), // (terminated)
|
1164 |
|
|
.av_outputenable () // (terminated)
|
1165 |
|
|
);
|
1166 |
|
|
|
1167 |
|
|
altera_merlin_slave_translator #(
|
1168 |
|
|
.AV_ADDRESS_W (1),
|
1169 |
|
|
.AV_DATA_W (32),
|
1170 |
|
|
.UAV_DATA_W (32),
|
1171 |
|
|
.AV_BURSTCOUNT_W (1),
|
1172 |
|
|
.AV_BYTEENABLE_W (1),
|
1173 |
|
|
.UAV_BYTEENABLE_W (4),
|
1174 |
|
|
.UAV_ADDRESS_W (21),
|
1175 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1176 |
|
|
.AV_READLATENCY (0),
|
1177 |
|
|
.USE_READDATAVALID (0),
|
1178 |
|
|
.USE_WAITREQUEST (1),
|
1179 |
|
|
.USE_UAV_CLKEN (0),
|
1180 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1181 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1182 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1183 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1184 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1185 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1186 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1187 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1188 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1189 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1190 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1191 |
|
|
) jtag_uart_0_avalon_jtag_slave_translator (
|
1192 |
|
|
.clk (clk_clk), // clk.clk
|
1193 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1194 |
|
|
.uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1195 |
|
|
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1196 |
|
|
.uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1197 |
|
|
.uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1198 |
|
|
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1199 |
|
|
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1200 |
|
|
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1201 |
|
|
.uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1202 |
|
|
.uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1203 |
|
|
.uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1204 |
|
|
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1205 |
|
|
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1206 |
|
|
.av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
|
1207 |
|
|
.av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
|
1208 |
|
|
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
|
1209 |
|
|
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
|
1210 |
|
|
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
|
1211 |
|
|
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1212 |
|
|
.av_begintransfer (), // (terminated)
|
1213 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1214 |
|
|
.av_burstcount (), // (terminated)
|
1215 |
|
|
.av_byteenable (), // (terminated)
|
1216 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1217 |
|
|
.av_writebyteenable (), // (terminated)
|
1218 |
|
|
.av_lock (), // (terminated)
|
1219 |
|
|
.av_clken (), // (terminated)
|
1220 |
|
|
.uav_clken (1'b0), // (terminated)
|
1221 |
|
|
.av_debugaccess (), // (terminated)
|
1222 |
|
|
.av_outputenable () // (terminated)
|
1223 |
|
|
);
|
1224 |
|
|
|
1225 |
|
|
altera_merlin_slave_translator #(
|
1226 |
|
|
.AV_ADDRESS_W (3),
|
1227 |
|
|
.AV_DATA_W (16),
|
1228 |
|
|
.UAV_DATA_W (32),
|
1229 |
|
|
.AV_BURSTCOUNT_W (1),
|
1230 |
|
|
.AV_BYTEENABLE_W (1),
|
1231 |
|
|
.UAV_BYTEENABLE_W (4),
|
1232 |
|
|
.UAV_ADDRESS_W (21),
|
1233 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1234 |
|
|
.AV_READLATENCY (0),
|
1235 |
|
|
.USE_READDATAVALID (0),
|
1236 |
|
|
.USE_WAITREQUEST (0),
|
1237 |
|
|
.USE_UAV_CLKEN (0),
|
1238 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1239 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1240 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1241 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1242 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1243 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1244 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1245 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1246 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1247 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1248 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1249 |
|
|
) timer_0_s1_translator (
|
1250 |
|
|
.clk (clk_clk), // clk.clk
|
1251 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1252 |
|
|
.uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1253 |
|
|
.uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1254 |
|
|
.uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1255 |
|
|
.uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1256 |
|
|
.uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1257 |
|
|
.uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1258 |
|
|
.uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1259 |
|
|
.uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1260 |
|
|
.uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1261 |
|
|
.uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1262 |
|
|
.uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1263 |
|
|
.av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1264 |
|
|
.av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write
|
1265 |
|
|
.av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
1266 |
|
|
.av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
1267 |
|
|
.av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1268 |
|
|
.av_read (), // (terminated)
|
1269 |
|
|
.av_begintransfer (), // (terminated)
|
1270 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1271 |
|
|
.av_burstcount (), // (terminated)
|
1272 |
|
|
.av_byteenable (), // (terminated)
|
1273 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1274 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1275 |
|
|
.av_writebyteenable (), // (terminated)
|
1276 |
|
|
.av_lock (), // (terminated)
|
1277 |
|
|
.av_clken (), // (terminated)
|
1278 |
|
|
.uav_clken (1'b0), // (terminated)
|
1279 |
|
|
.av_debugaccess (), // (terminated)
|
1280 |
|
|
.av_outputenable () // (terminated)
|
1281 |
|
|
);
|
1282 |
|
|
|
1283 |
|
|
altera_merlin_slave_translator #(
|
1284 |
|
|
.AV_ADDRESS_W (1),
|
1285 |
|
|
.AV_DATA_W (32),
|
1286 |
|
|
.UAV_DATA_W (32),
|
1287 |
|
|
.AV_BURSTCOUNT_W (1),
|
1288 |
|
|
.AV_BYTEENABLE_W (4),
|
1289 |
|
|
.UAV_BYTEENABLE_W (4),
|
1290 |
|
|
.UAV_ADDRESS_W (21),
|
1291 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1292 |
|
|
.AV_READLATENCY (0),
|
1293 |
|
|
.USE_READDATAVALID (0),
|
1294 |
|
|
.USE_WAITREQUEST (0),
|
1295 |
|
|
.USE_UAV_CLKEN (0),
|
1296 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1297 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1298 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1299 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1300 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1301 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1302 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1303 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1304 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1305 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1306 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1307 |
|
|
) sysid_qsys_0_control_slave_translator (
|
1308 |
|
|
.clk (clk_clk), // clk.clk
|
1309 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1310 |
|
|
.uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1311 |
|
|
.uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1312 |
|
|
.uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1313 |
|
|
.uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1314 |
|
|
.uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1315 |
|
|
.uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1316 |
|
|
.uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1317 |
|
|
.uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1318 |
|
|
.uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1319 |
|
|
.uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1320 |
|
|
.uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1321 |
|
|
.av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1322 |
|
|
.av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
|
1323 |
|
|
.av_write (), // (terminated)
|
1324 |
|
|
.av_read (), // (terminated)
|
1325 |
|
|
.av_writedata (), // (terminated)
|
1326 |
|
|
.av_begintransfer (), // (terminated)
|
1327 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1328 |
|
|
.av_burstcount (), // (terminated)
|
1329 |
|
|
.av_byteenable (), // (terminated)
|
1330 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1331 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1332 |
|
|
.av_writebyteenable (), // (terminated)
|
1333 |
|
|
.av_lock (), // (terminated)
|
1334 |
|
|
.av_chipselect (), // (terminated)
|
1335 |
|
|
.av_clken (), // (terminated)
|
1336 |
|
|
.uav_clken (1'b0), // (terminated)
|
1337 |
|
|
.av_debugaccess (), // (terminated)
|
1338 |
|
|
.av_outputenable () // (terminated)
|
1339 |
|
|
);
|
1340 |
|
|
|
1341 |
|
|
altera_merlin_slave_translator #(
|
1342 |
|
|
.AV_ADDRESS_W (7),
|
1343 |
|
|
.AV_DATA_W (32),
|
1344 |
|
|
.UAV_DATA_W (32),
|
1345 |
|
|
.AV_BURSTCOUNT_W (1),
|
1346 |
|
|
.AV_BYTEENABLE_W (4),
|
1347 |
|
|
.UAV_BYTEENABLE_W (4),
|
1348 |
|
|
.UAV_ADDRESS_W (21),
|
1349 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1350 |
|
|
.AV_READLATENCY (0),
|
1351 |
|
|
.USE_READDATAVALID (0),
|
1352 |
|
|
.USE_WAITREQUEST (1),
|
1353 |
|
|
.USE_UAV_CLKEN (0),
|
1354 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1355 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1356 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1357 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1358 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1359 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1360 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1361 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1362 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1363 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1364 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1365 |
|
|
) hibi_pe_dma_0_avalon_slave_0_translator (
|
1366 |
|
|
.clk (clk_clk), // clk.clk
|
1367 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1368 |
|
|
.uav_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1369 |
|
|
.uav_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1370 |
|
|
.uav_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1371 |
|
|
.uav_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1372 |
|
|
.uav_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1373 |
|
|
.uav_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1374 |
|
|
.uav_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1375 |
|
|
.uav_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1376 |
|
|
.uav_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1377 |
|
|
.uav_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1378 |
|
|
.uav_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1379 |
|
|
.av_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1380 |
|
|
.av_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
|
1381 |
|
|
.av_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
|
1382 |
|
|
.av_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
|
1383 |
|
|
.av_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
|
1384 |
|
|
.av_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
|
1385 |
|
|
.av_chipselect (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1386 |
|
|
.av_begintransfer (), // (terminated)
|
1387 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1388 |
|
|
.av_burstcount (), // (terminated)
|
1389 |
|
|
.av_byteenable (), // (terminated)
|
1390 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1391 |
|
|
.av_writebyteenable (), // (terminated)
|
1392 |
|
|
.av_lock (), // (terminated)
|
1393 |
|
|
.av_clken (), // (terminated)
|
1394 |
|
|
.uav_clken (1'b0), // (terminated)
|
1395 |
|
|
.av_debugaccess (), // (terminated)
|
1396 |
|
|
.av_outputenable () // (terminated)
|
1397 |
|
|
);
|
1398 |
|
|
|
1399 |
|
|
altera_merlin_slave_translator #(
|
1400 |
|
|
.AV_ADDRESS_W (3),
|
1401 |
|
|
.AV_DATA_W (16),
|
1402 |
|
|
.UAV_DATA_W (32),
|
1403 |
|
|
.AV_BURSTCOUNT_W (1),
|
1404 |
|
|
.AV_BYTEENABLE_W (1),
|
1405 |
|
|
.UAV_BYTEENABLE_W (4),
|
1406 |
|
|
.UAV_ADDRESS_W (21),
|
1407 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1408 |
|
|
.AV_READLATENCY (0),
|
1409 |
|
|
.USE_READDATAVALID (0),
|
1410 |
|
|
.USE_WAITREQUEST (0),
|
1411 |
|
|
.USE_UAV_CLKEN (0),
|
1412 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1413 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1414 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1415 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1416 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1417 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1418 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1419 |
|
|
.AV_READ_WAIT_CYCLES (1),
|
1420 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1421 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1422 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1423 |
|
|
) timer_1_s1_translator (
|
1424 |
|
|
.clk (clk_clk), // clk.clk
|
1425 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1426 |
|
|
.uav_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1427 |
|
|
.uav_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1428 |
|
|
.uav_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1429 |
|
|
.uav_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1430 |
|
|
.uav_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1431 |
|
|
.uav_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1432 |
|
|
.uav_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1433 |
|
|
.uav_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1434 |
|
|
.uav_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1435 |
|
|
.uav_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1436 |
|
|
.uav_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1437 |
|
|
.av_address (timer_1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1438 |
|
|
.av_write (timer_1_s1_translator_avalon_anti_slave_0_write), // .write
|
1439 |
|
|
.av_readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
|
1440 |
|
|
.av_writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
|
1441 |
|
|
.av_chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1442 |
|
|
.av_read (), // (terminated)
|
1443 |
|
|
.av_begintransfer (), // (terminated)
|
1444 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1445 |
|
|
.av_burstcount (), // (terminated)
|
1446 |
|
|
.av_byteenable (), // (terminated)
|
1447 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1448 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1449 |
|
|
.av_writebyteenable (), // (terminated)
|
1450 |
|
|
.av_lock (), // (terminated)
|
1451 |
|
|
.av_clken (), // (terminated)
|
1452 |
|
|
.uav_clken (1'b0), // (terminated)
|
1453 |
|
|
.av_debugaccess (), // (terminated)
|
1454 |
|
|
.av_outputenable () // (terminated)
|
1455 |
|
|
);
|
1456 |
|
|
|
1457 |
|
|
altera_merlin_master_translator #(
|
1458 |
|
|
.AV_ADDRESS_W (32),
|
1459 |
|
|
.AV_DATA_W (32),
|
1460 |
|
|
.AV_BURSTCOUNT_W (1),
|
1461 |
|
|
.AV_BYTEENABLE_W (4),
|
1462 |
|
|
.UAV_ADDRESS_W (32),
|
1463 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1464 |
|
|
.USE_READ (0),
|
1465 |
|
|
.USE_WRITE (1),
|
1466 |
|
|
.USE_BEGINBURSTTRANSFER (0),
|
1467 |
|
|
.USE_BEGINTRANSFER (0),
|
1468 |
|
|
.USE_CHIPSELECT (0),
|
1469 |
|
|
.USE_BURSTCOUNT (0),
|
1470 |
|
|
.USE_READDATAVALID (0),
|
1471 |
|
|
.USE_WAITREQUEST (1),
|
1472 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1473 |
|
|
.AV_ADDRESS_SYMBOLS (1),
|
1474 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1475 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1476 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1477 |
|
|
.AV_LINEWRAPBURSTS (0),
|
1478 |
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
1479 |
|
|
) hibi_pe_dma_0_avalon_master_translator (
|
1480 |
|
|
.clk (clk_clk), // clk.clk
|
1481 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1482 |
|
|
.uav_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
1483 |
|
|
.uav_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
1484 |
|
|
.uav_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read
|
1485 |
|
|
.uav_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write
|
1486 |
|
|
.uav_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
1487 |
|
|
.uav_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
1488 |
|
|
.uav_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
1489 |
|
|
.uav_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
|
1490 |
|
|
.uav_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
|
1491 |
|
|
.uav_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
|
1492 |
|
|
.uav_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
1493 |
|
|
.av_address (hibi_pe_dma_0_avalon_master_address), // avalon_anti_master_0.address
|
1494 |
|
|
.av_waitrequest (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest
|
1495 |
|
|
.av_byteenable (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable
|
1496 |
|
|
.av_write (hibi_pe_dma_0_avalon_master_write), // .write
|
1497 |
|
|
.av_writedata (hibi_pe_dma_0_avalon_master_writedata), // .writedata
|
1498 |
|
|
.av_burstcount (1'b1), // (terminated)
|
1499 |
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
1500 |
|
|
.av_begintransfer (1'b0), // (terminated)
|
1501 |
|
|
.av_chipselect (1'b0), // (terminated)
|
1502 |
|
|
.av_read (1'b0), // (terminated)
|
1503 |
|
|
.av_readdata (), // (terminated)
|
1504 |
|
|
.av_readdatavalid (), // (terminated)
|
1505 |
|
|
.av_lock (1'b0), // (terminated)
|
1506 |
|
|
.av_debugaccess (1'b0), // (terminated)
|
1507 |
|
|
.uav_clken (), // (terminated)
|
1508 |
|
|
.av_clken (1'b1) // (terminated)
|
1509 |
|
|
);
|
1510 |
|
|
|
1511 |
|
|
altera_merlin_master_translator #(
|
1512 |
|
|
.AV_ADDRESS_W (32),
|
1513 |
|
|
.AV_DATA_W (32),
|
1514 |
|
|
.AV_BURSTCOUNT_W (1),
|
1515 |
|
|
.AV_BYTEENABLE_W (4),
|
1516 |
|
|
.UAV_ADDRESS_W (32),
|
1517 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1518 |
|
|
.USE_READ (1),
|
1519 |
|
|
.USE_WRITE (0),
|
1520 |
|
|
.USE_BEGINBURSTTRANSFER (0),
|
1521 |
|
|
.USE_BEGINTRANSFER (0),
|
1522 |
|
|
.USE_CHIPSELECT (0),
|
1523 |
|
|
.USE_BURSTCOUNT (0),
|
1524 |
|
|
.USE_READDATAVALID (1),
|
1525 |
|
|
.USE_WAITREQUEST (1),
|
1526 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1527 |
|
|
.AV_ADDRESS_SYMBOLS (1),
|
1528 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1529 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1530 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1531 |
|
|
.AV_LINEWRAPBURSTS (0),
|
1532 |
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
1533 |
|
|
) hibi_pe_dma_0_avalon_master_1_translator (
|
1534 |
|
|
.clk (clk_clk), // clk.clk
|
1535 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1536 |
|
|
.uav_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
1537 |
|
|
.uav_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount
|
1538 |
|
|
.uav_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read
|
1539 |
|
|
.uav_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write
|
1540 |
|
|
.uav_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
1541 |
|
|
.uav_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
1542 |
|
|
.uav_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable
|
1543 |
|
|
.uav_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata
|
1544 |
|
|
.uav_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata
|
1545 |
|
|
.uav_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock
|
1546 |
|
|
.uav_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
1547 |
|
|
.av_address (hibi_pe_dma_0_avalon_master_1_address), // avalon_anti_master_0.address
|
1548 |
|
|
.av_waitrequest (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest
|
1549 |
|
|
.av_read (hibi_pe_dma_0_avalon_master_1_read), // .read
|
1550 |
|
|
.av_readdata (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata
|
1551 |
|
|
.av_readdatavalid (hibi_pe_dma_0_avalon_master_1_readdatavalid), // .readdatavalid
|
1552 |
|
|
.av_burstcount (1'b1), // (terminated)
|
1553 |
|
|
.av_byteenable (4'b1111), // (terminated)
|
1554 |
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
1555 |
|
|
.av_begintransfer (1'b0), // (terminated)
|
1556 |
|
|
.av_chipselect (1'b0), // (terminated)
|
1557 |
|
|
.av_write (1'b0), // (terminated)
|
1558 |
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
1559 |
|
|
.av_lock (1'b0), // (terminated)
|
1560 |
|
|
.av_debugaccess (1'b0), // (terminated)
|
1561 |
|
|
.uav_clken (), // (terminated)
|
1562 |
|
|
.av_clken (1'b1) // (terminated)
|
1563 |
|
|
);
|
1564 |
|
|
|
1565 |
|
|
altera_merlin_slave_translator #(
|
1566 |
|
|
.AV_ADDRESS_W (11),
|
1567 |
|
|
.AV_DATA_W (32),
|
1568 |
|
|
.UAV_DATA_W (32),
|
1569 |
|
|
.AV_BURSTCOUNT_W (1),
|
1570 |
|
|
.AV_BYTEENABLE_W (4),
|
1571 |
|
|
.UAV_BYTEENABLE_W (4),
|
1572 |
|
|
.UAV_ADDRESS_W (32),
|
1573 |
|
|
.UAV_BURSTCOUNT_W (3),
|
1574 |
|
|
.AV_READLATENCY (1),
|
1575 |
|
|
.USE_READDATAVALID (0),
|
1576 |
|
|
.USE_WAITREQUEST (0),
|
1577 |
|
|
.USE_UAV_CLKEN (0),
|
1578 |
|
|
.AV_SYMBOLS_PER_WORD (4),
|
1579 |
|
|
.AV_ADDRESS_SYMBOLS (0),
|
1580 |
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
1581 |
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
1582 |
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
1583 |
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
1584 |
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
1585 |
|
|
.AV_READ_WAIT_CYCLES (0),
|
1586 |
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
1587 |
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
1588 |
|
|
.AV_DATA_HOLD_CYCLES (0)
|
1589 |
|
|
) onchip_memory2_0_s2_translator (
|
1590 |
|
|
.clk (clk_clk), // clk.clk
|
1591 |
|
|
.reset (rst_controller_reset_out_reset), // reset.reset
|
1592 |
|
|
.uav_address (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
|
1593 |
|
|
.uav_burstcount (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1594 |
|
|
.uav_read (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1595 |
|
|
.uav_write (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1596 |
|
|
.uav_waitrequest (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1597 |
|
|
.uav_readdatavalid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1598 |
|
|
.uav_byteenable (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1599 |
|
|
.uav_readdata (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1600 |
|
|
.uav_writedata (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1601 |
|
|
.uav_lock (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1602 |
|
|
.uav_debugaccess (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1603 |
|
|
.av_address (onchip_memory2_0_s2_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
|
1604 |
|
|
.av_write (onchip_memory2_0_s2_translator_avalon_anti_slave_0_write), // .write
|
1605 |
|
|
.av_readdata (onchip_memory2_0_s2_translator_avalon_anti_slave_0_readdata), // .readdata
|
1606 |
|
|
.av_writedata (onchip_memory2_0_s2_translator_avalon_anti_slave_0_writedata), // .writedata
|
1607 |
|
|
.av_byteenable (onchip_memory2_0_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable
|
1608 |
|
|
.av_chipselect (onchip_memory2_0_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect
|
1609 |
|
|
.av_clken (onchip_memory2_0_s2_translator_avalon_anti_slave_0_clken), // .clken
|
1610 |
|
|
.av_read (), // (terminated)
|
1611 |
|
|
.av_begintransfer (), // (terminated)
|
1612 |
|
|
.av_beginbursttransfer (), // (terminated)
|
1613 |
|
|
.av_burstcount (), // (terminated)
|
1614 |
|
|
.av_readdatavalid (1'b0), // (terminated)
|
1615 |
|
|
.av_waitrequest (1'b0), // (terminated)
|
1616 |
|
|
.av_writebyteenable (), // (terminated)
|
1617 |
|
|
.av_lock (), // (terminated)
|
1618 |
|
|
.uav_clken (1'b0), // (terminated)
|
1619 |
|
|
.av_debugaccess (), // (terminated)
|
1620 |
|
|
.av_outputenable () // (terminated)
|
1621 |
|
|
);
|
1622 |
|
|
|
1623 |
|
|
altera_merlin_master_agent #(
|
1624 |
|
|
.PKT_PROTECTION_H (87),
|
1625 |
|
|
.PKT_PROTECTION_L (85),
|
1626 |
|
|
.PKT_BEGIN_BURST (76),
|
1627 |
|
|
.PKT_BURSTWRAP_H (68),
|
1628 |
|
|
.PKT_BURSTWRAP_L (66),
|
1629 |
|
|
.PKT_BURST_SIZE_H (71),
|
1630 |
|
|
.PKT_BURST_SIZE_L (69),
|
1631 |
|
|
.PKT_BURST_TYPE_H (73),
|
1632 |
|
|
.PKT_BURST_TYPE_L (72),
|
1633 |
|
|
.PKT_BYTE_CNT_H (65),
|
1634 |
|
|
.PKT_BYTE_CNT_L (63),
|
1635 |
|
|
.PKT_ADDR_H (56),
|
1636 |
|
|
.PKT_ADDR_L (36),
|
1637 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
1638 |
|
|
.PKT_TRANS_POSTED (58),
|
1639 |
|
|
.PKT_TRANS_WRITE (59),
|
1640 |
|
|
.PKT_TRANS_READ (60),
|
1641 |
|
|
.PKT_TRANS_LOCK (61),
|
1642 |
|
|
.PKT_TRANS_EXCLUSIVE (62),
|
1643 |
|
|
.PKT_DATA_H (31),
|
1644 |
|
|
.PKT_DATA_L (0),
|
1645 |
|
|
.PKT_BYTEEN_H (35),
|
1646 |
|
|
.PKT_BYTEEN_L (32),
|
1647 |
|
|
.PKT_SRC_ID_H (80),
|
1648 |
|
|
.PKT_SRC_ID_L (78),
|
1649 |
|
|
.PKT_DEST_ID_H (83),
|
1650 |
|
|
.PKT_DEST_ID_L (81),
|
1651 |
|
|
.PKT_THREAD_ID_H (84),
|
1652 |
|
|
.PKT_THREAD_ID_L (84),
|
1653 |
|
|
.PKT_CACHE_H (91),
|
1654 |
|
|
.PKT_CACHE_L (88),
|
1655 |
|
|
.PKT_DATA_SIDEBAND_H (75),
|
1656 |
|
|
.PKT_DATA_SIDEBAND_L (75),
|
1657 |
|
|
.PKT_QOS_H (77),
|
1658 |
|
|
.PKT_QOS_L (77),
|
1659 |
|
|
.PKT_ADDR_SIDEBAND_H (74),
|
1660 |
|
|
.PKT_ADDR_SIDEBAND_L (74),
|
1661 |
|
|
.ST_DATA_W (94),
|
1662 |
|
|
.ST_CHANNEL_W (8),
|
1663 |
|
|
.AV_BURSTCOUNT_W (3),
|
1664 |
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
1665 |
|
|
.ID (0),
|
1666 |
|
|
.BURSTWRAP_VALUE (3),
|
1667 |
|
|
.CACHE_VALUE (4'b0000)
|
1668 |
|
|
) nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent (
|
1669 |
|
|
.clk (clk_clk), // clk.clk
|
1670 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1671 |
|
|
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
|
1672 |
|
|
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
|
1673 |
|
|
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
|
1674 |
|
|
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
|
1675 |
|
|
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
|
1676 |
|
|
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
1677 |
|
|
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
1678 |
|
|
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
1679 |
|
|
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
1680 |
|
|
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
1681 |
|
|
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
|
1682 |
|
|
.cp_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
|
1683 |
|
|
.cp_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
1684 |
|
|
.cp_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
1685 |
|
|
.cp_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
1686 |
|
|
.cp_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
|
1687 |
|
|
.rp_valid (limiter_rsp_src_valid), // rp.valid
|
1688 |
|
|
.rp_data (limiter_rsp_src_data), // .data
|
1689 |
|
|
.rp_channel (limiter_rsp_src_channel), // .channel
|
1690 |
|
|
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
|
1691 |
|
|
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
|
1692 |
|
|
.rp_ready (limiter_rsp_src_ready) // .ready
|
1693 |
|
|
);
|
1694 |
|
|
|
1695 |
|
|
altera_merlin_master_agent #(
|
1696 |
|
|
.PKT_PROTECTION_H (87),
|
1697 |
|
|
.PKT_PROTECTION_L (85),
|
1698 |
|
|
.PKT_BEGIN_BURST (76),
|
1699 |
|
|
.PKT_BURSTWRAP_H (68),
|
1700 |
|
|
.PKT_BURSTWRAP_L (66),
|
1701 |
|
|
.PKT_BURST_SIZE_H (71),
|
1702 |
|
|
.PKT_BURST_SIZE_L (69),
|
1703 |
|
|
.PKT_BURST_TYPE_H (73),
|
1704 |
|
|
.PKT_BURST_TYPE_L (72),
|
1705 |
|
|
.PKT_BYTE_CNT_H (65),
|
1706 |
|
|
.PKT_BYTE_CNT_L (63),
|
1707 |
|
|
.PKT_ADDR_H (56),
|
1708 |
|
|
.PKT_ADDR_L (36),
|
1709 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
1710 |
|
|
.PKT_TRANS_POSTED (58),
|
1711 |
|
|
.PKT_TRANS_WRITE (59),
|
1712 |
|
|
.PKT_TRANS_READ (60),
|
1713 |
|
|
.PKT_TRANS_LOCK (61),
|
1714 |
|
|
.PKT_TRANS_EXCLUSIVE (62),
|
1715 |
|
|
.PKT_DATA_H (31),
|
1716 |
|
|
.PKT_DATA_L (0),
|
1717 |
|
|
.PKT_BYTEEN_H (35),
|
1718 |
|
|
.PKT_BYTEEN_L (32),
|
1719 |
|
|
.PKT_SRC_ID_H (80),
|
1720 |
|
|
.PKT_SRC_ID_L (78),
|
1721 |
|
|
.PKT_DEST_ID_H (83),
|
1722 |
|
|
.PKT_DEST_ID_L (81),
|
1723 |
|
|
.PKT_THREAD_ID_H (84),
|
1724 |
|
|
.PKT_THREAD_ID_L (84),
|
1725 |
|
|
.PKT_CACHE_H (91),
|
1726 |
|
|
.PKT_CACHE_L (88),
|
1727 |
|
|
.PKT_DATA_SIDEBAND_H (75),
|
1728 |
|
|
.PKT_DATA_SIDEBAND_L (75),
|
1729 |
|
|
.PKT_QOS_H (77),
|
1730 |
|
|
.PKT_QOS_L (77),
|
1731 |
|
|
.PKT_ADDR_SIDEBAND_H (74),
|
1732 |
|
|
.PKT_ADDR_SIDEBAND_L (74),
|
1733 |
|
|
.ST_DATA_W (94),
|
1734 |
|
|
.ST_CHANNEL_W (8),
|
1735 |
|
|
.AV_BURSTCOUNT_W (3),
|
1736 |
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
1737 |
|
|
.ID (1),
|
1738 |
|
|
.BURSTWRAP_VALUE (7),
|
1739 |
|
|
.CACHE_VALUE (4'b0000)
|
1740 |
|
|
) nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent (
|
1741 |
|
|
.clk (clk_clk), // clk.clk
|
1742 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1743 |
|
|
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
|
1744 |
|
|
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
|
1745 |
|
|
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
|
1746 |
|
|
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
|
1747 |
|
|
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
|
1748 |
|
|
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
1749 |
|
|
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
1750 |
|
|
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
1751 |
|
|
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
1752 |
|
|
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
1753 |
|
|
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
|
1754 |
|
|
.cp_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
|
1755 |
|
|
.cp_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
1756 |
|
|
.cp_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
1757 |
|
|
.cp_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
1758 |
|
|
.cp_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
|
1759 |
|
|
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
|
1760 |
|
|
.rp_data (limiter_001_rsp_src_data), // .data
|
1761 |
|
|
.rp_channel (limiter_001_rsp_src_channel), // .channel
|
1762 |
|
|
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
|
1763 |
|
|
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
|
1764 |
|
|
.rp_ready (limiter_001_rsp_src_ready) // .ready
|
1765 |
|
|
);
|
1766 |
|
|
|
1767 |
|
|
altera_merlin_slave_agent #(
|
1768 |
|
|
.PKT_DATA_H (31),
|
1769 |
|
|
.PKT_DATA_L (0),
|
1770 |
|
|
.PKT_BEGIN_BURST (76),
|
1771 |
|
|
.PKT_SYMBOL_W (8),
|
1772 |
|
|
.PKT_BYTEEN_H (35),
|
1773 |
|
|
.PKT_BYTEEN_L (32),
|
1774 |
|
|
.PKT_ADDR_H (56),
|
1775 |
|
|
.PKT_ADDR_L (36),
|
1776 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
1777 |
|
|
.PKT_TRANS_POSTED (58),
|
1778 |
|
|
.PKT_TRANS_WRITE (59),
|
1779 |
|
|
.PKT_TRANS_READ (60),
|
1780 |
|
|
.PKT_TRANS_LOCK (61),
|
1781 |
|
|
.PKT_SRC_ID_H (80),
|
1782 |
|
|
.PKT_SRC_ID_L (78),
|
1783 |
|
|
.PKT_DEST_ID_H (83),
|
1784 |
|
|
.PKT_DEST_ID_L (81),
|
1785 |
|
|
.PKT_BURSTWRAP_H (68),
|
1786 |
|
|
.PKT_BURSTWRAP_L (66),
|
1787 |
|
|
.PKT_BYTE_CNT_H (65),
|
1788 |
|
|
.PKT_BYTE_CNT_L (63),
|
1789 |
|
|
.PKT_PROTECTION_H (87),
|
1790 |
|
|
.PKT_PROTECTION_L (85),
|
1791 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
1792 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
1793 |
|
|
.PKT_BURST_SIZE_H (71),
|
1794 |
|
|
.PKT_BURST_SIZE_L (69),
|
1795 |
|
|
.ST_CHANNEL_W (8),
|
1796 |
|
|
.ST_DATA_W (94),
|
1797 |
|
|
.AVS_BURSTCOUNT_W (3),
|
1798 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
1799 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
1800 |
|
|
) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent (
|
1801 |
|
|
.clk (clk_clk), // clk.clk
|
1802 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1803 |
|
|
.m0_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
1804 |
|
|
.m0_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1805 |
|
|
.m0_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1806 |
|
|
.m0_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1807 |
|
|
.m0_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1808 |
|
|
.m0_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1809 |
|
|
.m0_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1810 |
|
|
.m0_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1811 |
|
|
.m0_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1812 |
|
|
.m0_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1813 |
|
|
.m0_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1814 |
|
|
.rp_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
1815 |
|
|
.rp_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
1816 |
|
|
.rp_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
1817 |
|
|
.rp_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
1818 |
|
|
.rp_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
1819 |
|
|
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
|
1820 |
|
|
.cp_valid (cmd_xbar_mux_src_valid), // .valid
|
1821 |
|
|
.cp_data (cmd_xbar_mux_src_data), // .data
|
1822 |
|
|
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
|
1823 |
|
|
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
|
1824 |
|
|
.cp_channel (cmd_xbar_mux_src_channel), // .channel
|
1825 |
|
|
.rf_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
1826 |
|
|
.rf_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
1827 |
|
|
.rf_sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
1828 |
|
|
.rf_sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
1829 |
|
|
.rf_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
1830 |
|
|
.rf_source_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
1831 |
|
|
.rf_source_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
1832 |
|
|
.rf_source_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
1833 |
|
|
.rf_source_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
1834 |
|
|
.rf_source_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
1835 |
|
|
.rdata_fifo_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
1836 |
|
|
.rdata_fifo_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
1837 |
|
|
.rdata_fifo_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
1838 |
|
|
.rdata_fifo_src_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
1839 |
|
|
.rdata_fifo_src_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
1840 |
|
|
.rdata_fifo_src_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
1841 |
|
|
);
|
1842 |
|
|
|
1843 |
|
|
altera_avalon_sc_fifo #(
|
1844 |
|
|
.SYMBOLS_PER_BEAT (1),
|
1845 |
|
|
.BITS_PER_SYMBOL (95),
|
1846 |
|
|
.FIFO_DEPTH (2),
|
1847 |
|
|
.CHANNEL_WIDTH (0),
|
1848 |
|
|
.ERROR_WIDTH (0),
|
1849 |
|
|
.USE_PACKETS (1),
|
1850 |
|
|
.USE_FILL_LEVEL (0),
|
1851 |
|
|
.EMPTY_LATENCY (1),
|
1852 |
|
|
.USE_MEMORY_BLOCKS (0),
|
1853 |
|
|
.USE_STORE_FORWARD (0),
|
1854 |
|
|
.USE_ALMOST_FULL_IF (0),
|
1855 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
1856 |
|
|
) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
1857 |
|
|
.clk (clk_clk), // clk.clk
|
1858 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1859 |
|
|
.in_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
1860 |
|
|
.in_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
1861 |
|
|
.in_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
1862 |
|
|
.in_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
1863 |
|
|
.in_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
1864 |
|
|
.out_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
1865 |
|
|
.out_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
1866 |
|
|
.out_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
1867 |
|
|
.out_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
1868 |
|
|
.out_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
1869 |
|
|
.csr_address (2'b00), // (terminated)
|
1870 |
|
|
.csr_read (1'b0), // (terminated)
|
1871 |
|
|
.csr_write (1'b0), // (terminated)
|
1872 |
|
|
.csr_readdata (), // (terminated)
|
1873 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
1874 |
|
|
.almost_full_data (), // (terminated)
|
1875 |
|
|
.almost_empty_data (), // (terminated)
|
1876 |
|
|
.in_empty (1'b0), // (terminated)
|
1877 |
|
|
.out_empty (), // (terminated)
|
1878 |
|
|
.in_error (1'b0), // (terminated)
|
1879 |
|
|
.out_error (), // (terminated)
|
1880 |
|
|
.in_channel (1'b0), // (terminated)
|
1881 |
|
|
.out_channel () // (terminated)
|
1882 |
|
|
);
|
1883 |
|
|
|
1884 |
|
|
altera_merlin_slave_agent #(
|
1885 |
|
|
.PKT_DATA_H (15),
|
1886 |
|
|
.PKT_DATA_L (0),
|
1887 |
|
|
.PKT_BEGIN_BURST (58),
|
1888 |
|
|
.PKT_SYMBOL_W (8),
|
1889 |
|
|
.PKT_BYTEEN_H (17),
|
1890 |
|
|
.PKT_BYTEEN_L (16),
|
1891 |
|
|
.PKT_ADDR_H (38),
|
1892 |
|
|
.PKT_ADDR_L (18),
|
1893 |
|
|
.PKT_TRANS_COMPRESSED_READ (39),
|
1894 |
|
|
.PKT_TRANS_POSTED (40),
|
1895 |
|
|
.PKT_TRANS_WRITE (41),
|
1896 |
|
|
.PKT_TRANS_READ (42),
|
1897 |
|
|
.PKT_TRANS_LOCK (43),
|
1898 |
|
|
.PKT_SRC_ID_H (62),
|
1899 |
|
|
.PKT_SRC_ID_L (60),
|
1900 |
|
|
.PKT_DEST_ID_H (65),
|
1901 |
|
|
.PKT_DEST_ID_L (63),
|
1902 |
|
|
.PKT_BURSTWRAP_H (50),
|
1903 |
|
|
.PKT_BURSTWRAP_L (48),
|
1904 |
|
|
.PKT_BYTE_CNT_H (47),
|
1905 |
|
|
.PKT_BYTE_CNT_L (45),
|
1906 |
|
|
.PKT_PROTECTION_H (69),
|
1907 |
|
|
.PKT_PROTECTION_L (67),
|
1908 |
|
|
.PKT_RESPONSE_STATUS_H (75),
|
1909 |
|
|
.PKT_RESPONSE_STATUS_L (74),
|
1910 |
|
|
.PKT_BURST_SIZE_H (53),
|
1911 |
|
|
.PKT_BURST_SIZE_L (51),
|
1912 |
|
|
.ST_CHANNEL_W (8),
|
1913 |
|
|
.ST_DATA_W (76),
|
1914 |
|
|
.AVS_BURSTCOUNT_W (2),
|
1915 |
|
|
.SUPPRESS_0_BYTEEN_CMD (1),
|
1916 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
1917 |
|
|
) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent (
|
1918 |
|
|
.clk (clk_clk), // clk.clk
|
1919 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1920 |
|
|
.m0_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
1921 |
|
|
.m0_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
1922 |
|
|
.m0_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
1923 |
|
|
.m0_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
1924 |
|
|
.m0_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
1925 |
|
|
.m0_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
1926 |
|
|
.m0_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
1927 |
|
|
.m0_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
1928 |
|
|
.m0_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
1929 |
|
|
.m0_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
1930 |
|
|
.m0_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
1931 |
|
|
.rp_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
1932 |
|
|
.rp_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
1933 |
|
|
.rp_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
1934 |
|
|
.rp_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
1935 |
|
|
.rp_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
1936 |
|
|
.cp_ready (burst_adapter_source0_ready), // cp.ready
|
1937 |
|
|
.cp_valid (burst_adapter_source0_valid), // .valid
|
1938 |
|
|
.cp_data (burst_adapter_source0_data), // .data
|
1939 |
|
|
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
|
1940 |
|
|
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
|
1941 |
|
|
.cp_channel (burst_adapter_source0_channel), // .channel
|
1942 |
|
|
.rf_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
1943 |
|
|
.rf_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
1944 |
|
|
.rf_sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
1945 |
|
|
.rf_sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
1946 |
|
|
.rf_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
1947 |
|
|
.rf_source_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
1948 |
|
|
.rf_source_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
1949 |
|
|
.rf_source_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
1950 |
|
|
.rf_source_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
1951 |
|
|
.rf_source_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
1952 |
|
|
.rdata_fifo_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
1953 |
|
|
.rdata_fifo_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
1954 |
|
|
.rdata_fifo_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
1955 |
|
|
.rdata_fifo_src_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
1956 |
|
|
.rdata_fifo_src_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
1957 |
|
|
.rdata_fifo_src_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
1958 |
|
|
);
|
1959 |
|
|
|
1960 |
|
|
altera_avalon_sc_fifo #(
|
1961 |
|
|
.SYMBOLS_PER_BEAT (1),
|
1962 |
|
|
.BITS_PER_SYMBOL (77),
|
1963 |
|
|
.FIFO_DEPTH (3),
|
1964 |
|
|
.CHANNEL_WIDTH (0),
|
1965 |
|
|
.ERROR_WIDTH (0),
|
1966 |
|
|
.USE_PACKETS (1),
|
1967 |
|
|
.USE_FILL_LEVEL (0),
|
1968 |
|
|
.EMPTY_LATENCY (1),
|
1969 |
|
|
.USE_MEMORY_BLOCKS (0),
|
1970 |
|
|
.USE_STORE_FORWARD (0),
|
1971 |
|
|
.USE_ALMOST_FULL_IF (0),
|
1972 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
1973 |
|
|
) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
1974 |
|
|
.clk (clk_clk), // clk.clk
|
1975 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
1976 |
|
|
.in_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
1977 |
|
|
.in_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
1978 |
|
|
.in_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
1979 |
|
|
.in_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
1980 |
|
|
.in_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
1981 |
|
|
.out_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
1982 |
|
|
.out_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
1983 |
|
|
.out_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
1984 |
|
|
.out_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
1985 |
|
|
.out_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
1986 |
|
|
.csr_address (2'b00), // (terminated)
|
1987 |
|
|
.csr_read (1'b0), // (terminated)
|
1988 |
|
|
.csr_write (1'b0), // (terminated)
|
1989 |
|
|
.csr_readdata (), // (terminated)
|
1990 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
1991 |
|
|
.almost_full_data (), // (terminated)
|
1992 |
|
|
.almost_empty_data (), // (terminated)
|
1993 |
|
|
.in_empty (1'b0), // (terminated)
|
1994 |
|
|
.out_empty (), // (terminated)
|
1995 |
|
|
.in_error (1'b0), // (terminated)
|
1996 |
|
|
.out_error (), // (terminated)
|
1997 |
|
|
.in_channel (1'b0), // (terminated)
|
1998 |
|
|
.out_channel () // (terminated)
|
1999 |
|
|
);
|
2000 |
|
|
|
2001 |
|
|
altera_merlin_slave_agent #(
|
2002 |
|
|
.PKT_DATA_H (31),
|
2003 |
|
|
.PKT_DATA_L (0),
|
2004 |
|
|
.PKT_BEGIN_BURST (76),
|
2005 |
|
|
.PKT_SYMBOL_W (8),
|
2006 |
|
|
.PKT_BYTEEN_H (35),
|
2007 |
|
|
.PKT_BYTEEN_L (32),
|
2008 |
|
|
.PKT_ADDR_H (56),
|
2009 |
|
|
.PKT_ADDR_L (36),
|
2010 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2011 |
|
|
.PKT_TRANS_POSTED (58),
|
2012 |
|
|
.PKT_TRANS_WRITE (59),
|
2013 |
|
|
.PKT_TRANS_READ (60),
|
2014 |
|
|
.PKT_TRANS_LOCK (61),
|
2015 |
|
|
.PKT_SRC_ID_H (80),
|
2016 |
|
|
.PKT_SRC_ID_L (78),
|
2017 |
|
|
.PKT_DEST_ID_H (83),
|
2018 |
|
|
.PKT_DEST_ID_L (81),
|
2019 |
|
|
.PKT_BURSTWRAP_H (68),
|
2020 |
|
|
.PKT_BURSTWRAP_L (66),
|
2021 |
|
|
.PKT_BYTE_CNT_H (65),
|
2022 |
|
|
.PKT_BYTE_CNT_L (63),
|
2023 |
|
|
.PKT_PROTECTION_H (87),
|
2024 |
|
|
.PKT_PROTECTION_L (85),
|
2025 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2026 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2027 |
|
|
.PKT_BURST_SIZE_H (71),
|
2028 |
|
|
.PKT_BURST_SIZE_L (69),
|
2029 |
|
|
.ST_CHANNEL_W (8),
|
2030 |
|
|
.ST_DATA_W (94),
|
2031 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2032 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2033 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2034 |
|
|
) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent (
|
2035 |
|
|
.clk (clk_clk), // clk.clk
|
2036 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2037 |
|
|
.m0_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2038 |
|
|
.m0_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2039 |
|
|
.m0_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2040 |
|
|
.m0_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2041 |
|
|
.m0_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2042 |
|
|
.m0_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2043 |
|
|
.m0_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2044 |
|
|
.m0_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2045 |
|
|
.m0_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2046 |
|
|
.m0_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2047 |
|
|
.m0_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2048 |
|
|
.rp_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2049 |
|
|
.rp_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2050 |
|
|
.rp_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2051 |
|
|
.rp_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2052 |
|
|
.rp_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2053 |
|
|
.cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
|
2054 |
|
|
.cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
|
2055 |
|
|
.cp_data (cmd_xbar_demux_001_src2_data), // .data
|
2056 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
|
2057 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
|
2058 |
|
|
.cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
|
2059 |
|
|
.rf_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2060 |
|
|
.rf_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2061 |
|
|
.rf_sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2062 |
|
|
.rf_sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2063 |
|
|
.rf_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2064 |
|
|
.rf_source_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2065 |
|
|
.rf_source_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2066 |
|
|
.rf_source_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2067 |
|
|
.rf_source_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2068 |
|
|
.rf_source_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2069 |
|
|
.rdata_fifo_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2070 |
|
|
.rdata_fifo_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2071 |
|
|
.rdata_fifo_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2072 |
|
|
.rdata_fifo_src_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2073 |
|
|
.rdata_fifo_src_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2074 |
|
|
.rdata_fifo_src_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2075 |
|
|
);
|
2076 |
|
|
|
2077 |
|
|
altera_avalon_sc_fifo #(
|
2078 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2079 |
|
|
.BITS_PER_SYMBOL (95),
|
2080 |
|
|
.FIFO_DEPTH (2),
|
2081 |
|
|
.CHANNEL_WIDTH (0),
|
2082 |
|
|
.ERROR_WIDTH (0),
|
2083 |
|
|
.USE_PACKETS (1),
|
2084 |
|
|
.USE_FILL_LEVEL (0),
|
2085 |
|
|
.EMPTY_LATENCY (1),
|
2086 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2087 |
|
|
.USE_STORE_FORWARD (0),
|
2088 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2089 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2090 |
|
|
) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2091 |
|
|
.clk (clk_clk), // clk.clk
|
2092 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2093 |
|
|
.in_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2094 |
|
|
.in_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2095 |
|
|
.in_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2096 |
|
|
.in_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2097 |
|
|
.in_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2098 |
|
|
.out_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2099 |
|
|
.out_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2100 |
|
|
.out_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2101 |
|
|
.out_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2102 |
|
|
.out_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2103 |
|
|
.csr_address (2'b00), // (terminated)
|
2104 |
|
|
.csr_read (1'b0), // (terminated)
|
2105 |
|
|
.csr_write (1'b0), // (terminated)
|
2106 |
|
|
.csr_readdata (), // (terminated)
|
2107 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2108 |
|
|
.almost_full_data (), // (terminated)
|
2109 |
|
|
.almost_empty_data (), // (terminated)
|
2110 |
|
|
.in_empty (1'b0), // (terminated)
|
2111 |
|
|
.out_empty (), // (terminated)
|
2112 |
|
|
.in_error (1'b0), // (terminated)
|
2113 |
|
|
.out_error (), // (terminated)
|
2114 |
|
|
.in_channel (1'b0), // (terminated)
|
2115 |
|
|
.out_channel () // (terminated)
|
2116 |
|
|
);
|
2117 |
|
|
|
2118 |
|
|
altera_merlin_slave_agent #(
|
2119 |
|
|
.PKT_DATA_H (31),
|
2120 |
|
|
.PKT_DATA_L (0),
|
2121 |
|
|
.PKT_BEGIN_BURST (76),
|
2122 |
|
|
.PKT_SYMBOL_W (8),
|
2123 |
|
|
.PKT_BYTEEN_H (35),
|
2124 |
|
|
.PKT_BYTEEN_L (32),
|
2125 |
|
|
.PKT_ADDR_H (56),
|
2126 |
|
|
.PKT_ADDR_L (36),
|
2127 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2128 |
|
|
.PKT_TRANS_POSTED (58),
|
2129 |
|
|
.PKT_TRANS_WRITE (59),
|
2130 |
|
|
.PKT_TRANS_READ (60),
|
2131 |
|
|
.PKT_TRANS_LOCK (61),
|
2132 |
|
|
.PKT_SRC_ID_H (80),
|
2133 |
|
|
.PKT_SRC_ID_L (78),
|
2134 |
|
|
.PKT_DEST_ID_H (83),
|
2135 |
|
|
.PKT_DEST_ID_L (81),
|
2136 |
|
|
.PKT_BURSTWRAP_H (68),
|
2137 |
|
|
.PKT_BURSTWRAP_L (66),
|
2138 |
|
|
.PKT_BYTE_CNT_H (65),
|
2139 |
|
|
.PKT_BYTE_CNT_L (63),
|
2140 |
|
|
.PKT_PROTECTION_H (87),
|
2141 |
|
|
.PKT_PROTECTION_L (85),
|
2142 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2143 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2144 |
|
|
.PKT_BURST_SIZE_H (71),
|
2145 |
|
|
.PKT_BURST_SIZE_L (69),
|
2146 |
|
|
.ST_CHANNEL_W (8),
|
2147 |
|
|
.ST_DATA_W (94),
|
2148 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2149 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2150 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2151 |
|
|
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
|
2152 |
|
|
.clk (clk_clk), // clk.clk
|
2153 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2154 |
|
|
.m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2155 |
|
|
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2156 |
|
|
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2157 |
|
|
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2158 |
|
|
.m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2159 |
|
|
.m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2160 |
|
|
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2161 |
|
|
.m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2162 |
|
|
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2163 |
|
|
.m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2164 |
|
|
.m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2165 |
|
|
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2166 |
|
|
.rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2167 |
|
|
.rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2168 |
|
|
.rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2169 |
|
|
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2170 |
|
|
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
|
2171 |
|
|
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
|
2172 |
|
|
.cp_data (cmd_xbar_demux_001_src3_data), // .data
|
2173 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
|
2174 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
|
2175 |
|
|
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
|
2176 |
|
|
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2177 |
|
|
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2178 |
|
|
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2179 |
|
|
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2180 |
|
|
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2181 |
|
|
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2182 |
|
|
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2183 |
|
|
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2184 |
|
|
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2185 |
|
|
.rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2186 |
|
|
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2187 |
|
|
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2188 |
|
|
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2189 |
|
|
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2190 |
|
|
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2191 |
|
|
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2192 |
|
|
);
|
2193 |
|
|
|
2194 |
|
|
altera_avalon_sc_fifo #(
|
2195 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2196 |
|
|
.BITS_PER_SYMBOL (95),
|
2197 |
|
|
.FIFO_DEPTH (2),
|
2198 |
|
|
.CHANNEL_WIDTH (0),
|
2199 |
|
|
.ERROR_WIDTH (0),
|
2200 |
|
|
.USE_PACKETS (1),
|
2201 |
|
|
.USE_FILL_LEVEL (0),
|
2202 |
|
|
.EMPTY_LATENCY (1),
|
2203 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2204 |
|
|
.USE_STORE_FORWARD (0),
|
2205 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2206 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2207 |
|
|
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2208 |
|
|
.clk (clk_clk), // clk.clk
|
2209 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2210 |
|
|
.in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2211 |
|
|
.in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2212 |
|
|
.in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2213 |
|
|
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2214 |
|
|
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2215 |
|
|
.out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2216 |
|
|
.out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2217 |
|
|
.out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2218 |
|
|
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2219 |
|
|
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2220 |
|
|
.csr_address (2'b00), // (terminated)
|
2221 |
|
|
.csr_read (1'b0), // (terminated)
|
2222 |
|
|
.csr_write (1'b0), // (terminated)
|
2223 |
|
|
.csr_readdata (), // (terminated)
|
2224 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2225 |
|
|
.almost_full_data (), // (terminated)
|
2226 |
|
|
.almost_empty_data (), // (terminated)
|
2227 |
|
|
.in_empty (1'b0), // (terminated)
|
2228 |
|
|
.out_empty (), // (terminated)
|
2229 |
|
|
.in_error (1'b0), // (terminated)
|
2230 |
|
|
.out_error (), // (terminated)
|
2231 |
|
|
.in_channel (1'b0), // (terminated)
|
2232 |
|
|
.out_channel () // (terminated)
|
2233 |
|
|
);
|
2234 |
|
|
|
2235 |
|
|
altera_merlin_slave_agent #(
|
2236 |
|
|
.PKT_DATA_H (31),
|
2237 |
|
|
.PKT_DATA_L (0),
|
2238 |
|
|
.PKT_BEGIN_BURST (76),
|
2239 |
|
|
.PKT_SYMBOL_W (8),
|
2240 |
|
|
.PKT_BYTEEN_H (35),
|
2241 |
|
|
.PKT_BYTEEN_L (32),
|
2242 |
|
|
.PKT_ADDR_H (56),
|
2243 |
|
|
.PKT_ADDR_L (36),
|
2244 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2245 |
|
|
.PKT_TRANS_POSTED (58),
|
2246 |
|
|
.PKT_TRANS_WRITE (59),
|
2247 |
|
|
.PKT_TRANS_READ (60),
|
2248 |
|
|
.PKT_TRANS_LOCK (61),
|
2249 |
|
|
.PKT_SRC_ID_H (80),
|
2250 |
|
|
.PKT_SRC_ID_L (78),
|
2251 |
|
|
.PKT_DEST_ID_H (83),
|
2252 |
|
|
.PKT_DEST_ID_L (81),
|
2253 |
|
|
.PKT_BURSTWRAP_H (68),
|
2254 |
|
|
.PKT_BURSTWRAP_L (66),
|
2255 |
|
|
.PKT_BYTE_CNT_H (65),
|
2256 |
|
|
.PKT_BYTE_CNT_L (63),
|
2257 |
|
|
.PKT_PROTECTION_H (87),
|
2258 |
|
|
.PKT_PROTECTION_L (85),
|
2259 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2260 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2261 |
|
|
.PKT_BURST_SIZE_H (71),
|
2262 |
|
|
.PKT_BURST_SIZE_L (69),
|
2263 |
|
|
.ST_CHANNEL_W (8),
|
2264 |
|
|
.ST_DATA_W (94),
|
2265 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2266 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2267 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2268 |
|
|
) timer_0_s1_translator_avalon_universal_slave_0_agent (
|
2269 |
|
|
.clk (clk_clk), // clk.clk
|
2270 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2271 |
|
|
.m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2272 |
|
|
.m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2273 |
|
|
.m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2274 |
|
|
.m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2275 |
|
|
.m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2276 |
|
|
.m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2277 |
|
|
.m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2278 |
|
|
.m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2279 |
|
|
.m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2280 |
|
|
.m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2281 |
|
|
.m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2282 |
|
|
.rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2283 |
|
|
.rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2284 |
|
|
.rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2285 |
|
|
.rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2286 |
|
|
.rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2287 |
|
|
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
|
2288 |
|
|
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
|
2289 |
|
|
.cp_data (cmd_xbar_demux_001_src4_data), // .data
|
2290 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
|
2291 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
|
2292 |
|
|
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
|
2293 |
|
|
.rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2294 |
|
|
.rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2295 |
|
|
.rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2296 |
|
|
.rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2297 |
|
|
.rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2298 |
|
|
.rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2299 |
|
|
.rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2300 |
|
|
.rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2301 |
|
|
.rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2302 |
|
|
.rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2303 |
|
|
.rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2304 |
|
|
.rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2305 |
|
|
.rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2306 |
|
|
.rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2307 |
|
|
.rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2308 |
|
|
.rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2309 |
|
|
);
|
2310 |
|
|
|
2311 |
|
|
altera_avalon_sc_fifo #(
|
2312 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2313 |
|
|
.BITS_PER_SYMBOL (95),
|
2314 |
|
|
.FIFO_DEPTH (2),
|
2315 |
|
|
.CHANNEL_WIDTH (0),
|
2316 |
|
|
.ERROR_WIDTH (0),
|
2317 |
|
|
.USE_PACKETS (1),
|
2318 |
|
|
.USE_FILL_LEVEL (0),
|
2319 |
|
|
.EMPTY_LATENCY (1),
|
2320 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2321 |
|
|
.USE_STORE_FORWARD (0),
|
2322 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2323 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2324 |
|
|
) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2325 |
|
|
.clk (clk_clk), // clk.clk
|
2326 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2327 |
|
|
.in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2328 |
|
|
.in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2329 |
|
|
.in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2330 |
|
|
.in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2331 |
|
|
.in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2332 |
|
|
.out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2333 |
|
|
.out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2334 |
|
|
.out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2335 |
|
|
.out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2336 |
|
|
.out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2337 |
|
|
.csr_address (2'b00), // (terminated)
|
2338 |
|
|
.csr_read (1'b0), // (terminated)
|
2339 |
|
|
.csr_write (1'b0), // (terminated)
|
2340 |
|
|
.csr_readdata (), // (terminated)
|
2341 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2342 |
|
|
.almost_full_data (), // (terminated)
|
2343 |
|
|
.almost_empty_data (), // (terminated)
|
2344 |
|
|
.in_empty (1'b0), // (terminated)
|
2345 |
|
|
.out_empty (), // (terminated)
|
2346 |
|
|
.in_error (1'b0), // (terminated)
|
2347 |
|
|
.out_error (), // (terminated)
|
2348 |
|
|
.in_channel (1'b0), // (terminated)
|
2349 |
|
|
.out_channel () // (terminated)
|
2350 |
|
|
);
|
2351 |
|
|
|
2352 |
|
|
altera_merlin_slave_agent #(
|
2353 |
|
|
.PKT_DATA_H (31),
|
2354 |
|
|
.PKT_DATA_L (0),
|
2355 |
|
|
.PKT_BEGIN_BURST (76),
|
2356 |
|
|
.PKT_SYMBOL_W (8),
|
2357 |
|
|
.PKT_BYTEEN_H (35),
|
2358 |
|
|
.PKT_BYTEEN_L (32),
|
2359 |
|
|
.PKT_ADDR_H (56),
|
2360 |
|
|
.PKT_ADDR_L (36),
|
2361 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2362 |
|
|
.PKT_TRANS_POSTED (58),
|
2363 |
|
|
.PKT_TRANS_WRITE (59),
|
2364 |
|
|
.PKT_TRANS_READ (60),
|
2365 |
|
|
.PKT_TRANS_LOCK (61),
|
2366 |
|
|
.PKT_SRC_ID_H (80),
|
2367 |
|
|
.PKT_SRC_ID_L (78),
|
2368 |
|
|
.PKT_DEST_ID_H (83),
|
2369 |
|
|
.PKT_DEST_ID_L (81),
|
2370 |
|
|
.PKT_BURSTWRAP_H (68),
|
2371 |
|
|
.PKT_BURSTWRAP_L (66),
|
2372 |
|
|
.PKT_BYTE_CNT_H (65),
|
2373 |
|
|
.PKT_BYTE_CNT_L (63),
|
2374 |
|
|
.PKT_PROTECTION_H (87),
|
2375 |
|
|
.PKT_PROTECTION_L (85),
|
2376 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2377 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2378 |
|
|
.PKT_BURST_SIZE_H (71),
|
2379 |
|
|
.PKT_BURST_SIZE_L (69),
|
2380 |
|
|
.ST_CHANNEL_W (8),
|
2381 |
|
|
.ST_DATA_W (94),
|
2382 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2383 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2384 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2385 |
|
|
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent (
|
2386 |
|
|
.clk (clk_clk), // clk.clk
|
2387 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2388 |
|
|
.m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2389 |
|
|
.m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2390 |
|
|
.m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2391 |
|
|
.m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2392 |
|
|
.m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2393 |
|
|
.m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2394 |
|
|
.m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2395 |
|
|
.m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2396 |
|
|
.m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2397 |
|
|
.m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2398 |
|
|
.m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2399 |
|
|
.rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2400 |
|
|
.rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2401 |
|
|
.rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2402 |
|
|
.rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2403 |
|
|
.rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2404 |
|
|
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
|
2405 |
|
|
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
|
2406 |
|
|
.cp_data (cmd_xbar_demux_001_src5_data), // .data
|
2407 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
|
2408 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
|
2409 |
|
|
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
|
2410 |
|
|
.rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2411 |
|
|
.rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2412 |
|
|
.rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2413 |
|
|
.rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2414 |
|
|
.rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2415 |
|
|
.rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2416 |
|
|
.rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2417 |
|
|
.rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2418 |
|
|
.rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2419 |
|
|
.rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2420 |
|
|
.rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2421 |
|
|
.rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2422 |
|
|
.rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2423 |
|
|
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2424 |
|
|
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2425 |
|
|
.rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2426 |
|
|
);
|
2427 |
|
|
|
2428 |
|
|
altera_avalon_sc_fifo #(
|
2429 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2430 |
|
|
.BITS_PER_SYMBOL (95),
|
2431 |
|
|
.FIFO_DEPTH (2),
|
2432 |
|
|
.CHANNEL_WIDTH (0),
|
2433 |
|
|
.ERROR_WIDTH (0),
|
2434 |
|
|
.USE_PACKETS (1),
|
2435 |
|
|
.USE_FILL_LEVEL (0),
|
2436 |
|
|
.EMPTY_LATENCY (1),
|
2437 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2438 |
|
|
.USE_STORE_FORWARD (0),
|
2439 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2440 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2441 |
|
|
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2442 |
|
|
.clk (clk_clk), // clk.clk
|
2443 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2444 |
|
|
.in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2445 |
|
|
.in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2446 |
|
|
.in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2447 |
|
|
.in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2448 |
|
|
.in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2449 |
|
|
.out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2450 |
|
|
.out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2451 |
|
|
.out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2452 |
|
|
.out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2453 |
|
|
.out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2454 |
|
|
.csr_address (2'b00), // (terminated)
|
2455 |
|
|
.csr_read (1'b0), // (terminated)
|
2456 |
|
|
.csr_write (1'b0), // (terminated)
|
2457 |
|
|
.csr_readdata (), // (terminated)
|
2458 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2459 |
|
|
.almost_full_data (), // (terminated)
|
2460 |
|
|
.almost_empty_data (), // (terminated)
|
2461 |
|
|
.in_empty (1'b0), // (terminated)
|
2462 |
|
|
.out_empty (), // (terminated)
|
2463 |
|
|
.in_error (1'b0), // (terminated)
|
2464 |
|
|
.out_error (), // (terminated)
|
2465 |
|
|
.in_channel (1'b0), // (terminated)
|
2466 |
|
|
.out_channel () // (terminated)
|
2467 |
|
|
);
|
2468 |
|
|
|
2469 |
|
|
altera_merlin_slave_agent #(
|
2470 |
|
|
.PKT_DATA_H (31),
|
2471 |
|
|
.PKT_DATA_L (0),
|
2472 |
|
|
.PKT_BEGIN_BURST (76),
|
2473 |
|
|
.PKT_SYMBOL_W (8),
|
2474 |
|
|
.PKT_BYTEEN_H (35),
|
2475 |
|
|
.PKT_BYTEEN_L (32),
|
2476 |
|
|
.PKT_ADDR_H (56),
|
2477 |
|
|
.PKT_ADDR_L (36),
|
2478 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2479 |
|
|
.PKT_TRANS_POSTED (58),
|
2480 |
|
|
.PKT_TRANS_WRITE (59),
|
2481 |
|
|
.PKT_TRANS_READ (60),
|
2482 |
|
|
.PKT_TRANS_LOCK (61),
|
2483 |
|
|
.PKT_SRC_ID_H (80),
|
2484 |
|
|
.PKT_SRC_ID_L (78),
|
2485 |
|
|
.PKT_DEST_ID_H (83),
|
2486 |
|
|
.PKT_DEST_ID_L (81),
|
2487 |
|
|
.PKT_BURSTWRAP_H (68),
|
2488 |
|
|
.PKT_BURSTWRAP_L (66),
|
2489 |
|
|
.PKT_BYTE_CNT_H (65),
|
2490 |
|
|
.PKT_BYTE_CNT_L (63),
|
2491 |
|
|
.PKT_PROTECTION_H (87),
|
2492 |
|
|
.PKT_PROTECTION_L (85),
|
2493 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2494 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2495 |
|
|
.PKT_BURST_SIZE_H (71),
|
2496 |
|
|
.PKT_BURST_SIZE_L (69),
|
2497 |
|
|
.ST_CHANNEL_W (8),
|
2498 |
|
|
.ST_DATA_W (94),
|
2499 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2500 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2501 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2502 |
|
|
) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
|
2503 |
|
|
.clk (clk_clk), // clk.clk
|
2504 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2505 |
|
|
.m0_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2506 |
|
|
.m0_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2507 |
|
|
.m0_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2508 |
|
|
.m0_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2509 |
|
|
.m0_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2510 |
|
|
.m0_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2511 |
|
|
.m0_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2512 |
|
|
.m0_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2513 |
|
|
.m0_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2514 |
|
|
.m0_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2515 |
|
|
.m0_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2516 |
|
|
.rp_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2517 |
|
|
.rp_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2518 |
|
|
.rp_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2519 |
|
|
.rp_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2520 |
|
|
.rp_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2521 |
|
|
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
|
2522 |
|
|
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
|
2523 |
|
|
.cp_data (cmd_xbar_demux_001_src6_data), // .data
|
2524 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
|
2525 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
|
2526 |
|
|
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
|
2527 |
|
|
.rf_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2528 |
|
|
.rf_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2529 |
|
|
.rf_sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2530 |
|
|
.rf_sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2531 |
|
|
.rf_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2532 |
|
|
.rf_source_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2533 |
|
|
.rf_source_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2534 |
|
|
.rf_source_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2535 |
|
|
.rf_source_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2536 |
|
|
.rf_source_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2537 |
|
|
.rdata_fifo_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2538 |
|
|
.rdata_fifo_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2539 |
|
|
.rdata_fifo_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2540 |
|
|
.rdata_fifo_src_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2541 |
|
|
.rdata_fifo_src_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2542 |
|
|
.rdata_fifo_src_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2543 |
|
|
);
|
2544 |
|
|
|
2545 |
|
|
altera_avalon_sc_fifo #(
|
2546 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2547 |
|
|
.BITS_PER_SYMBOL (95),
|
2548 |
|
|
.FIFO_DEPTH (2),
|
2549 |
|
|
.CHANNEL_WIDTH (0),
|
2550 |
|
|
.ERROR_WIDTH (0),
|
2551 |
|
|
.USE_PACKETS (1),
|
2552 |
|
|
.USE_FILL_LEVEL (0),
|
2553 |
|
|
.EMPTY_LATENCY (1),
|
2554 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2555 |
|
|
.USE_STORE_FORWARD (0),
|
2556 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2557 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2558 |
|
|
) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2559 |
|
|
.clk (clk_clk), // clk.clk
|
2560 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2561 |
|
|
.in_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2562 |
|
|
.in_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2563 |
|
|
.in_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2564 |
|
|
.in_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2565 |
|
|
.in_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2566 |
|
|
.out_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2567 |
|
|
.out_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2568 |
|
|
.out_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2569 |
|
|
.out_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2570 |
|
|
.out_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2571 |
|
|
.csr_address (2'b00), // (terminated)
|
2572 |
|
|
.csr_read (1'b0), // (terminated)
|
2573 |
|
|
.csr_write (1'b0), // (terminated)
|
2574 |
|
|
.csr_readdata (), // (terminated)
|
2575 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2576 |
|
|
.almost_full_data (), // (terminated)
|
2577 |
|
|
.almost_empty_data (), // (terminated)
|
2578 |
|
|
.in_empty (1'b0), // (terminated)
|
2579 |
|
|
.out_empty (), // (terminated)
|
2580 |
|
|
.in_error (1'b0), // (terminated)
|
2581 |
|
|
.out_error (), // (terminated)
|
2582 |
|
|
.in_channel (1'b0), // (terminated)
|
2583 |
|
|
.out_channel () // (terminated)
|
2584 |
|
|
);
|
2585 |
|
|
|
2586 |
|
|
altera_merlin_slave_agent #(
|
2587 |
|
|
.PKT_DATA_H (31),
|
2588 |
|
|
.PKT_DATA_L (0),
|
2589 |
|
|
.PKT_BEGIN_BURST (76),
|
2590 |
|
|
.PKT_SYMBOL_W (8),
|
2591 |
|
|
.PKT_BYTEEN_H (35),
|
2592 |
|
|
.PKT_BYTEEN_L (32),
|
2593 |
|
|
.PKT_ADDR_H (56),
|
2594 |
|
|
.PKT_ADDR_L (36),
|
2595 |
|
|
.PKT_TRANS_COMPRESSED_READ (57),
|
2596 |
|
|
.PKT_TRANS_POSTED (58),
|
2597 |
|
|
.PKT_TRANS_WRITE (59),
|
2598 |
|
|
.PKT_TRANS_READ (60),
|
2599 |
|
|
.PKT_TRANS_LOCK (61),
|
2600 |
|
|
.PKT_SRC_ID_H (80),
|
2601 |
|
|
.PKT_SRC_ID_L (78),
|
2602 |
|
|
.PKT_DEST_ID_H (83),
|
2603 |
|
|
.PKT_DEST_ID_L (81),
|
2604 |
|
|
.PKT_BURSTWRAP_H (68),
|
2605 |
|
|
.PKT_BURSTWRAP_L (66),
|
2606 |
|
|
.PKT_BYTE_CNT_H (65),
|
2607 |
|
|
.PKT_BYTE_CNT_L (63),
|
2608 |
|
|
.PKT_PROTECTION_H (87),
|
2609 |
|
|
.PKT_PROTECTION_L (85),
|
2610 |
|
|
.PKT_RESPONSE_STATUS_H (93),
|
2611 |
|
|
.PKT_RESPONSE_STATUS_L (92),
|
2612 |
|
|
.PKT_BURST_SIZE_H (71),
|
2613 |
|
|
.PKT_BURST_SIZE_L (69),
|
2614 |
|
|
.ST_CHANNEL_W (8),
|
2615 |
|
|
.ST_DATA_W (94),
|
2616 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2617 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2618 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2619 |
|
|
) timer_1_s1_translator_avalon_universal_slave_0_agent (
|
2620 |
|
|
.clk (clk_clk), // clk.clk
|
2621 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2622 |
|
|
.m0_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2623 |
|
|
.m0_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2624 |
|
|
.m0_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2625 |
|
|
.m0_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2626 |
|
|
.m0_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2627 |
|
|
.m0_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2628 |
|
|
.m0_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2629 |
|
|
.m0_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2630 |
|
|
.m0_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2631 |
|
|
.m0_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2632 |
|
|
.m0_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2633 |
|
|
.rp_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2634 |
|
|
.rp_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2635 |
|
|
.rp_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2636 |
|
|
.rp_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2637 |
|
|
.rp_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2638 |
|
|
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
|
2639 |
|
|
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
|
2640 |
|
|
.cp_data (cmd_xbar_demux_001_src7_data), // .data
|
2641 |
|
|
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
|
2642 |
|
|
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
|
2643 |
|
|
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
|
2644 |
|
|
.rf_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2645 |
|
|
.rf_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2646 |
|
|
.rf_sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2647 |
|
|
.rf_sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2648 |
|
|
.rf_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2649 |
|
|
.rf_source_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2650 |
|
|
.rf_source_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2651 |
|
|
.rf_source_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2652 |
|
|
.rf_source_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2653 |
|
|
.rf_source_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2654 |
|
|
.rdata_fifo_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2655 |
|
|
.rdata_fifo_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2656 |
|
|
.rdata_fifo_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2657 |
|
|
.rdata_fifo_src_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2658 |
|
|
.rdata_fifo_src_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2659 |
|
|
.rdata_fifo_src_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2660 |
|
|
);
|
2661 |
|
|
|
2662 |
|
|
altera_avalon_sc_fifo #(
|
2663 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2664 |
|
|
.BITS_PER_SYMBOL (95),
|
2665 |
|
|
.FIFO_DEPTH (2),
|
2666 |
|
|
.CHANNEL_WIDTH (0),
|
2667 |
|
|
.ERROR_WIDTH (0),
|
2668 |
|
|
.USE_PACKETS (1),
|
2669 |
|
|
.USE_FILL_LEVEL (0),
|
2670 |
|
|
.EMPTY_LATENCY (1),
|
2671 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2672 |
|
|
.USE_STORE_FORWARD (0),
|
2673 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2674 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2675 |
|
|
) timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2676 |
|
|
.clk (clk_clk), // clk.clk
|
2677 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2678 |
|
|
.in_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2679 |
|
|
.in_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2680 |
|
|
.in_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2681 |
|
|
.in_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2682 |
|
|
.in_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2683 |
|
|
.out_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2684 |
|
|
.out_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2685 |
|
|
.out_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2686 |
|
|
.out_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2687 |
|
|
.out_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2688 |
|
|
.csr_address (2'b00), // (terminated)
|
2689 |
|
|
.csr_read (1'b0), // (terminated)
|
2690 |
|
|
.csr_write (1'b0), // (terminated)
|
2691 |
|
|
.csr_readdata (), // (terminated)
|
2692 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2693 |
|
|
.almost_full_data (), // (terminated)
|
2694 |
|
|
.almost_empty_data (), // (terminated)
|
2695 |
|
|
.in_empty (1'b0), // (terminated)
|
2696 |
|
|
.out_empty (), // (terminated)
|
2697 |
|
|
.in_error (1'b0), // (terminated)
|
2698 |
|
|
.out_error (), // (terminated)
|
2699 |
|
|
.in_channel (1'b0), // (terminated)
|
2700 |
|
|
.out_channel () // (terminated)
|
2701 |
|
|
);
|
2702 |
|
|
|
2703 |
|
|
altera_merlin_master_agent #(
|
2704 |
|
|
.PKT_PROTECTION_H (94),
|
2705 |
|
|
.PKT_PROTECTION_L (92),
|
2706 |
|
|
.PKT_BEGIN_BURST (87),
|
2707 |
|
|
.PKT_BURSTWRAP_H (79),
|
2708 |
|
|
.PKT_BURSTWRAP_L (77),
|
2709 |
|
|
.PKT_BURST_SIZE_H (82),
|
2710 |
|
|
.PKT_BURST_SIZE_L (80),
|
2711 |
|
|
.PKT_BURST_TYPE_H (84),
|
2712 |
|
|
.PKT_BURST_TYPE_L (83),
|
2713 |
|
|
.PKT_BYTE_CNT_H (76),
|
2714 |
|
|
.PKT_BYTE_CNT_L (74),
|
2715 |
|
|
.PKT_ADDR_H (67),
|
2716 |
|
|
.PKT_ADDR_L (36),
|
2717 |
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
2718 |
|
|
.PKT_TRANS_POSTED (69),
|
2719 |
|
|
.PKT_TRANS_WRITE (70),
|
2720 |
|
|
.PKT_TRANS_READ (71),
|
2721 |
|
|
.PKT_TRANS_LOCK (72),
|
2722 |
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
2723 |
|
|
.PKT_DATA_H (31),
|
2724 |
|
|
.PKT_DATA_L (0),
|
2725 |
|
|
.PKT_BYTEEN_H (35),
|
2726 |
|
|
.PKT_BYTEEN_L (32),
|
2727 |
|
|
.PKT_SRC_ID_H (89),
|
2728 |
|
|
.PKT_SRC_ID_L (89),
|
2729 |
|
|
.PKT_DEST_ID_H (90),
|
2730 |
|
|
.PKT_DEST_ID_L (90),
|
2731 |
|
|
.PKT_THREAD_ID_H (91),
|
2732 |
|
|
.PKT_THREAD_ID_L (91),
|
2733 |
|
|
.PKT_CACHE_H (98),
|
2734 |
|
|
.PKT_CACHE_L (95),
|
2735 |
|
|
.PKT_DATA_SIDEBAND_H (86),
|
2736 |
|
|
.PKT_DATA_SIDEBAND_L (86),
|
2737 |
|
|
.PKT_QOS_H (88),
|
2738 |
|
|
.PKT_QOS_L (88),
|
2739 |
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
2740 |
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
2741 |
|
|
.ST_DATA_W (101),
|
2742 |
|
|
.ST_CHANNEL_W (2),
|
2743 |
|
|
.AV_BURSTCOUNT_W (3),
|
2744 |
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
2745 |
|
|
.ID (0),
|
2746 |
|
|
.BURSTWRAP_VALUE (7),
|
2747 |
|
|
.CACHE_VALUE (4'b0000)
|
2748 |
|
|
) hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent (
|
2749 |
|
|
.clk (clk_clk), // clk.clk
|
2750 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2751 |
|
|
.av_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
|
2752 |
|
|
.av_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write
|
2753 |
|
|
.av_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read
|
2754 |
|
|
.av_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
|
2755 |
|
|
.av_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
|
2756 |
|
|
.av_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
2757 |
|
|
.av_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
2758 |
|
|
.av_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
2759 |
|
|
.av_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
2760 |
|
|
.av_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
2761 |
|
|
.av_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
|
2762 |
|
|
.cp_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
|
2763 |
|
|
.cp_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
2764 |
|
|
.cp_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
2765 |
|
|
.cp_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
2766 |
|
|
.cp_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
|
2767 |
|
|
.rp_valid (rsp_xbar_demux_008_src0_valid), // rp.valid
|
2768 |
|
|
.rp_data (rsp_xbar_demux_008_src0_data), // .data
|
2769 |
|
|
.rp_channel (rsp_xbar_demux_008_src0_channel), // .channel
|
2770 |
|
|
.rp_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
|
2771 |
|
|
.rp_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
|
2772 |
|
|
.rp_ready (rsp_xbar_demux_008_src0_ready) // .ready
|
2773 |
|
|
);
|
2774 |
|
|
|
2775 |
|
|
altera_merlin_master_agent #(
|
2776 |
|
|
.PKT_PROTECTION_H (94),
|
2777 |
|
|
.PKT_PROTECTION_L (92),
|
2778 |
|
|
.PKT_BEGIN_BURST (87),
|
2779 |
|
|
.PKT_BURSTWRAP_H (79),
|
2780 |
|
|
.PKT_BURSTWRAP_L (77),
|
2781 |
|
|
.PKT_BURST_SIZE_H (82),
|
2782 |
|
|
.PKT_BURST_SIZE_L (80),
|
2783 |
|
|
.PKT_BURST_TYPE_H (84),
|
2784 |
|
|
.PKT_BURST_TYPE_L (83),
|
2785 |
|
|
.PKT_BYTE_CNT_H (76),
|
2786 |
|
|
.PKT_BYTE_CNT_L (74),
|
2787 |
|
|
.PKT_ADDR_H (67),
|
2788 |
|
|
.PKT_ADDR_L (36),
|
2789 |
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
2790 |
|
|
.PKT_TRANS_POSTED (69),
|
2791 |
|
|
.PKT_TRANS_WRITE (70),
|
2792 |
|
|
.PKT_TRANS_READ (71),
|
2793 |
|
|
.PKT_TRANS_LOCK (72),
|
2794 |
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
2795 |
|
|
.PKT_DATA_H (31),
|
2796 |
|
|
.PKT_DATA_L (0),
|
2797 |
|
|
.PKT_BYTEEN_H (35),
|
2798 |
|
|
.PKT_BYTEEN_L (32),
|
2799 |
|
|
.PKT_SRC_ID_H (89),
|
2800 |
|
|
.PKT_SRC_ID_L (89),
|
2801 |
|
|
.PKT_DEST_ID_H (90),
|
2802 |
|
|
.PKT_DEST_ID_L (90),
|
2803 |
|
|
.PKT_THREAD_ID_H (91),
|
2804 |
|
|
.PKT_THREAD_ID_L (91),
|
2805 |
|
|
.PKT_CACHE_H (98),
|
2806 |
|
|
.PKT_CACHE_L (95),
|
2807 |
|
|
.PKT_DATA_SIDEBAND_H (86),
|
2808 |
|
|
.PKT_DATA_SIDEBAND_L (86),
|
2809 |
|
|
.PKT_QOS_H (88),
|
2810 |
|
|
.PKT_QOS_L (88),
|
2811 |
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
2812 |
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
2813 |
|
|
.ST_DATA_W (101),
|
2814 |
|
|
.ST_CHANNEL_W (2),
|
2815 |
|
|
.AV_BURSTCOUNT_W (3),
|
2816 |
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
2817 |
|
|
.ID (1),
|
2818 |
|
|
.BURSTWRAP_VALUE (7),
|
2819 |
|
|
.CACHE_VALUE (4'b0000)
|
2820 |
|
|
) hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent (
|
2821 |
|
|
.clk (clk_clk), // clk.clk
|
2822 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2823 |
|
|
.av_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // av.address
|
2824 |
|
|
.av_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write
|
2825 |
|
|
.av_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read
|
2826 |
|
|
.av_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata
|
2827 |
|
|
.av_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata
|
2828 |
|
|
.av_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
2829 |
|
|
.av_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
2830 |
|
|
.av_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable
|
2831 |
|
|
.av_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount
|
2832 |
|
|
.av_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
2833 |
|
|
.av_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock
|
2834 |
|
|
.cp_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
|
2835 |
|
|
.cp_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data
|
2836 |
|
|
.cp_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
2837 |
|
|
.cp_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
2838 |
|
|
.cp_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // .ready
|
2839 |
|
|
.rp_valid (rsp_xbar_demux_008_src1_valid), // rp.valid
|
2840 |
|
|
.rp_data (rsp_xbar_demux_008_src1_data), // .data
|
2841 |
|
|
.rp_channel (rsp_xbar_demux_008_src1_channel), // .channel
|
2842 |
|
|
.rp_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket
|
2843 |
|
|
.rp_endofpacket (rsp_xbar_demux_008_src1_endofpacket), // .endofpacket
|
2844 |
|
|
.rp_ready (rsp_xbar_demux_008_src1_ready) // .ready
|
2845 |
|
|
);
|
2846 |
|
|
|
2847 |
|
|
altera_merlin_slave_agent #(
|
2848 |
|
|
.PKT_DATA_H (31),
|
2849 |
|
|
.PKT_DATA_L (0),
|
2850 |
|
|
.PKT_BEGIN_BURST (87),
|
2851 |
|
|
.PKT_SYMBOL_W (8),
|
2852 |
|
|
.PKT_BYTEEN_H (35),
|
2853 |
|
|
.PKT_BYTEEN_L (32),
|
2854 |
|
|
.PKT_ADDR_H (67),
|
2855 |
|
|
.PKT_ADDR_L (36),
|
2856 |
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
2857 |
|
|
.PKT_TRANS_POSTED (69),
|
2858 |
|
|
.PKT_TRANS_WRITE (70),
|
2859 |
|
|
.PKT_TRANS_READ (71),
|
2860 |
|
|
.PKT_TRANS_LOCK (72),
|
2861 |
|
|
.PKT_SRC_ID_H (89),
|
2862 |
|
|
.PKT_SRC_ID_L (89),
|
2863 |
|
|
.PKT_DEST_ID_H (90),
|
2864 |
|
|
.PKT_DEST_ID_L (90),
|
2865 |
|
|
.PKT_BURSTWRAP_H (79),
|
2866 |
|
|
.PKT_BURSTWRAP_L (77),
|
2867 |
|
|
.PKT_BYTE_CNT_H (76),
|
2868 |
|
|
.PKT_BYTE_CNT_L (74),
|
2869 |
|
|
.PKT_PROTECTION_H (94),
|
2870 |
|
|
.PKT_PROTECTION_L (92),
|
2871 |
|
|
.PKT_RESPONSE_STATUS_H (100),
|
2872 |
|
|
.PKT_RESPONSE_STATUS_L (99),
|
2873 |
|
|
.PKT_BURST_SIZE_H (82),
|
2874 |
|
|
.PKT_BURST_SIZE_L (80),
|
2875 |
|
|
.ST_CHANNEL_W (2),
|
2876 |
|
|
.ST_DATA_W (101),
|
2877 |
|
|
.AVS_BURSTCOUNT_W (3),
|
2878 |
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
2879 |
|
|
.PREVENT_FIFO_OVERFLOW (1)
|
2880 |
|
|
) onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent (
|
2881 |
|
|
.clk (clk_clk), // clk.clk
|
2882 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2883 |
|
|
.m0_address (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
|
2884 |
|
|
.m0_burstcount (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
|
2885 |
|
|
.m0_byteenable (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
|
2886 |
|
|
.m0_debugaccess (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
|
2887 |
|
|
.m0_lock (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
|
2888 |
|
|
.m0_readdata (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
|
2889 |
|
|
.m0_readdatavalid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
|
2890 |
|
|
.m0_read (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read
|
2891 |
|
|
.m0_waitrequest (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
|
2892 |
|
|
.m0_writedata (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
|
2893 |
|
|
.m0_write (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write
|
2894 |
|
|
.rp_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
|
2895 |
|
|
.rp_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
|
2896 |
|
|
.rp_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2897 |
|
|
.rp_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
2898 |
|
|
.rp_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
2899 |
|
|
.cp_ready (cmd_xbar_mux_008_src_ready), // cp.ready
|
2900 |
|
|
.cp_valid (cmd_xbar_mux_008_src_valid), // .valid
|
2901 |
|
|
.cp_data (cmd_xbar_mux_008_src_data), // .data
|
2902 |
|
|
.cp_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket
|
2903 |
|
|
.cp_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket
|
2904 |
|
|
.cp_channel (cmd_xbar_mux_008_src_channel), // .channel
|
2905 |
|
|
.rf_sink_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
|
2906 |
|
|
.rf_sink_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2907 |
|
|
.rf_sink_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2908 |
|
|
.rf_sink_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2909 |
|
|
.rf_sink_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
|
2910 |
|
|
.rf_source_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
|
2911 |
|
|
.rf_source_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2912 |
|
|
.rf_source_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2913 |
|
|
.rf_source_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2914 |
|
|
.rf_source_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
|
2915 |
|
|
.rdata_fifo_sink_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
|
2916 |
|
|
.rdata_fifo_sink_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2917 |
|
|
.rdata_fifo_sink_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
|
2918 |
|
|
.rdata_fifo_src_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
2919 |
|
|
.rdata_fifo_src_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
|
2920 |
|
|
.rdata_fifo_src_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
|
2921 |
|
|
);
|
2922 |
|
|
|
2923 |
|
|
altera_avalon_sc_fifo #(
|
2924 |
|
|
.SYMBOLS_PER_BEAT (1),
|
2925 |
|
|
.BITS_PER_SYMBOL (102),
|
2926 |
|
|
.FIFO_DEPTH (2),
|
2927 |
|
|
.CHANNEL_WIDTH (0),
|
2928 |
|
|
.ERROR_WIDTH (0),
|
2929 |
|
|
.USE_PACKETS (1),
|
2930 |
|
|
.USE_FILL_LEVEL (0),
|
2931 |
|
|
.EMPTY_LATENCY (1),
|
2932 |
|
|
.USE_MEMORY_BLOCKS (0),
|
2933 |
|
|
.USE_STORE_FORWARD (0),
|
2934 |
|
|
.USE_ALMOST_FULL_IF (0),
|
2935 |
|
|
.USE_ALMOST_EMPTY_IF (0)
|
2936 |
|
|
) onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo (
|
2937 |
|
|
.clk (clk_clk), // clk.clk
|
2938 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2939 |
|
|
.in_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
|
2940 |
|
|
.in_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
|
2941 |
|
|
.in_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
|
2942 |
|
|
.in_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
|
2943 |
|
|
.in_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
|
2944 |
|
|
.out_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
|
2945 |
|
|
.out_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
|
2946 |
|
|
.out_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
|
2947 |
|
|
.out_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
2948 |
|
|
.out_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
2949 |
|
|
.csr_address (2'b00), // (terminated)
|
2950 |
|
|
.csr_read (1'b0), // (terminated)
|
2951 |
|
|
.csr_write (1'b0), // (terminated)
|
2952 |
|
|
.csr_readdata (), // (terminated)
|
2953 |
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
2954 |
|
|
.almost_full_data (), // (terminated)
|
2955 |
|
|
.almost_empty_data (), // (terminated)
|
2956 |
|
|
.in_empty (1'b0), // (terminated)
|
2957 |
|
|
.out_empty (), // (terminated)
|
2958 |
|
|
.in_error (1'b0), // (terminated)
|
2959 |
|
|
.out_error (), // (terminated)
|
2960 |
|
|
.in_channel (1'b0), // (terminated)
|
2961 |
|
|
.out_channel () // (terminated)
|
2962 |
|
|
);
|
2963 |
|
|
|
2964 |
|
|
nios2_sram_addr_router addr_router (
|
2965 |
|
|
.sink_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
|
2966 |
|
|
.sink_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
|
2967 |
|
|
.sink_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
2968 |
|
|
.sink_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
2969 |
|
|
.sink_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
2970 |
|
|
.clk (clk_clk), // clk.clk
|
2971 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2972 |
|
|
.src_ready (addr_router_src_ready), // src.ready
|
2973 |
|
|
.src_valid (addr_router_src_valid), // .valid
|
2974 |
|
|
.src_data (addr_router_src_data), // .data
|
2975 |
|
|
.src_channel (addr_router_src_channel), // .channel
|
2976 |
|
|
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
|
2977 |
|
|
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
|
2978 |
|
|
);
|
2979 |
|
|
|
2980 |
|
|
nios2_sram_addr_router_001 addr_router_001 (
|
2981 |
|
|
.sink_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
|
2982 |
|
|
.sink_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
|
2983 |
|
|
.sink_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
2984 |
|
|
.sink_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
2985 |
|
|
.sink_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
2986 |
|
|
.clk (clk_clk), // clk.clk
|
2987 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
2988 |
|
|
.src_ready (addr_router_001_src_ready), // src.ready
|
2989 |
|
|
.src_valid (addr_router_001_src_valid), // .valid
|
2990 |
|
|
.src_data (addr_router_001_src_data), // .data
|
2991 |
|
|
.src_channel (addr_router_001_src_channel), // .channel
|
2992 |
|
|
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
|
2993 |
|
|
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
|
2994 |
|
|
);
|
2995 |
|
|
|
2996 |
|
|
nios2_sram_id_router id_router (
|
2997 |
|
|
.sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
2998 |
|
|
.sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
2999 |
|
|
.sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3000 |
|
|
.sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3001 |
|
|
.sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3002 |
|
|
.clk (clk_clk), // clk.clk
|
3003 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3004 |
|
|
.src_ready (id_router_src_ready), // src.ready
|
3005 |
|
|
.src_valid (id_router_src_valid), // .valid
|
3006 |
|
|
.src_data (id_router_src_data), // .data
|
3007 |
|
|
.src_channel (id_router_src_channel), // .channel
|
3008 |
|
|
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
|
3009 |
|
|
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
|
3010 |
|
|
);
|
3011 |
|
|
|
3012 |
|
|
nios2_sram_id_router_001 id_router_001 (
|
3013 |
|
|
.sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3014 |
|
|
.sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3015 |
|
|
.sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3016 |
|
|
.sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3017 |
|
|
.sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3018 |
|
|
.clk (clk_clk), // clk.clk
|
3019 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3020 |
|
|
.src_ready (id_router_001_src_ready), // src.ready
|
3021 |
|
|
.src_valid (id_router_001_src_valid), // .valid
|
3022 |
|
|
.src_data (id_router_001_src_data), // .data
|
3023 |
|
|
.src_channel (id_router_001_src_channel), // .channel
|
3024 |
|
|
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
|
3025 |
|
|
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
|
3026 |
|
|
);
|
3027 |
|
|
|
3028 |
|
|
nios2_sram_id_router_002 id_router_002 (
|
3029 |
|
|
.sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3030 |
|
|
.sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3031 |
|
|
.sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3032 |
|
|
.sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3033 |
|
|
.sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3034 |
|
|
.clk (clk_clk), // clk.clk
|
3035 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3036 |
|
|
.src_ready (id_router_002_src_ready), // src.ready
|
3037 |
|
|
.src_valid (id_router_002_src_valid), // .valid
|
3038 |
|
|
.src_data (id_router_002_src_data), // .data
|
3039 |
|
|
.src_channel (id_router_002_src_channel), // .channel
|
3040 |
|
|
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
|
3041 |
|
|
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
|
3042 |
|
|
);
|
3043 |
|
|
|
3044 |
|
|
nios2_sram_id_router_002 id_router_003 (
|
3045 |
|
|
.sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3046 |
|
|
.sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3047 |
|
|
.sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3048 |
|
|
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3049 |
|
|
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3050 |
|
|
.clk (clk_clk), // clk.clk
|
3051 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3052 |
|
|
.src_ready (id_router_003_src_ready), // src.ready
|
3053 |
|
|
.src_valid (id_router_003_src_valid), // .valid
|
3054 |
|
|
.src_data (id_router_003_src_data), // .data
|
3055 |
|
|
.src_channel (id_router_003_src_channel), // .channel
|
3056 |
|
|
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
|
3057 |
|
|
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
|
3058 |
|
|
);
|
3059 |
|
|
|
3060 |
|
|
nios2_sram_id_router_002 id_router_004 (
|
3061 |
|
|
.sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3062 |
|
|
.sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3063 |
|
|
.sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3064 |
|
|
.sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3065 |
|
|
.sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3066 |
|
|
.clk (clk_clk), // clk.clk
|
3067 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3068 |
|
|
.src_ready (id_router_004_src_ready), // src.ready
|
3069 |
|
|
.src_valid (id_router_004_src_valid), // .valid
|
3070 |
|
|
.src_data (id_router_004_src_data), // .data
|
3071 |
|
|
.src_channel (id_router_004_src_channel), // .channel
|
3072 |
|
|
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
|
3073 |
|
|
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
|
3074 |
|
|
);
|
3075 |
|
|
|
3076 |
|
|
nios2_sram_id_router_002 id_router_005 (
|
3077 |
|
|
.sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3078 |
|
|
.sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3079 |
|
|
.sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3080 |
|
|
.sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3081 |
|
|
.sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3082 |
|
|
.clk (clk_clk), // clk.clk
|
3083 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3084 |
|
|
.src_ready (id_router_005_src_ready), // src.ready
|
3085 |
|
|
.src_valid (id_router_005_src_valid), // .valid
|
3086 |
|
|
.src_data (id_router_005_src_data), // .data
|
3087 |
|
|
.src_channel (id_router_005_src_channel), // .channel
|
3088 |
|
|
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
|
3089 |
|
|
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
|
3090 |
|
|
);
|
3091 |
|
|
|
3092 |
|
|
nios2_sram_id_router_002 id_router_006 (
|
3093 |
|
|
.sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3094 |
|
|
.sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3095 |
|
|
.sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3096 |
|
|
.sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3097 |
|
|
.sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3098 |
|
|
.clk (clk_clk), // clk.clk
|
3099 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3100 |
|
|
.src_ready (id_router_006_src_ready), // src.ready
|
3101 |
|
|
.src_valid (id_router_006_src_valid), // .valid
|
3102 |
|
|
.src_data (id_router_006_src_data), // .data
|
3103 |
|
|
.src_channel (id_router_006_src_channel), // .channel
|
3104 |
|
|
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
|
3105 |
|
|
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
|
3106 |
|
|
);
|
3107 |
|
|
|
3108 |
|
|
nios2_sram_id_router_002 id_router_007 (
|
3109 |
|
|
.sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3110 |
|
|
.sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3111 |
|
|
.sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3112 |
|
|
.sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3113 |
|
|
.sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3114 |
|
|
.clk (clk_clk), // clk.clk
|
3115 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3116 |
|
|
.src_ready (id_router_007_src_ready), // src.ready
|
3117 |
|
|
.src_valid (id_router_007_src_valid), // .valid
|
3118 |
|
|
.src_data (id_router_007_src_data), // .data
|
3119 |
|
|
.src_channel (id_router_007_src_channel), // .channel
|
3120 |
|
|
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
|
3121 |
|
|
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
|
3122 |
|
|
);
|
3123 |
|
|
|
3124 |
|
|
nios2_sram_addr_router_002 addr_router_002 (
|
3125 |
|
|
.sink_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
|
3126 |
|
|
.sink_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
|
3127 |
|
|
.sink_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data
|
3128 |
|
|
.sink_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
3129 |
|
|
.sink_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
3130 |
|
|
.clk (clk_clk), // clk.clk
|
3131 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3132 |
|
|
.src_ready (addr_router_002_src_ready), // src.ready
|
3133 |
|
|
.src_valid (addr_router_002_src_valid), // .valid
|
3134 |
|
|
.src_data (addr_router_002_src_data), // .data
|
3135 |
|
|
.src_channel (addr_router_002_src_channel), // .channel
|
3136 |
|
|
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
|
3137 |
|
|
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
|
3138 |
|
|
);
|
3139 |
|
|
|
3140 |
|
|
nios2_sram_addr_router_002 addr_router_003 (
|
3141 |
|
|
.sink_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
|
3142 |
|
|
.sink_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // .valid
|
3143 |
|
|
.sink_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data
|
3144 |
|
|
.sink_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
|
3145 |
|
|
.sink_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
|
3146 |
|
|
.clk (clk_clk), // clk.clk
|
3147 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3148 |
|
|
.src_ready (addr_router_003_src_ready), // src.ready
|
3149 |
|
|
.src_valid (addr_router_003_src_valid), // .valid
|
3150 |
|
|
.src_data (addr_router_003_src_data), // .data
|
3151 |
|
|
.src_channel (addr_router_003_src_channel), // .channel
|
3152 |
|
|
.src_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
|
3153 |
|
|
.src_endofpacket (addr_router_003_src_endofpacket) // .endofpacket
|
3154 |
|
|
);
|
3155 |
|
|
|
3156 |
|
|
nios2_sram_id_router_008 id_router_008 (
|
3157 |
|
|
.sink_ready (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
|
3158 |
|
|
.sink_valid (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
|
3159 |
|
|
.sink_data (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data
|
3160 |
|
|
.sink_startofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
|
3161 |
|
|
.sink_endofpacket (onchip_memory2_0_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
|
3162 |
|
|
.clk (clk_clk), // clk.clk
|
3163 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3164 |
|
|
.src_ready (id_router_008_src_ready), // src.ready
|
3165 |
|
|
.src_valid (id_router_008_src_valid), // .valid
|
3166 |
|
|
.src_data (id_router_008_src_data), // .data
|
3167 |
|
|
.src_channel (id_router_008_src_channel), // .channel
|
3168 |
|
|
.src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
|
3169 |
|
|
.src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
|
3170 |
|
|
);
|
3171 |
|
|
|
3172 |
|
|
altera_merlin_traffic_limiter #(
|
3173 |
|
|
.PKT_DEST_ID_H (83),
|
3174 |
|
|
.PKT_DEST_ID_L (81),
|
3175 |
|
|
.PKT_TRANS_POSTED (58),
|
3176 |
|
|
.PKT_TRANS_WRITE (59),
|
3177 |
|
|
.MAX_OUTSTANDING_RESPONSES (4),
|
3178 |
|
|
.PIPELINED (0),
|
3179 |
|
|
.ST_DATA_W (94),
|
3180 |
|
|
.ST_CHANNEL_W (8),
|
3181 |
|
|
.VALID_WIDTH (8),
|
3182 |
|
|
.ENFORCE_ORDER (1),
|
3183 |
|
|
.PREVENT_HAZARDS (0),
|
3184 |
|
|
.PKT_BYTE_CNT_H (65),
|
3185 |
|
|
.PKT_BYTE_CNT_L (63),
|
3186 |
|
|
.PKT_BYTEEN_H (35),
|
3187 |
|
|
.PKT_BYTEEN_L (32)
|
3188 |
|
|
) limiter (
|
3189 |
|
|
.clk (clk_clk), // clk.clk
|
3190 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3191 |
|
|
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
|
3192 |
|
|
.cmd_sink_valid (addr_router_src_valid), // .valid
|
3193 |
|
|
.cmd_sink_data (addr_router_src_data), // .data
|
3194 |
|
|
.cmd_sink_channel (addr_router_src_channel), // .channel
|
3195 |
|
|
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
|
3196 |
|
|
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
|
3197 |
|
|
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
|
3198 |
|
|
.cmd_src_data (limiter_cmd_src_data), // .data
|
3199 |
|
|
.cmd_src_channel (limiter_cmd_src_channel), // .channel
|
3200 |
|
|
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
|
3201 |
|
|
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
|
3202 |
|
|
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
|
3203 |
|
|
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
|
3204 |
|
|
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
|
3205 |
|
|
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
|
3206 |
|
|
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
|
3207 |
|
|
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
|
3208 |
|
|
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
|
3209 |
|
|
.rsp_src_valid (limiter_rsp_src_valid), // .valid
|
3210 |
|
|
.rsp_src_data (limiter_rsp_src_data), // .data
|
3211 |
|
|
.rsp_src_channel (limiter_rsp_src_channel), // .channel
|
3212 |
|
|
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
|
3213 |
|
|
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
|
3214 |
|
|
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
|
3215 |
|
|
);
|
3216 |
|
|
|
3217 |
|
|
altera_merlin_traffic_limiter #(
|
3218 |
|
|
.PKT_DEST_ID_H (83),
|
3219 |
|
|
.PKT_DEST_ID_L (81),
|
3220 |
|
|
.PKT_TRANS_POSTED (58),
|
3221 |
|
|
.PKT_TRANS_WRITE (59),
|
3222 |
|
|
.MAX_OUTSTANDING_RESPONSES (4),
|
3223 |
|
|
.PIPELINED (0),
|
3224 |
|
|
.ST_DATA_W (94),
|
3225 |
|
|
.ST_CHANNEL_W (8),
|
3226 |
|
|
.VALID_WIDTH (8),
|
3227 |
|
|
.ENFORCE_ORDER (1),
|
3228 |
|
|
.PREVENT_HAZARDS (0),
|
3229 |
|
|
.PKT_BYTE_CNT_H (65),
|
3230 |
|
|
.PKT_BYTE_CNT_L (63),
|
3231 |
|
|
.PKT_BYTEEN_H (35),
|
3232 |
|
|
.PKT_BYTEEN_L (32)
|
3233 |
|
|
) limiter_001 (
|
3234 |
|
|
.clk (clk_clk), // clk.clk
|
3235 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3236 |
|
|
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
|
3237 |
|
|
.cmd_sink_valid (addr_router_001_src_valid), // .valid
|
3238 |
|
|
.cmd_sink_data (addr_router_001_src_data), // .data
|
3239 |
|
|
.cmd_sink_channel (addr_router_001_src_channel), // .channel
|
3240 |
|
|
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
|
3241 |
|
|
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
|
3242 |
|
|
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
|
3243 |
|
|
.cmd_src_data (limiter_001_cmd_src_data), // .data
|
3244 |
|
|
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
|
3245 |
|
|
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
|
3246 |
|
|
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
|
3247 |
|
|
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
|
3248 |
|
|
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
|
3249 |
|
|
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
|
3250 |
|
|
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
|
3251 |
|
|
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
|
3252 |
|
|
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
|
3253 |
|
|
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
|
3254 |
|
|
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
|
3255 |
|
|
.rsp_src_data (limiter_001_rsp_src_data), // .data
|
3256 |
|
|
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
|
3257 |
|
|
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
|
3258 |
|
|
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
|
3259 |
|
|
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
|
3260 |
|
|
);
|
3261 |
|
|
|
3262 |
|
|
altera_merlin_burst_adapter #(
|
3263 |
|
|
.PKT_ADDR_H (38),
|
3264 |
|
|
.PKT_ADDR_L (18),
|
3265 |
|
|
.PKT_BEGIN_BURST (58),
|
3266 |
|
|
.PKT_BYTE_CNT_H (47),
|
3267 |
|
|
.PKT_BYTE_CNT_L (45),
|
3268 |
|
|
.PKT_BYTEEN_H (17),
|
3269 |
|
|
.PKT_BYTEEN_L (16),
|
3270 |
|
|
.PKT_BURST_SIZE_H (53),
|
3271 |
|
|
.PKT_BURST_SIZE_L (51),
|
3272 |
|
|
.PKT_BURST_TYPE_H (55),
|
3273 |
|
|
.PKT_BURST_TYPE_L (54),
|
3274 |
|
|
.PKT_BURSTWRAP_H (50),
|
3275 |
|
|
.PKT_BURSTWRAP_L (48),
|
3276 |
|
|
.PKT_TRANS_COMPRESSED_READ (39),
|
3277 |
|
|
.PKT_TRANS_WRITE (41),
|
3278 |
|
|
.PKT_TRANS_READ (42),
|
3279 |
|
|
.OUT_NARROW_SIZE (0),
|
3280 |
|
|
.IN_NARROW_SIZE (0),
|
3281 |
|
|
.OUT_FIXED (0),
|
3282 |
|
|
.OUT_COMPLETE_WRAP (0),
|
3283 |
|
|
.ST_DATA_W (76),
|
3284 |
|
|
.ST_CHANNEL_W (8),
|
3285 |
|
|
.OUT_BYTE_CNT_H (46),
|
3286 |
|
|
.OUT_BURSTWRAP_H (50),
|
3287 |
|
|
.COMPRESSED_READ_SUPPORT (0),
|
3288 |
|
|
.BYTEENABLE_SYNTHESIS (0),
|
3289 |
|
|
.PIPE_INPUTS (0),
|
3290 |
|
|
.NO_WRAP_SUPPORT (0),
|
3291 |
|
|
.BURSTWRAP_CONST_MASK (3),
|
3292 |
|
|
.BURSTWRAP_CONST_VALUE (3)
|
3293 |
|
|
) burst_adapter (
|
3294 |
|
|
.clk (clk_clk), // cr0.clk
|
3295 |
|
|
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
|
3296 |
|
|
.sink0_valid (width_adapter_src_valid), // sink0.valid
|
3297 |
|
|
.sink0_data (width_adapter_src_data), // .data
|
3298 |
|
|
.sink0_channel (width_adapter_src_channel), // .channel
|
3299 |
|
|
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
|
3300 |
|
|
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
|
3301 |
|
|
.sink0_ready (width_adapter_src_ready), // .ready
|
3302 |
|
|
.source0_valid (burst_adapter_source0_valid), // source0.valid
|
3303 |
|
|
.source0_data (burst_adapter_source0_data), // .data
|
3304 |
|
|
.source0_channel (burst_adapter_source0_channel), // .channel
|
3305 |
|
|
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
|
3306 |
|
|
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
|
3307 |
|
|
.source0_ready (burst_adapter_source0_ready) // .ready
|
3308 |
|
|
);
|
3309 |
|
|
|
3310 |
|
|
altera_reset_controller #(
|
3311 |
|
|
.NUM_RESET_INPUTS (1),
|
3312 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
3313 |
|
|
.SYNC_DEPTH (2)
|
3314 |
|
|
) rst_controller (
|
3315 |
|
|
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
3316 |
|
|
.clk (clk_clk), // clk.clk
|
3317 |
|
|
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
3318 |
|
|
.reset_in1 (1'b0), // (terminated)
|
3319 |
|
|
.reset_in2 (1'b0), // (terminated)
|
3320 |
|
|
.reset_in3 (1'b0), // (terminated)
|
3321 |
|
|
.reset_in4 (1'b0), // (terminated)
|
3322 |
|
|
.reset_in5 (1'b0), // (terminated)
|
3323 |
|
|
.reset_in6 (1'b0), // (terminated)
|
3324 |
|
|
.reset_in7 (1'b0), // (terminated)
|
3325 |
|
|
.reset_in8 (1'b0), // (terminated)
|
3326 |
|
|
.reset_in9 (1'b0), // (terminated)
|
3327 |
|
|
.reset_in10 (1'b0), // (terminated)
|
3328 |
|
|
.reset_in11 (1'b0), // (terminated)
|
3329 |
|
|
.reset_in12 (1'b0), // (terminated)
|
3330 |
|
|
.reset_in13 (1'b0), // (terminated)
|
3331 |
|
|
.reset_in14 (1'b0), // (terminated)
|
3332 |
|
|
.reset_in15 (1'b0) // (terminated)
|
3333 |
|
|
);
|
3334 |
|
|
|
3335 |
|
|
nios2_sram_cmd_xbar_demux cmd_xbar_demux (
|
3336 |
|
|
.clk (clk_clk), // clk.clk
|
3337 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3338 |
|
|
.sink_ready (limiter_cmd_src_ready), // sink.ready
|
3339 |
|
|
.sink_channel (limiter_cmd_src_channel), // .channel
|
3340 |
|
|
.sink_data (limiter_cmd_src_data), // .data
|
3341 |
|
|
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
|
3342 |
|
|
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
|
3343 |
|
|
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
|
3344 |
|
|
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
|
3345 |
|
|
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
|
3346 |
|
|
.src0_data (cmd_xbar_demux_src0_data), // .data
|
3347 |
|
|
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
|
3348 |
|
|
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
|
3349 |
|
|
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
|
3350 |
|
|
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
|
3351 |
|
|
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
|
3352 |
|
|
.src1_data (cmd_xbar_demux_src1_data), // .data
|
3353 |
|
|
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
|
3354 |
|
|
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
|
3355 |
|
|
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
|
3356 |
|
|
);
|
3357 |
|
|
|
3358 |
|
|
nios2_sram_cmd_xbar_demux_001 cmd_xbar_demux_001 (
|
3359 |
|
|
.clk (clk_clk), // clk.clk
|
3360 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3361 |
|
|
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
|
3362 |
|
|
.sink_channel (limiter_001_cmd_src_channel), // .channel
|
3363 |
|
|
.sink_data (limiter_001_cmd_src_data), // .data
|
3364 |
|
|
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
|
3365 |
|
|
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
|
3366 |
|
|
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
|
3367 |
|
|
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
|
3368 |
|
|
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
|
3369 |
|
|
.src0_data (cmd_xbar_demux_001_src0_data), // .data
|
3370 |
|
|
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
|
3371 |
|
|
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
|
3372 |
|
|
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
|
3373 |
|
|
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
|
3374 |
|
|
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
|
3375 |
|
|
.src1_data (cmd_xbar_demux_001_src1_data), // .data
|
3376 |
|
|
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
|
3377 |
|
|
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
|
3378 |
|
|
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
|
3379 |
|
|
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
|
3380 |
|
|
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
|
3381 |
|
|
.src2_data (cmd_xbar_demux_001_src2_data), // .data
|
3382 |
|
|
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
|
3383 |
|
|
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
|
3384 |
|
|
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
|
3385 |
|
|
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
|
3386 |
|
|
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
|
3387 |
|
|
.src3_data (cmd_xbar_demux_001_src3_data), // .data
|
3388 |
|
|
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
|
3389 |
|
|
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
|
3390 |
|
|
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
|
3391 |
|
|
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
|
3392 |
|
|
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
|
3393 |
|
|
.src4_data (cmd_xbar_demux_001_src4_data), // .data
|
3394 |
|
|
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
|
3395 |
|
|
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
|
3396 |
|
|
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
|
3397 |
|
|
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
|
3398 |
|
|
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
|
3399 |
|
|
.src5_data (cmd_xbar_demux_001_src5_data), // .data
|
3400 |
|
|
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
|
3401 |
|
|
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
|
3402 |
|
|
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
|
3403 |
|
|
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
|
3404 |
|
|
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
|
3405 |
|
|
.src6_data (cmd_xbar_demux_001_src6_data), // .data
|
3406 |
|
|
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
|
3407 |
|
|
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
|
3408 |
|
|
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
|
3409 |
|
|
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
|
3410 |
|
|
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
|
3411 |
|
|
.src7_data (cmd_xbar_demux_001_src7_data), // .data
|
3412 |
|
|
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
|
3413 |
|
|
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
|
3414 |
|
|
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
|
3415 |
|
|
);
|
3416 |
|
|
|
3417 |
|
|
nios2_sram_cmd_xbar_mux cmd_xbar_mux (
|
3418 |
|
|
.clk (clk_clk), // clk.clk
|
3419 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3420 |
|
|
.src_ready (cmd_xbar_mux_src_ready), // src.ready
|
3421 |
|
|
.src_valid (cmd_xbar_mux_src_valid), // .valid
|
3422 |
|
|
.src_data (cmd_xbar_mux_src_data), // .data
|
3423 |
|
|
.src_channel (cmd_xbar_mux_src_channel), // .channel
|
3424 |
|
|
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
|
3425 |
|
|
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
|
3426 |
|
|
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
|
3427 |
|
|
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
|
3428 |
|
|
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
|
3429 |
|
|
.sink0_data (cmd_xbar_demux_src0_data), // .data
|
3430 |
|
|
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
|
3431 |
|
|
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
|
3432 |
|
|
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
|
3433 |
|
|
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
|
3434 |
|
|
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
|
3435 |
|
|
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
|
3436 |
|
|
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
|
3437 |
|
|
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
|
3438 |
|
|
);
|
3439 |
|
|
|
3440 |
|
|
nios2_sram_cmd_xbar_mux cmd_xbar_mux_001 (
|
3441 |
|
|
.clk (clk_clk), // clk.clk
|
3442 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3443 |
|
|
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
|
3444 |
|
|
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
|
3445 |
|
|
.src_data (cmd_xbar_mux_001_src_data), // .data
|
3446 |
|
|
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
|
3447 |
|
|
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
|
3448 |
|
|
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
|
3449 |
|
|
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
|
3450 |
|
|
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
|
3451 |
|
|
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
|
3452 |
|
|
.sink0_data (cmd_xbar_demux_src1_data), // .data
|
3453 |
|
|
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
|
3454 |
|
|
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
|
3455 |
|
|
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
|
3456 |
|
|
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
|
3457 |
|
|
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
|
3458 |
|
|
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
|
3459 |
|
|
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
|
3460 |
|
|
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
|
3461 |
|
|
);
|
3462 |
|
|
|
3463 |
|
|
nios2_sram_rsp_xbar_demux rsp_xbar_demux (
|
3464 |
|
|
.clk (clk_clk), // clk.clk
|
3465 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3466 |
|
|
.sink_ready (id_router_src_ready), // sink.ready
|
3467 |
|
|
.sink_channel (id_router_src_channel), // .channel
|
3468 |
|
|
.sink_data (id_router_src_data), // .data
|
3469 |
|
|
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
|
3470 |
|
|
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
|
3471 |
|
|
.sink_valid (id_router_src_valid), // .valid
|
3472 |
|
|
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
|
3473 |
|
|
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
|
3474 |
|
|
.src0_data (rsp_xbar_demux_src0_data), // .data
|
3475 |
|
|
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
|
3476 |
|
|
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
|
3477 |
|
|
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
|
3478 |
|
|
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
|
3479 |
|
|
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
|
3480 |
|
|
.src1_data (rsp_xbar_demux_src1_data), // .data
|
3481 |
|
|
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
|
3482 |
|
|
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
|
3483 |
|
|
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
|
3484 |
|
|
);
|
3485 |
|
|
|
3486 |
|
|
nios2_sram_rsp_xbar_demux rsp_xbar_demux_001 (
|
3487 |
|
|
.clk (clk_clk), // clk.clk
|
3488 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3489 |
|
|
.sink_ready (width_adapter_001_src_ready), // sink.ready
|
3490 |
|
|
.sink_channel (width_adapter_001_src_channel), // .channel
|
3491 |
|
|
.sink_data (width_adapter_001_src_data), // .data
|
3492 |
|
|
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
|
3493 |
|
|
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
|
3494 |
|
|
.sink_valid (width_adapter_001_src_valid), // .valid
|
3495 |
|
|
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
|
3496 |
|
|
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
|
3497 |
|
|
.src0_data (rsp_xbar_demux_001_src0_data), // .data
|
3498 |
|
|
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
|
3499 |
|
|
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
|
3500 |
|
|
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
|
3501 |
|
|
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
|
3502 |
|
|
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
|
3503 |
|
|
.src1_data (rsp_xbar_demux_001_src1_data), // .data
|
3504 |
|
|
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
|
3505 |
|
|
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
|
3506 |
|
|
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
|
3507 |
|
|
);
|
3508 |
|
|
|
3509 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_002 (
|
3510 |
|
|
.clk (clk_clk), // clk.clk
|
3511 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3512 |
|
|
.sink_ready (id_router_002_src_ready), // sink.ready
|
3513 |
|
|
.sink_channel (id_router_002_src_channel), // .channel
|
3514 |
|
|
.sink_data (id_router_002_src_data), // .data
|
3515 |
|
|
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
|
3516 |
|
|
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
|
3517 |
|
|
.sink_valid (id_router_002_src_valid), // .valid
|
3518 |
|
|
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
|
3519 |
|
|
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
|
3520 |
|
|
.src0_data (rsp_xbar_demux_002_src0_data), // .data
|
3521 |
|
|
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
|
3522 |
|
|
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
|
3523 |
|
|
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
|
3524 |
|
|
);
|
3525 |
|
|
|
3526 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_003 (
|
3527 |
|
|
.clk (clk_clk), // clk.clk
|
3528 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3529 |
|
|
.sink_ready (id_router_003_src_ready), // sink.ready
|
3530 |
|
|
.sink_channel (id_router_003_src_channel), // .channel
|
3531 |
|
|
.sink_data (id_router_003_src_data), // .data
|
3532 |
|
|
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
|
3533 |
|
|
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
|
3534 |
|
|
.sink_valid (id_router_003_src_valid), // .valid
|
3535 |
|
|
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
|
3536 |
|
|
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
|
3537 |
|
|
.src0_data (rsp_xbar_demux_003_src0_data), // .data
|
3538 |
|
|
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
|
3539 |
|
|
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
|
3540 |
|
|
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
|
3541 |
|
|
);
|
3542 |
|
|
|
3543 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_004 (
|
3544 |
|
|
.clk (clk_clk), // clk.clk
|
3545 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3546 |
|
|
.sink_ready (id_router_004_src_ready), // sink.ready
|
3547 |
|
|
.sink_channel (id_router_004_src_channel), // .channel
|
3548 |
|
|
.sink_data (id_router_004_src_data), // .data
|
3549 |
|
|
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
|
3550 |
|
|
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
|
3551 |
|
|
.sink_valid (id_router_004_src_valid), // .valid
|
3552 |
|
|
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
|
3553 |
|
|
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
|
3554 |
|
|
.src0_data (rsp_xbar_demux_004_src0_data), // .data
|
3555 |
|
|
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
|
3556 |
|
|
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
|
3557 |
|
|
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
|
3558 |
|
|
);
|
3559 |
|
|
|
3560 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_005 (
|
3561 |
|
|
.clk (clk_clk), // clk.clk
|
3562 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3563 |
|
|
.sink_ready (id_router_005_src_ready), // sink.ready
|
3564 |
|
|
.sink_channel (id_router_005_src_channel), // .channel
|
3565 |
|
|
.sink_data (id_router_005_src_data), // .data
|
3566 |
|
|
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
|
3567 |
|
|
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
|
3568 |
|
|
.sink_valid (id_router_005_src_valid), // .valid
|
3569 |
|
|
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
|
3570 |
|
|
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
|
3571 |
|
|
.src0_data (rsp_xbar_demux_005_src0_data), // .data
|
3572 |
|
|
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
|
3573 |
|
|
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
|
3574 |
|
|
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
|
3575 |
|
|
);
|
3576 |
|
|
|
3577 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_006 (
|
3578 |
|
|
.clk (clk_clk), // clk.clk
|
3579 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3580 |
|
|
.sink_ready (id_router_006_src_ready), // sink.ready
|
3581 |
|
|
.sink_channel (id_router_006_src_channel), // .channel
|
3582 |
|
|
.sink_data (id_router_006_src_data), // .data
|
3583 |
|
|
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
|
3584 |
|
|
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
|
3585 |
|
|
.sink_valid (id_router_006_src_valid), // .valid
|
3586 |
|
|
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
|
3587 |
|
|
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
|
3588 |
|
|
.src0_data (rsp_xbar_demux_006_src0_data), // .data
|
3589 |
|
|
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
|
3590 |
|
|
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
|
3591 |
|
|
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
|
3592 |
|
|
);
|
3593 |
|
|
|
3594 |
|
|
nios2_sram_rsp_xbar_demux_002 rsp_xbar_demux_007 (
|
3595 |
|
|
.clk (clk_clk), // clk.clk
|
3596 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3597 |
|
|
.sink_ready (id_router_007_src_ready), // sink.ready
|
3598 |
|
|
.sink_channel (id_router_007_src_channel), // .channel
|
3599 |
|
|
.sink_data (id_router_007_src_data), // .data
|
3600 |
|
|
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
|
3601 |
|
|
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
|
3602 |
|
|
.sink_valid (id_router_007_src_valid), // .valid
|
3603 |
|
|
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
|
3604 |
|
|
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
|
3605 |
|
|
.src0_data (rsp_xbar_demux_007_src0_data), // .data
|
3606 |
|
|
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
|
3607 |
|
|
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
|
3608 |
|
|
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
|
3609 |
|
|
);
|
3610 |
|
|
|
3611 |
|
|
nios2_sram_rsp_xbar_mux rsp_xbar_mux (
|
3612 |
|
|
.clk (clk_clk), // clk.clk
|
3613 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3614 |
|
|
.src_ready (rsp_xbar_mux_src_ready), // src.ready
|
3615 |
|
|
.src_valid (rsp_xbar_mux_src_valid), // .valid
|
3616 |
|
|
.src_data (rsp_xbar_mux_src_data), // .data
|
3617 |
|
|
.src_channel (rsp_xbar_mux_src_channel), // .channel
|
3618 |
|
|
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
|
3619 |
|
|
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
|
3620 |
|
|
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
|
3621 |
|
|
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
|
3622 |
|
|
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
|
3623 |
|
|
.sink0_data (rsp_xbar_demux_src0_data), // .data
|
3624 |
|
|
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
|
3625 |
|
|
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
|
3626 |
|
|
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
|
3627 |
|
|
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
|
3628 |
|
|
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
|
3629 |
|
|
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
|
3630 |
|
|
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
|
3631 |
|
|
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
|
3632 |
|
|
);
|
3633 |
|
|
|
3634 |
|
|
nios2_sram_rsp_xbar_mux_001 rsp_xbar_mux_001 (
|
3635 |
|
|
.clk (clk_clk), // clk.clk
|
3636 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3637 |
|
|
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
|
3638 |
|
|
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
|
3639 |
|
|
.src_data (rsp_xbar_mux_001_src_data), // .data
|
3640 |
|
|
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
|
3641 |
|
|
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
|
3642 |
|
|
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
|
3643 |
|
|
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
|
3644 |
|
|
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
|
3645 |
|
|
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
|
3646 |
|
|
.sink0_data (rsp_xbar_demux_src1_data), // .data
|
3647 |
|
|
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
|
3648 |
|
|
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
|
3649 |
|
|
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
|
3650 |
|
|
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
|
3651 |
|
|
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
|
3652 |
|
|
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
|
3653 |
|
|
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
|
3654 |
|
|
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
|
3655 |
|
|
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
|
3656 |
|
|
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
|
3657 |
|
|
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
|
3658 |
|
|
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
|
3659 |
|
|
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
|
3660 |
|
|
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
|
3661 |
|
|
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
|
3662 |
|
|
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
|
3663 |
|
|
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
|
3664 |
|
|
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
|
3665 |
|
|
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
|
3666 |
|
|
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
|
3667 |
|
|
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
|
3668 |
|
|
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
|
3669 |
|
|
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
|
3670 |
|
|
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
|
3671 |
|
|
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
|
3672 |
|
|
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
|
3673 |
|
|
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
|
3674 |
|
|
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
|
3675 |
|
|
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
|
3676 |
|
|
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
|
3677 |
|
|
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
|
3678 |
|
|
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
|
3679 |
|
|
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
|
3680 |
|
|
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
|
3681 |
|
|
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
|
3682 |
|
|
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
|
3683 |
|
|
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
|
3684 |
|
|
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
|
3685 |
|
|
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
|
3686 |
|
|
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
|
3687 |
|
|
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
|
3688 |
|
|
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
|
3689 |
|
|
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
|
3690 |
|
|
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
|
3691 |
|
|
);
|
3692 |
|
|
|
3693 |
|
|
nios2_sram_cmd_xbar_demux_002 cmd_xbar_demux_002 (
|
3694 |
|
|
.clk (clk_clk), // clk.clk
|
3695 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3696 |
|
|
.sink_ready (addr_router_002_src_ready), // sink.ready
|
3697 |
|
|
.sink_channel (addr_router_002_src_channel), // .channel
|
3698 |
|
|
.sink_data (addr_router_002_src_data), // .data
|
3699 |
|
|
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
|
3700 |
|
|
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
|
3701 |
|
|
.sink_valid (addr_router_002_src_valid), // .valid
|
3702 |
|
|
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
|
3703 |
|
|
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
|
3704 |
|
|
.src0_data (cmd_xbar_demux_002_src0_data), // .data
|
3705 |
|
|
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
|
3706 |
|
|
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
|
3707 |
|
|
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
|
3708 |
|
|
);
|
3709 |
|
|
|
3710 |
|
|
nios2_sram_cmd_xbar_demux_002 cmd_xbar_demux_003 (
|
3711 |
|
|
.clk (clk_clk), // clk.clk
|
3712 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3713 |
|
|
.sink_ready (addr_router_003_src_ready), // sink.ready
|
3714 |
|
|
.sink_channel (addr_router_003_src_channel), // .channel
|
3715 |
|
|
.sink_data (addr_router_003_src_data), // .data
|
3716 |
|
|
.sink_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
|
3717 |
|
|
.sink_endofpacket (addr_router_003_src_endofpacket), // .endofpacket
|
3718 |
|
|
.sink_valid (addr_router_003_src_valid), // .valid
|
3719 |
|
|
.src0_ready (cmd_xbar_demux_003_src0_ready), // src0.ready
|
3720 |
|
|
.src0_valid (cmd_xbar_demux_003_src0_valid), // .valid
|
3721 |
|
|
.src0_data (cmd_xbar_demux_003_src0_data), // .data
|
3722 |
|
|
.src0_channel (cmd_xbar_demux_003_src0_channel), // .channel
|
3723 |
|
|
.src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
|
3724 |
|
|
.src0_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
|
3725 |
|
|
);
|
3726 |
|
|
|
3727 |
|
|
nios2_sram_cmd_xbar_mux_008 cmd_xbar_mux_008 (
|
3728 |
|
|
.clk (clk_clk), // clk.clk
|
3729 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3730 |
|
|
.src_ready (cmd_xbar_mux_008_src_ready), // src.ready
|
3731 |
|
|
.src_valid (cmd_xbar_mux_008_src_valid), // .valid
|
3732 |
|
|
.src_data (cmd_xbar_mux_008_src_data), // .data
|
3733 |
|
|
.src_channel (cmd_xbar_mux_008_src_channel), // .channel
|
3734 |
|
|
.src_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket
|
3735 |
|
|
.src_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket
|
3736 |
|
|
.sink0_ready (cmd_xbar_demux_002_src0_ready), // sink0.ready
|
3737 |
|
|
.sink0_valid (cmd_xbar_demux_002_src0_valid), // .valid
|
3738 |
|
|
.sink0_channel (cmd_xbar_demux_002_src0_channel), // .channel
|
3739 |
|
|
.sink0_data (cmd_xbar_demux_002_src0_data), // .data
|
3740 |
|
|
.sink0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
|
3741 |
|
|
.sink0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
|
3742 |
|
|
.sink1_ready (cmd_xbar_demux_003_src0_ready), // sink1.ready
|
3743 |
|
|
.sink1_valid (cmd_xbar_demux_003_src0_valid), // .valid
|
3744 |
|
|
.sink1_channel (cmd_xbar_demux_003_src0_channel), // .channel
|
3745 |
|
|
.sink1_data (cmd_xbar_demux_003_src0_data), // .data
|
3746 |
|
|
.sink1_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
|
3747 |
|
|
.sink1_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
|
3748 |
|
|
);
|
3749 |
|
|
|
3750 |
|
|
nios2_sram_rsp_xbar_demux_008 rsp_xbar_demux_008 (
|
3751 |
|
|
.clk (clk_clk), // clk.clk
|
3752 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3753 |
|
|
.sink_ready (id_router_008_src_ready), // sink.ready
|
3754 |
|
|
.sink_channel (id_router_008_src_channel), // .channel
|
3755 |
|
|
.sink_data (id_router_008_src_data), // .data
|
3756 |
|
|
.sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
|
3757 |
|
|
.sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
|
3758 |
|
|
.sink_valid (id_router_008_src_valid), // .valid
|
3759 |
|
|
.src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
|
3760 |
|
|
.src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
|
3761 |
|
|
.src0_data (rsp_xbar_demux_008_src0_data), // .data
|
3762 |
|
|
.src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
|
3763 |
|
|
.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
|
3764 |
|
|
.src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
|
3765 |
|
|
.src1_ready (rsp_xbar_demux_008_src1_ready), // src1.ready
|
3766 |
|
|
.src1_valid (rsp_xbar_demux_008_src1_valid), // .valid
|
3767 |
|
|
.src1_data (rsp_xbar_demux_008_src1_data), // .data
|
3768 |
|
|
.src1_channel (rsp_xbar_demux_008_src1_channel), // .channel
|
3769 |
|
|
.src1_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket
|
3770 |
|
|
.src1_endofpacket (rsp_xbar_demux_008_src1_endofpacket) // .endofpacket
|
3771 |
|
|
);
|
3772 |
|
|
|
3773 |
|
|
altera_merlin_width_adapter #(
|
3774 |
|
|
.IN_PKT_ADDR_H (56),
|
3775 |
|
|
.IN_PKT_ADDR_L (36),
|
3776 |
|
|
.IN_PKT_DATA_H (31),
|
3777 |
|
|
.IN_PKT_DATA_L (0),
|
3778 |
|
|
.IN_PKT_BYTEEN_H (35),
|
3779 |
|
|
.IN_PKT_BYTEEN_L (32),
|
3780 |
|
|
.IN_PKT_BYTE_CNT_H (65),
|
3781 |
|
|
.IN_PKT_BYTE_CNT_L (63),
|
3782 |
|
|
.IN_PKT_TRANS_COMPRESSED_READ (57),
|
3783 |
|
|
.IN_PKT_BURSTWRAP_H (68),
|
3784 |
|
|
.IN_PKT_BURSTWRAP_L (66),
|
3785 |
|
|
.IN_PKT_BURST_SIZE_H (71),
|
3786 |
|
|
.IN_PKT_BURST_SIZE_L (69),
|
3787 |
|
|
.IN_PKT_RESPONSE_STATUS_H (93),
|
3788 |
|
|
.IN_PKT_RESPONSE_STATUS_L (92),
|
3789 |
|
|
.IN_PKT_TRANS_EXCLUSIVE (62),
|
3790 |
|
|
.IN_PKT_BURST_TYPE_H (73),
|
3791 |
|
|
.IN_PKT_BURST_TYPE_L (72),
|
3792 |
|
|
.IN_ST_DATA_W (94),
|
3793 |
|
|
.OUT_PKT_ADDR_H (38),
|
3794 |
|
|
.OUT_PKT_ADDR_L (18),
|
3795 |
|
|
.OUT_PKT_DATA_H (15),
|
3796 |
|
|
.OUT_PKT_DATA_L (0),
|
3797 |
|
|
.OUT_PKT_BYTEEN_H (17),
|
3798 |
|
|
.OUT_PKT_BYTEEN_L (16),
|
3799 |
|
|
.OUT_PKT_BYTE_CNT_H (47),
|
3800 |
|
|
.OUT_PKT_BYTE_CNT_L (45),
|
3801 |
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (39),
|
3802 |
|
|
.OUT_PKT_BURST_SIZE_H (53),
|
3803 |
|
|
.OUT_PKT_BURST_SIZE_L (51),
|
3804 |
|
|
.OUT_PKT_RESPONSE_STATUS_H (75),
|
3805 |
|
|
.OUT_PKT_RESPONSE_STATUS_L (74),
|
3806 |
|
|
.OUT_PKT_TRANS_EXCLUSIVE (44),
|
3807 |
|
|
.OUT_PKT_BURST_TYPE_H (55),
|
3808 |
|
|
.OUT_PKT_BURST_TYPE_L (54),
|
3809 |
|
|
.OUT_ST_DATA_W (76),
|
3810 |
|
|
.ST_CHANNEL_W (8),
|
3811 |
|
|
.OPTIMIZE_FOR_RSP (0)
|
3812 |
|
|
) width_adapter (
|
3813 |
|
|
.clk (clk_clk), // clk.clk
|
3814 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3815 |
|
|
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
|
3816 |
|
|
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
|
3817 |
|
|
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
|
3818 |
|
|
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
|
3819 |
|
|
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
|
3820 |
|
|
.in_data (cmd_xbar_mux_001_src_data), // .data
|
3821 |
|
|
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
|
3822 |
|
|
.out_data (width_adapter_src_data), // .data
|
3823 |
|
|
.out_channel (width_adapter_src_channel), // .channel
|
3824 |
|
|
.out_valid (width_adapter_src_valid), // .valid
|
3825 |
|
|
.out_ready (width_adapter_src_ready), // .ready
|
3826 |
|
|
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
|
3827 |
|
|
.in_command_size_data (3'b000) // (terminated)
|
3828 |
|
|
);
|
3829 |
|
|
|
3830 |
|
|
altera_merlin_width_adapter #(
|
3831 |
|
|
.IN_PKT_ADDR_H (38),
|
3832 |
|
|
.IN_PKT_ADDR_L (18),
|
3833 |
|
|
.IN_PKT_DATA_H (15),
|
3834 |
|
|
.IN_PKT_DATA_L (0),
|
3835 |
|
|
.IN_PKT_BYTEEN_H (17),
|
3836 |
|
|
.IN_PKT_BYTEEN_L (16),
|
3837 |
|
|
.IN_PKT_BYTE_CNT_H (47),
|
3838 |
|
|
.IN_PKT_BYTE_CNT_L (45),
|
3839 |
|
|
.IN_PKT_TRANS_COMPRESSED_READ (39),
|
3840 |
|
|
.IN_PKT_BURSTWRAP_H (50),
|
3841 |
|
|
.IN_PKT_BURSTWRAP_L (48),
|
3842 |
|
|
.IN_PKT_BURST_SIZE_H (53),
|
3843 |
|
|
.IN_PKT_BURST_SIZE_L (51),
|
3844 |
|
|
.IN_PKT_RESPONSE_STATUS_H (75),
|
3845 |
|
|
.IN_PKT_RESPONSE_STATUS_L (74),
|
3846 |
|
|
.IN_PKT_TRANS_EXCLUSIVE (44),
|
3847 |
|
|
.IN_PKT_BURST_TYPE_H (55),
|
3848 |
|
|
.IN_PKT_BURST_TYPE_L (54),
|
3849 |
|
|
.IN_ST_DATA_W (76),
|
3850 |
|
|
.OUT_PKT_ADDR_H (56),
|
3851 |
|
|
.OUT_PKT_ADDR_L (36),
|
3852 |
|
|
.OUT_PKT_DATA_H (31),
|
3853 |
|
|
.OUT_PKT_DATA_L (0),
|
3854 |
|
|
.OUT_PKT_BYTEEN_H (35),
|
3855 |
|
|
.OUT_PKT_BYTEEN_L (32),
|
3856 |
|
|
.OUT_PKT_BYTE_CNT_H (65),
|
3857 |
|
|
.OUT_PKT_BYTE_CNT_L (63),
|
3858 |
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (57),
|
3859 |
|
|
.OUT_PKT_BURST_SIZE_H (71),
|
3860 |
|
|
.OUT_PKT_BURST_SIZE_L (69),
|
3861 |
|
|
.OUT_PKT_RESPONSE_STATUS_H (93),
|
3862 |
|
|
.OUT_PKT_RESPONSE_STATUS_L (92),
|
3863 |
|
|
.OUT_PKT_TRANS_EXCLUSIVE (62),
|
3864 |
|
|
.OUT_PKT_BURST_TYPE_H (73),
|
3865 |
|
|
.OUT_PKT_BURST_TYPE_L (72),
|
3866 |
|
|
.OUT_ST_DATA_W (94),
|
3867 |
|
|
.ST_CHANNEL_W (8),
|
3868 |
|
|
.OPTIMIZE_FOR_RSP (1)
|
3869 |
|
|
) width_adapter_001 (
|
3870 |
|
|
.clk (clk_clk), // clk.clk
|
3871 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3872 |
|
|
.in_valid (id_router_001_src_valid), // sink.valid
|
3873 |
|
|
.in_channel (id_router_001_src_channel), // .channel
|
3874 |
|
|
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
|
3875 |
|
|
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
|
3876 |
|
|
.in_ready (id_router_001_src_ready), // .ready
|
3877 |
|
|
.in_data (id_router_001_src_data), // .data
|
3878 |
|
|
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
|
3879 |
|
|
.out_data (width_adapter_001_src_data), // .data
|
3880 |
|
|
.out_channel (width_adapter_001_src_channel), // .channel
|
3881 |
|
|
.out_valid (width_adapter_001_src_valid), // .valid
|
3882 |
|
|
.out_ready (width_adapter_001_src_ready), // .ready
|
3883 |
|
|
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
|
3884 |
|
|
.in_command_size_data (3'b000) // (terminated)
|
3885 |
|
|
);
|
3886 |
|
|
|
3887 |
|
|
nios2_sram_irq_mapper irq_mapper (
|
3888 |
|
|
.clk (clk_clk), // clk.clk
|
3889 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
3890 |
|
|
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
|
3891 |
|
|
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
|
3892 |
|
|
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
|
3893 |
|
|
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
|
3894 |
|
|
.sender_irq (nios2_qsys_0_d_irq_irq) // sender.irq
|
3895 |
|
|
);
|
3896 |
|
|
|
3897 |
|
|
endmodule
|