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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dct_to_hibi/] [1.0/] [dct_to_hibi.1.0.xml] - Blame information for rev 166

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        TUT
        ip.hwp.accelerator
        dct_to_hibi
        1.0
        DCT to Hibi. Connects dctQidct block to HIBI Wrapper
 
 
Input:
1. Two address to send the results to (one for quant, one for idct)
2. Control word for the current macroblock
    Control word structure: bit 6: chroma(1)/luma(0), 5: intra(1)/inter(0),
                             4..0: quantizer parameter (QP)
3. Then the DCT data ( 8x8x6 x 16-bit values = 384 x 16 bit )
 
Chroma/luma: 4 luma, 2 chroma
 
Outputs:
 Outputs are 16-bit words which are packed up to hibi. If hibi width is
 32b, then 2 16-bit words are combined into one hibi word.
 01. quant results: 1. 8*8 x 16bit values to quant result address
 02. idct  results: 1. 8*8 x 16bit values to idct  result address
 03. quant results: 2. 8*8 x 16bit values to quant result address
 04. idct  results: 2. 8*8 x 16bit values to idct  result address
 05. quant results: 3. 8*8 x 16bit values to quant result address
 06. idct  results: 3. 8*8 x 16bit values to idct  result address
 07. quant results: 4. 8*8 x 16bit values to quant result address
 08. idct  results: 4. 8*8 x 16bit values to idct  result address
 09. quant results: 5. 8*8 x 16bit values to quant result address
 10. idct  results: 5. 8*8 x 16bit values to idct  result address
 11. quant results: 6. 8*8 x 16bit values to quant result address
 12. quant results: 1 word with bits 5..0 determing if 8x8 quant blocks(1-6)
                    has all values zeros (except dc-component in intra)
 13. idct  results: 6. 8*8 x 16bit values to idct  result address
-
 Total amount of 16-bit values is: 384 per result address + 1 hibi word to
 quantization result address.
 
 With default parameter:
 Total of 193 words of data to quant address (if data_width_g = 32)
 Total of 192 words of data to idct address (if data_width_g = 32)

        
                
                        clk
                        Clock interface
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        dct_if
                        Interface for connecting idctquant accelerator  
                        
                        
                        
                        false
                        
                                
                                        
                                                CHROMA_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                chroma_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                DCT_READY4COL_FROM_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                dct_ready4col_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                IDCT_READY4COL_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                idct_ready4col_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                INTRA_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                intra_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOAD_QP_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                loadQP_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                QP_TO_ACC
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                QP_out
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                WR_DCT_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                wr_dct_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                WR_IDCT_FROM_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                wr_idct_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                WR_QUANT_FROM_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                wr_quant_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                QUANT_READY4COL_TO_ACC
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                quant_ready4col_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA_DCT_TO_ACC
                                                
                                                        8
                                                        0
                                                
                                        
                                        
                                                data_dct_out
                                                
                                                        8
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA_IDCT_FROM_ACC
                                                
                                                        8
                                                        0
                                                
                                        
                                        
                                                data_idct_in
                                                
                                                        8
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA_QUANT_FROM_ACC
                                                
                                                        7
                                                        0
                                                
                                        
                                        
                                                data_quant_in
                                                
                                                        7
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_master
                        HIBI wrapper r4 version 2 master interface
                        
                        
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_av_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                hibi_comm_out
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                hibi_data_out
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                RE
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_re_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                WE
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_we_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        Active low reset input.
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_slave
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_av_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                hibi_comm_in
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                hibi_data_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                EMPTY
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_empty_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_full_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        dct_mem_map
                        
                                dct_regs
                                0x0
                                1
                                32
                                register
                                
                                        quant_result_addr
                                        0
                                        0x0
                                        32
                                
                                
                                        idct_result_addr
                                        0
                                        0x1
                                        32
                                
                                
                                        ctrl_reg
                                        0
                                        0x2
                                        32
                                        
                                                QP
                                                Quant parameter
                                                0
                                                5
                                                false
                                                true
                                        
                                        
                                                intra_or_inter
                                                0=intra, 1=inter
                                                5
                                                1
                                                false
                                                true
                                        
                                        
                                                chroma_luma
                                                0=luma, 1=chroma
                                                6
                                                1
                                                false
                                                true
                                        
                                
                                
                                        dct_data
                                        0
                                        0x3
                                        32
                                
                        
                        8
                
        
        
                
                        
                                rtl
                                vhdl:quartus, modelsim:
                                dct_to_hibi
                                
                                        hdlSources
                                
                        
                
                
                        
                                QP_out
                                
                                        out
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                chroma_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                clk
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                data_dct_out
                                
                                        out
                                        
                                                8
                                                0
                                        
                                
                                
                        
                        
                                data_idct_in
                                
                                        in
                                        
                                                8
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                data_quant_in
                                
                                        in
                                        
                                                7
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                dct_ready4col_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                debug_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                hibi_av_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                hibi_av_out
                                
                                        out
                                
                                
                        
                        
                                hibi_comm_in
                                
                                        in
                                        
                                                4
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                hibi_comm_out
                                
                                        out
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                hibi_data_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                hibi_data_out
                                
                                        out
                                        
                                                31
                                                0
                                        
                                
                                
                        
                        
                                hibi_empty_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                hibi_full_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                hibi_re_out
                                
                                        out
                                
                                
                        
                        
                                hibi_we_out
                                
                                        out
                                
                                
                        
                        
                                idct_ready4col_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                intra_out
                                
                                        out
                                
                                
                        
                        
                                loadQP_out
                                
                                        out
                                
                                
                        
                        
                                quant_ready4col_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                rst_n
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                wr_dct_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                wr_idct_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                wr_quant_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                
                
                        
                                comm_width_g
                                5
                        
                        
                                data_width_g
                                32
                        
                        
                                dct_width_g
                                Incoming data width(9b)
                                9
                        
                        
                                debug_w_g
                                1
                        
                        
                                idct_width_g
                                Data width after IDCT(9b)
                                9
                        
                        
                                own_address_g
                                Used for self-release
                                0
                        
                        
                                quant_width_g
                                Quantizated data width(8b)
                                8
                        
                        
                                rtm_address_g
                                Used for self-release
                                0
                        
                        
                                use_self_rel_g
                                Does it release itself from RTM?
                                1
                        
                
        
        
                
                        hdlSources
                        
                                hdl/cl_cnt.vhd
                                vhdlSource
                                false
                                dct_to_hibi
                        
                        
                                hdl/dct_to_hibi_v2.vhd
                                vhdlSource
                                false
                                dct_to_hibi
                        
                        
                                ../../dctqidct/1.0/hdl/dctQidct/IDCT_fifo.vhd
                                vhdlSource
                                false
                                dct_to_hibi
                        
                
                
                        Documentation
                        
                                doc/dct_to_hibi_ports.csv
                                csvFile
                                false
                        
                
        
        
                
                        
                                IP
                                HW
                                Mutable
                        
                        
                                
                                        dct_data_in
                                        
                                        
                                        
                                        packet
                                        in
                                        
                                
                                
                                        dct_data_out
                                        
                                        
                                        
                                        packet
                                        out
                                        
                                
                                
                                        block_count_in
                                        
                                        
                                        
                                        message
                                        in
                                        
                                
                        
                
        


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Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dct_to_hibi/] [1.0/] [dct_to_hibi.1.0.xml] - Blame information for rev 166

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4
5
6
7			`TUT`
8			`ip.hwp.accelerator`
9			`dct_to_hibi`
10			`1.0`
11			`DCT to Hibi. Connects dctQidct block to HIBI Wrapper`
12
13
14			`Input:`
15			`1. Two address to send the results to (one for quant, one for idct)`
16			`2. Control word for the current macroblock`
17			`Control word structure: bit 6: chroma(1)/luma(0), 5: intra(1)/inter(0),`
18			`4..0: quantizer parameter (QP)`
19			`3. Then the DCT data ( 8x8x6 x 16-bit values = 384 x 16 bit )`
20
21			`Chroma/luma: 4 luma, 2 chroma`
22
23			`Outputs:`
24			`Outputs are 16-bit words which are packed up to hibi. If hibi width is`
25			`32b, then 2 16-bit words are combined into one hibi word.`
26			`01. quant results: 1. 8*8 x 16bit values to quant result address`
27			`02. idct results: 1. 8*8 x 16bit values to idct result address`
28			`03. quant results: 2. 8*8 x 16bit values to quant result address`
29			`04. idct results: 2. 8*8 x 16bit values to idct result address`
30			`05. quant results: 3. 8*8 x 16bit values to quant result address`
31			`06. idct results: 3. 8*8 x 16bit values to idct result address`
32			`07. quant results: 4. 8*8 x 16bit values to quant result address`
33			`08. idct results: 4. 8*8 x 16bit values to idct result address`
34			`09. quant results: 5. 8*8 x 16bit values to quant result address`
35			`10. idct results: 5. 8*8 x 16bit values to idct result address`
36			`11. quant results: 6. 8*8 x 16bit values to quant result address`
37			`12. quant results: 1 word with bits 5..0 determing if 8x8 quant blocks(1-6)`
38			`has all values zeros (except dc-component in intra)`
39			`13. idct results: 6. 8*8 x 16bit values to idct result address`
40			`-`
41			`Total amount of 16-bit values is: 384 per result address + 1 hibi word to`
42			`quantization result address.`
43
44			`With default parameter:`
45			`Total of 193 words of data to quant address (if data_width_g = 32)`
46			`Total of 192 words of data to idct address (if data_width_g = 32)`
47
48
49
50			`clk`
51			`Clock interface`
52
53
54
55			`false`
56
57
58
59			`CLK`
60
61			`0`
62			`0`
63
64
65
66			`clk`
67
68			`0`
69			`0`
70
71
72
73
74			`8`
75			`little`
76
77
78			`dct_if`
79			`Interface for connecting idctquant accelerator`
80
81
82
83			`false`
84
85
86
87			`CHROMA_TO_ACC`
88
89			`0`
90			`0`
91
92
93
94			`chroma_out`
95
96			`0`
97			`0`
98
99
100
101
102
103			`DCT_READY4COL_FROM_ACC`
104
105			`0`
106			`0`
107
108
109
110			`dct_ready4col_in`
111
112			`0`
113			`0`
114
115
116
117
118
119			`IDCT_READY4COL_TO_ACC`
120
121			`0`
122			`0`
123
124
125
126			`idct_ready4col_out`
127
128			`0`
129			`0`
130
131
132
133
134
135			`INTRA_TO_ACC`
136
137			`0`
138			`0`
139
140
141
142			`intra_out`
143
144			`0`
145			`0`
146
147
148
149
150
151			`LOAD_QP_TO_ACC`
152
153			`0`
154			`0`
155
156
157
158			`loadQP_out`
159
160			`0`
161			`0`
162
163
164
165
166
167			`QP_TO_ACC`
168
169			`4`
170			`0`
171
172
173
174			`QP_out`
175
176			`4`
177			`0`
178
179
180
181
182
183			`WR_DCT_TO_ACC`
184
185			`0`
186			`0`
187
188
189
190			`wr_dct_out`
191
192			`0`
193			`0`
194
195
196
197
198
199			`WR_IDCT_FROM_ACC`
200
201			`0`
202			`0`
203
204
205
206			`wr_idct_in`
207
208			`0`
209			`0`
210
211
212
213
214
215			`WR_QUANT_FROM_ACC`
216
217			`0`
218			`0`
219
220
221
222			`wr_quant_in`
223
224			`0`
225			`0`
226
227
228
229
230
231			`QUANT_READY4COL_TO_ACC`
232
233			`0`
234			`0`
235
236
237
238			`quant_ready4col_out`
239
240			`0`
241			`0`
242
243
244
245
246
247			`DATA_DCT_TO_ACC`
248
249			`8`
250			`0`
251
252
253
254			`data_dct_out`
255
256			`8`
257			`0`
258
259
260
261
262
263			`DATA_IDCT_FROM_ACC`
264
265			`8`
266			`0`
267
268
269
270			`data_idct_in`
271
272			`8`
273			`0`
274
275
276
277
278
279			`DATA_QUANT_FROM_ACC`
280
281			`7`
282			`0`
283
284
285
286			`data_quant_in`
287
288			`7`
289			`0`
290
291
292
293
294			`8`
295			`little`
296
297
298			`hibi_master`
299			`HIBI wrapper r4 version 2 master interface`
300
301
302
303			`false`
304
305
306
307			`AV`
308
309			`0`
310			`0`
311
312
313
314			`hibi_av_out`
315
316			`0`
317			`0`
318
319
320
321
322
323			`COMM`
324
325			`4`
326			`0`
327
328
329
330			`hibi_comm_out`
331
332			`4`
333			`0`
334
335
336
337
338
339			`DATA`
340
341			`31`
342			`0`
343
344
345
346			`hibi_data_out`
347
348			`31`
349			`0`
350
351
352
353
354
355			`RE`
356
357			`0`
358			`0`
359
360
361
362			`hibi_re_out`
363
364			`0`
365			`0`
366
367
368
369
370
371			`WE`
372
373			`0`
374			`0`
375
376
377
378			`hibi_we_out`
379
380			`0`
381			`0`
382
383
384
385
386			`8`
387			`little`
388
389
390			`rst_n`
391			`Active low reset input.`
392
393
394
395			`false`
396
397
398
399			`RESETn`
400
401			`0`
402			`0`
403
404
405
406			`rst_n`
407
408			`0`
409			`0`
410
411
412
413
414			`8`
415			`little`
416
417
418			`hibi_slave`
419
420
421	157	lanttu
422
423
424	145	lanttu	`false`
425
426
427
428			`AV`
429
430			`0`
431			`0`
432
433
434
435			`hibi_av_in`
436
437			`0`
438			`0`
439
440
441
442
443
444			`COMM`
445
446			`4`
447			`0`
448
449
450
451			`hibi_comm_in`
452
453			`4`
454			`0`
455
456
457
458
459
460			`DATA`
461
462			`31`
463			`0`
464
465
466
467			`hibi_data_in`
468
469			`31`
470			`0`
471
472
473
474
475
476			`EMPTY`
477
478			`0`
479			`0`
480
481
482
483			`hibi_empty_in`
484
485			`0`
486			`0`
487
488
489
490
491
492			`FULL`
493
494			`0`
495			`0`
496
497
498
499			`hibi_full_in`
500
501			`0`
502			`0`
503
504
505
506
507			`8`
508			`little`
509
510
511	157	lanttu
512
513			`dct_mem_map`
514
515			`dct_regs`
516			`0x0`
517			`1`
518			`32`
519			`register`
520
521			`quant_result_addr`
522			`0`
523			`0x0`
524			`32`
525
526
527			`idct_result_addr`
528			`0`
529			`0x1`
530			`32`
531
532
533			`ctrl_reg`
534			`0`
535			`0x2`
536			`32`
537
538			`QP`
539			`Quant parameter`
540			`0`
541			`5`
542			`false`
543			`true`
544
545
546			`intra_or_inter`
547			`0=intra, 1=inter`
548			`5`
549			`1`
550			`false`
551			`true`
552
553
554			`chroma_luma`
555			`0=luma, 1=chroma`
556			`6`
557			`1`
558			`false`
559			`true`
560
561
562
563			`dct_data`
564			`0`
565			`0x3`
566			`32`
567
568
569	166	lanttu	`8`
570	157	lanttu
571
572	145	lanttu
573
574
575			`rtl`
576			`vhdl:quartus, modelsim:`
577			`dct_to_hibi`
578
579			`hdlSources`
580
581
582
583
584
585			`QP_out`
586
587			`out`
588
589			`4`
590			`0`
591
592
593
594
595
596			`chroma_out`
597
598			`out`
599
600			`0`
601			`0`
602
603	159	lanttu
604			`'0'`
605
606	145	lanttu
607
608
609
610			`clk`
611
612			`in`
613	159	lanttu
614			`'0'`
615
616	145	lanttu
617
618
619
620			`data_dct_out`
621
622			`out`
623
624			`8`
625			`0`
626
627
628
629
630
631			`data_idct_in`
632
633			`in`
634
635			`8`
636			`0`
637
638	159	lanttu
639			`(others => '0')`
640
641	145	lanttu
642
643
644
645			`data_quant_in`
646
647			`in`
648
649			`7`
650			`0`
651
652	159	lanttu
653			`(others => '0')`
654
655	145	lanttu
656
657
658
659			`dct_ready4col_in`
660
661			`in`
662	159	lanttu
663			`'0'`
664
665	145	lanttu
666
667
668
669			`debug_out`
670
671			`out`
672
673			`0`
674			`0`
675
676
677
678
679
680			`hibi_av_in`
681
682			`in`
683	159	lanttu
684			`'0'`
685
686	145	lanttu
687
688
689
690			`hibi_av_out`
691
692			`out`
693
694
695
696
697			`hibi_comm_in`
698
699			`in`
700
701			`4`
702			`0`
703
704
705	159	lanttu	`(others => '0')`
706	145	lanttu
707
708
709
710
711			`hibi_comm_out`
712
713			`out`
714
715			`4`
716			`0`
717
718
719
720
721
722			`hibi_data_in`
723
724			`in`
725
726			`31`
727			`0`
728
729
730			`(others => '0')`
731
732
733
734
735
736			`hibi_data_out`
737
738			`out`
739
740			`31`
741			`0`
742
743
744
745
746
747			`hibi_empty_in`
748
749			`in`
750
751			`'0'`
752
753
754
755
756
757			`hibi_full_in`
758
759			`in`
760
761	159	lanttu	`'0'`
762	145	lanttu
763
764
765
766
767			`hibi_re_out`
768
769			`out`
770
771
772
773
774			`hibi_we_out`
775
776			`out`
777
778
779
780
781			`idct_ready4col_out`
782
783			`out`
784
785			`0`
786			`0`
787
788
789
790
791
792			`intra_out`
793
794			`out`
795
796
797
798
799			`loadQP_out`
800
801			`out`
802
803
804
805
806			`quant_ready4col_out`
807
808			`out`
809
810			`0`
811			`0`
812
813
814
815
816
817			`rst_n`
818
819			`in`
820	159	lanttu
821			`'0'`
822
823	145	lanttu
824
825
826
827			`wr_dct_out`
828
829			`out`
830
831			`0`
832			`0`
833
834
835
836
837
838			`wr_idct_in`
839
840			`in`
841
842			`0`
843			`0`
844
845	159	lanttu
846			`'0'`
847
848	145	lanttu
849
850
851
852			`wr_quant_in`
853
854			`in`
855
856			`0`
857			`0`
858
859	159	lanttu
860			`'0'`
861
862	145	lanttu
863
864
865
866
867
868			`comm_width_g`
869			`5`
870
871
872			`data_width_g`
873			`32`
874
875
876			`dct_width_g`
877			`Incoming data width(9b)`
878			`9`
879
880
881			`debug_w_g`
882			`1`
883
884
885			`idct_width_g`
886			`Data width after IDCT(9b)`
887			`9`
888
889
890			`own_address_g`
891			`Used for self-release`
892			`0`
893
894
895			`quant_width_g`
896			`Quantizated data width(8b)`
897			`8`
898
899
900			`rtm_address_g`
901			`Used for self-release`
902			`0`
903
904
905			`use_self_rel_g`
906			`Does it release itself from RTM?`
907			`1`
908
909
910
911
912
913			`hdlSources`
914
915			`hdl/cl_cnt.vhd`
916			`vhdlSource`
917			`false`
918			`dct_to_hibi`
919
920
921			`hdl/dct_to_hibi_v2.vhd`
922			`vhdlSource`
923			`false`
924			`dct_to_hibi`
925
926
927			`../../dctqidct/1.0/hdl/dctQidct/IDCT_fifo.vhd`
928			`vhdlSource`
929			`false`
930			`dct_to_hibi`
931
932
933
934			`Documentation`
935
936			`doc/dct_to_hibi_ports.csv`
937			`csvFile`
938			`false`
939
940
941
942
943
944
945			`IP`
946			`HW`
947			`Mutable`
948
949
950
951			`dct_data_in`
952
953
954
955			`packet`
956			`in`
957
958
959
960			`dct_data_out`
961
962
963
964			`packet`
965			`out`
966
967
968
969			`block_count_in`
970
971
972
973			`message`
974			`in`
975
976
977
978
979
980