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mballance |
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info commands
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info procs
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new_project \
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-location libero/fwrisc_fpga \
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-name fwrisc_fpga \
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-hdl VERILOG \
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-family SmartFusion2 \
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-die "M2S025" \
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-use_enhanced_constraint_flow 1
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# open_project -file libero/fwrisc_fpga
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_alu.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_comparator.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_dbus_if.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_regfile.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_tracer.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc.sv
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_defines.vh
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import_files -hdl_source $env(FWRISC)/rtl/fwrisc_fpga_top.sv
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set_root fwrisc_fpga_top
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file copy $env(FWRISC)/rtl/regs.hex libero/fwrisc_fpga/synthesis/regs.hex
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file copy sw/rom.hex libero/fwrisc_fpga/synthesis/rom.hex
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run_tool -name {CONSTRAINT_MANAGEMENT}
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import_files \
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-io_pdc constraints/fwrisc_fpga_top.pdc
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organize_tool_files -tool {PLACEROUTE} \
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-file ./libero/fwrisc_fpga/constraint/io/fwrisc_fpga_top.pdc \
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-module {fwrisc_fpga_top::work} \
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-input_type constraint
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import_files -sdc constraints/fwrisc_fpga_top.sdc
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organize_tool_files -tool {SYNTHESIZE} \
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-file ./libero/fwrisc_fpga/constraint/fwrisc_fpga_top.sdc \
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-module {fwrisc_fpga_top::work} \
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-input_type constraint
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organize_tool_files -tool {PLACEROUTE} \
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-file ./libero/fwrisc_fpga/constraint/io/fwrisc_fpga_top.pdc \
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-file ./libero/fwrisc_fpga/constraint/fwrisc_fpga_top.sdc \
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-module fwrisc_fpga_top::work \
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-input_type {constraint}
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organize_tool_files -tool {VERIFYTIMING} \
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-file ./libero/fwrisc_fpga/constraint/fwrisc_fpga_top.sdc \
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-module fwrisc_fpga_top::work \
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-input_type {constraint}
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save_project
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# update_and_run_tool -name SYNTHESIZE
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delete_files -file {./synthesis/fwrisc_fpga_top.edn} -from_disk
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delete_files -file {./synthesis/fwrisc_fpga_top_sdc.sdc} -from_disk
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set_device \
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-family {SmartFusion2} -die {M2S025} -package {256 VF} \
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-speed {-1} -die_voltage {1.2} -part_range {COM} \
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-adv_options {IO_DEFT_STD:LVCMOS 2.5V} \
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-adv_options {RESERVEMIGRATIONPINS:1} \
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-adv_options {RESTRICTPROBEPINS:1} \
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-adv_options {RESTRICTSPIPINS:0} \
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-adv_options {TEMPR:COM} \
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-adv_options {UNUSED_MSS_IO_RESISTOR_PULL:None} \
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-adv_options {VCCI_1.2_VOLTR:COM} \
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-adv_options {VCCI_1.5_VOLTR:COM} \
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-adv_options {VCCI_1.8_VOLTR:COM} \
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-adv_options {VCCI_2.5_VOLTR:COM} \
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-adv_options {VCCI_3.3_VOLTR:COM} -adv_options {VOLTR:COM}
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puts "**> SYNTHESIZE (1)"
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run_tool -name {SYNTHESIZE}
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puts "<** SYNTHESIZE (1)"
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generate_sdc_constraint_coverage -tool {PLACEROUTE}
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# generate_sdc_constraint_coverage -tool {PLACEROUTE}
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puts "**> PLACEROUTE (1)"
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run_tool -name {PLACEROUTE}
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puts "<** PLACEROUTE (1)"
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puts "**> GENERATEPROGRAMMINGDATA (1)"
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run_tool -name {GENERATEPROGRAMMINGDATA}
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puts "<** GENERATEPROGRAMMINGDATA (1)"
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puts "**> GENERATEPROGRAMMINGFILE (1)"
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run_tool -name {GENERATEPROGRAMMINGFILE}
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puts "<** GENERATEPROGRAMMINGFILE (1)"
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puts "**> SYNTHESIZE (2)"
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run_tool -name {SYNTHESIZE}
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puts "<**> SYNTHESIZE (2)"
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generate_sdc_constraint_coverage -tool {PLACEROUTE}
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# generate_sdc_constraint_coverage -tool {PLACEROUTE}
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puts "**> PLACEROUTE (2)"
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run_tool -name {PLACEROUTE}
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puts "<** PLACEROUTE (2)"
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puts "**> GENERATEPROGRAMMINGFILE (2)"
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run_tool -name {GENERATEPROGRAMMINGFILE}
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puts "<** GENERATEPROGRAMMINGFILE (2)"
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puts "**> export_bitstream"
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export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
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puts "<** export_bitstream"
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exit 0
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