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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [fwrisc_instr_tests_exception.cpp] - Blame information for rev 2

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1 2 mballance
/*
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 * fwrisc_instr_tests_exception.cpp
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 *
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 *  Created on: Nov 11, 2018
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 *      Author: ballance
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 */
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#include "fwrisc_instr_tests_exception.h"
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fwrisc_instr_tests_exception::fwrisc_instr_tests_exception() {
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        // TODO Auto-generated constructor stub
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}
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fwrisc_instr_tests_exception::~fwrisc_instr_tests_exception() {
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        // TODO Auto-generated destructor stub
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}
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TEST_F(fwrisc_instr_tests_exception, j) {
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        reg_val_s exp[] = {
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                        {8,     4},
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                        {37,    0x8000002C}, // MTVEC
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                        {41,    0x80000018}, // MEPC
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                        {42,    0x00000000}, // MCAUSE
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                        {43,    0x80000022}, // MTVAL
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        };
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        const char *program = R"(
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                entry:
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                        la              x8, _trap_handler
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                        csrw    mtvec, x8
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                        j               1f+2            // Jump will not be taken, since the address is misaligned
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                        li              x8, 4           // When we come back, clear out x8
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                        j               done
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                1:
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                        li              x8, 26
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                        j               done
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                        nop
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                _trap_handler:
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                        csrr    x8, mepc // Increment beyond the faulting instruction
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                        addi    x8, x8, 4
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                        csrw    mepc, x8
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                        mret
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                        )";
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        runtest(program, exp, sizeof(exp)/sizeof(reg_val_s));
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}
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TEST_F(fwrisc_instr_tests_exception, jalr) {
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        reg_val_s exp[] = {
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                        {8,     4},
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                        {9,     0x80000028},
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                        {37,    0x80000034}, // MTVEC
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                        {41,    0x80000020}, // MEPC
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                        {42,    0x00000000}, // MCAUSE
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                        {43,    0x8000002a}, // MTVAL
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        };
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        const char *program = R"(
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                entry:
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                        la              x8, _trap_handler
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                        csrw    mtvec, x8
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                        la              x9, 1f
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                        jalr    2(x9)           // Jump will not be taken, since the address is misaligned
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                        li              x8, 4           // When we come back, clear out x8
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                        j               done
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                1:
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                        li              x8, 26
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                        j               done
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                        nop
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                _trap_handler:
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                        csrr    x8, mepc // Increment beyond the faulting instruction
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                        addi    x8, x8, 4
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                        csrw    mepc, x8
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                        mret
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                        )";
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        runtest(program, exp, sizeof(exp)/sizeof(reg_val_s));
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}
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TEST_F(fwrisc_instr_tests_exception, lw) {
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        reg_val_s exp[] = {
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                        {8,     4},
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                        {9,     0x80000044},
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                        {37,    0x80000034}, // MTVEC
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                        {41,    0x80000020}, // MEPC
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                        {42,    0x00000004}, // MCAUSE
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                        {43,    0x80000046}, // MTVAL
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        };
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        const char *program = R"(
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                entry:
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                        la              x8, _trap_handler
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                        csrw    mtvec, x8
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                        la              x9, data
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                        lw              x7, 2(x9)
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                        li              x8, 4           // When we come back, clear out x8
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                        j               done
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                1:
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                        li              x8, 26
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                        j               done
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                        nop
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                _trap_handler:
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                        csrr    x8, mepc // Increment beyond the faulting instruction
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                        addi    x8, x8, 4
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                        csrw    mepc, x8
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                        mret
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                data:
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                        .word   0x01020304
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                        .word   0x05060708
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                        )";
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        runtest(program, exp, sizeof(exp)/sizeof(reg_val_s));
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}
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TEST_F(fwrisc_instr_tests_exception, bne) {
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        reg_val_s exp[] = {
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                        {8,     4},
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                        {37,    0x8000002C}, // MTVEC
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                        {41,    0x80000018}, // MEPC
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                        {42,    0x00000000}, // MCAUSE
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                        {43,    0x80000022}, // MTVAL
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        };
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        const char *program = R"(
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                entry:
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                        la              x8, _trap_handler
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                        csrw    mtvec, x8
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                        bne             x8, zero, 1f+2  // Jump will not be taken, since the address is misaligned
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                        li              x8, 4                           // When we come back, clear out x8
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                        j               done
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                1:
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                        li              x8, 26
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                        j               done
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                        nop
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                _trap_handler:
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                        csrr    x8, mepc // Increment beyond the faulting instruction
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                        addi    x8, x8, 4
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                        csrw    mepc, x8
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                        mret
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                        )";
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        runtest(program, exp, sizeof(exp)/sizeof(reg_val_s));
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}

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