OpenCores
URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [Makefrag] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mballance
# RISC-V Compliance Test RV32I Makefrag
2
#
3
# Copyright (c) 2017, Codasip Ltd.
4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions are met:
8
#      * Redistributions of source code must retain the above copyright
9
#        notice, this list of conditions and the following disclaimer.
10
#      * Redistributions in binary form must reproduce the above copyright
11
#        notice, this list of conditions and the following disclaimer in the
12
#        documentation and/or other materials provided with the distribution.
13
#      * Neither the name of the Codasip Ltd. nor the
14
#        names of its contributors may be used to endorse or promote products
15
#        derived from this software without specific prior written permission.
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
18
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
21
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
28
# Description: Makefrag for RV32I compliance tests
29
 
30
rv32i_sc_tests =    \
31
    I-ENDIANESS-01 \
32
    I-RF_x0-01 \
33
    I-RF_size-01 \
34
    I-RF_width-01 \
35
    I-MISALIGN_JMP-01 \
36
    I-MISALIGN_LDST-01 \
37
    I-DELAY_SLOTS-01 \
38
    I-JAL-01 \
39
    I-JALR-01 \
40
    I-LUI-01 \
41
    I-AUIPC-01 \
42
    I-LW-01 \
43
    I-LH-01 \
44
    I-LHU-01 \
45
    I-LB-01 \
46
    I-LBU-01 \
47
    I-SW-01 \
48
    I-SH-01 \
49
    I-SB-01 \
50
    I-ADD-01 \
51
    I-ADDI-01 \
52
    I-AND-01 \
53
    I-OR-01 \
54
    I-ORI-01 \
55
    I-XORI-01 \
56
    I-XOR-01 \
57
    I-SUB-01 \
58
    I-ANDI-01 \
59
    I-FENCE.I-01 \
60
    I-SLTI-01 \
61
    I-SLTIU-01 \
62
    I-BEQ-01 \
63
    I-BNE-01 \
64
    I-BLT-01 \
65
    I-BLTU-01 \
66
    I-BGE-01 \
67
    I-BGEU-01 \
68
    I-SRLI-01 \
69
    I-SLLI-01 \
70
    I-SRAI-01 \
71
    I-SLL-01 \
72
    I-SRL-01 \
73
    I-SRA-01 \
74
    I-SLT-01 \
75
    I-SLTU-01 \
76
    I-CSRRW-01 \
77
    I-CSRRWI-01 \
78
    I-NOP-01 \
79
    I-CSRRS-01 \
80
    I-CSRRSI-01 \
81
    I-CSRRC-01 \
82
    I-CSRRCI-01 \
83
    I-ECALL-01 \
84
    I-EBREAK-01 \
85
    I-IO \
86
 
87
 
88
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
89
 
90
target32_tests += $(rv32i_tests)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.