URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-LBU-01.S] - Blame information for rev 2

Details | Compare with Previous | View Log


# RISC-V Compliance Test I-LBU-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction LBU.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");
 
    # Addresses for test data and results
    la      x31, test_A1_data
    la      x2, test_A1_res
 
    # Test
    lbu     x3, 0(x31)
    lbu     x4, 1(x31)
    lbu     x5, 2(x31)
    lbu     x6, 3(x31)
 
    # Store results
    sw      x3, 0(x2)
    sw      x4, 4(x2)
    sw      x5, 8(x2)
    sw      x6, 12(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000022)
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x000000F2)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000011)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000011)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");
 
    # Addresses for test data and results
    la      x24, test_A2_data + 1
    la      x5, test_A2_res
 
    # Test
    lbu     x25, -1(x24)
    lbu     x26, +0(x24)
    lbu     x27, +1(x24)
    lbu     x28, +2(x24)
 
    # Store results
    sw      x25, 0(x5)
    sw      x26, 4(x5)
    sw      x27, 8(x5)
    sw      x28, 12(x5)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000F4)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x00000044)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000033)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x000000F3)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");
 
    # Addresses for test data and results
    la      x7, test_A3_data - 1
    la      x8, test_A3_res
 
    # Test
    lbu     x30, 1(x7)
    lbu     x31, 2(x7)
    lbu     x1, 3(x7)
    lbu     x2, 4(x7)
 
    # Store results
    sw      x30, 0(x8)
    sw      x31, 4(x8)
    sw      x1, 8(x8)
    sw      x2, 12(x8)
 
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00000066)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0x000000F6)
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80000920)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x00000055)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");
 
    # Addresses for test data and results
    la      x10, test_A4_data + 2048
    la      x11, test_A4_res
 
    # Test
    lbu     x12, 0xFFFFF800(x10)
    lbu     x13, 0xFFFFF801(x10)
    lbu     x14, 0xFFFFF802(x10)
    lbu     x15, 0xFFFFF803(x10)
 
    # Store results
    sw      x12, 0(x11)
    sw      x13, 4(x11)
    sw      x14, 8(x11)
    sw      x15, 12(x11)
 
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x000000F8)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000088)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000077)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x000000F7)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");
 
    # Addresses for test data and results
    la      x13, test_A5_data - 2044
    la      x14, test_A5_res
 
    # Test
    lbu     x15, 0x7FC(x13)
    lbu     x16, 0x7FD(x13)
    lbu     x17, 0x7FE(x13)
    lbu     x18, 0x7FF(x13)
 
    # Store results
    sw      x15, 0(x14)
    sw      x16, 4(x14)
    sw      x17, 8(x14)
    sw      x18, 12(x14)
 
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x000000AA)
    RVTEST_IO_ASSERT_GPR_EQ(x16, 0x0000000A)
    RVTEST_IO_ASSERT_GPR_EQ(x17, 0x00000009)
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x00000099)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - test base address + -4,-1, ..., 6, 7\n");
 
    # Addresses for test data and results
    la      x16, test_B_data
    la      x17, test_B_res
 
    # Test
    lbu     x18, -4(x16)
    lbu     x19, -3(x16)
    lbu     x20, -2(x16)
    lbu     x21, -1(x16)
    lbu     x22, 0(x16)
    lbu     x23, 1(x16)
    lbu     x24, 2(x16)
    lbu     x25, 3(x16)
    lbu     x26, 4(x16)
    lbu     x27, 5(x16)
    lbu     x28, 6(x16)
    lbu     x29, 7(x16)
 
    # Store results
    sw      x18, 0(x17)
    sw      x19, 4(x17)
    sw      x20, 8(x17)
    sw      x21, 12(x17)
    sw      x22, 16(x17)
    sw      x23, 20(x17)
    sw      x24, 24(x17)
    sw      x25, 28(x17)
    sw      x26, 32(x17)
    sw      x27, 36(x17)
    sw      x28, 40(x17)
    sw      x29, 44(x17)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0000000C)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x000000CC)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x000000BB)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x0000000B)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0x000000EE)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x0000000E)
    RVTEST_IO_ASSERT_GPR_EQ(x24, 0x0000000D)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000DD)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x000000F0)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x000000FF)
    RVTEST_IO_ASSERT_GPR_EQ(x29, 0x0000000F)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - test load to x0\n");
 
    # Addresses for test data and results
    la      x21, test_C_data
    la      x22, test_C_res
 
    # Test
    lbu     x0, 0(x21)
 
    # Store results
    sw      x0, 0(x22)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D - test for forwarding\n");
 
    # Addresses for test data and results
    la      x21, test_D_data
    la      x22, test_D_res
 
    # Test
    lw      x23, 0(x21)
    lbu     x24, 0(x23)
    mv      x25, x24
 
    # Store results
    sw      x25, 0(x22)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000F0)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E1 - test store with same base and destination address\n");
 
    # Addresses for test data and results
    la      x25, test_E1_data
    la      x26, test_E1_res
 
    # Test
    lbu     x25, 0(x25)
 
    # Store results
    sw      x25, 0(x26)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000010)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E2 - test store with same base and destination address, base with offset\n");
 
    # Addresses for test data and results
    la      x27, test_E2_data + 1
    la      x28, test_E2_res
 
    # Test
    lbu     x27, -1(x27)
 
    # Store results
    sw      x27, 0(x28)
 
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000098)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_A1_data:
    .word 0x11F1F222
test_A2_data:
    .word 0xF33344F4
test_A3_data:
    .word 0x55F5F666
test_A4_data:
    .word 0xF77788F8
test_A5_data:
    .word 0x99090AAA
    .word 0x0BBBCC0C
test_B_data:
    .word 0xDD0D0EEE
    .word 0x0FFF00F0
test_C_data:
    .word 0x12345678
test_D_data:
    .word test_D_data2_label
test_D_data2_label:
    .word 0x9ABCDEF0
test_E1_data:
    .word 0x76543210
test_E2_data:
    .word 0xFEDCBA98
 
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 4, 4, -1
test_A2_res:
    .fill 4, 4, -1
test_A3_res:
    .fill 4, 4, -1
test_A4_res:
    .fill 4, 4, -1
test_A5_res:
    .fill 4, 4, -1
test_B_res:
    .fill 12, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D_res:
    .fill 1, 4, -1
test_E1_res:
    .fill 1, 4, -1
test_E2_res:
    .fill 1, 4, -1
 
RV_COMPLIANCE_DATA_END

Browse

Tools

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-LBU-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-LBU-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction LBU.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");`
48
49			`# Addresses for test data and results`
50			`la x31, test_A1_data`
51			`la x2, test_A1_res`
52
53			`# Test`
54			`lbu x3, 0(x31)`
55			`lbu x4, 1(x31)`
56			`lbu x5, 2(x31)`
57			`lbu x6, 3(x31)`
58
59			`# Store results`
60			`sw x3, 0(x2)`
61			`sw x4, 4(x2)`
62			`sw x5, 8(x2)`
63			`sw x6, 12(x2)`
64
65			`//`
66			`// Assert`
67			`//`
68			`RVTEST_IO_CHECK()`
69			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000022)`
70			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x000000F2)`
71			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000011)`
72			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000011)`
73
74			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
75
76			`# ---------------------------------------------------------------------------------------------`
77			`RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");`
78
79			`# Addresses for test data and results`
80			`la x24, test_A2_data + 1`
81			`la x5, test_A2_res`
82
83			`# Test`
84			`lbu x25, -1(x24)`
85			`lbu x26, +0(x24)`
86			`lbu x27, +1(x24)`
87			`lbu x28, +2(x24)`
88
89			`# Store results`
90			`sw x25, 0(x5)`
91			`sw x26, 4(x5)`
92			`sw x27, 8(x5)`
93			`sw x28, 12(x5)`
94
95			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000F4)`
96			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x00000044)`
97			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000033)`
98			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x000000F3)`
99
100			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
101
102			`# ---------------------------------------------------------------------------------------------`
103			`RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");`
104
105			`# Addresses for test data and results`
106			`la x7, test_A3_data - 1`
107			`la x8, test_A3_res`
108
109			`# Test`
110			`lbu x30, 1(x7)`
111			`lbu x31, 2(x7)`
112			`lbu x1, 3(x7)`
113			`lbu x2, 4(x7)`
114
115			`# Store results`
116			`sw x30, 0(x8)`
117			`sw x31, 4(x8)`
118			`sw x1, 8(x8)`
119			`sw x2, 12(x8)`
120
121			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00000066)`
122			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0x000000F6)`
123			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80000920)`
124			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x00000055)`
125
126			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
127
128			`# ---------------------------------------------------------------------------------------------`
129			`RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");`
130
131			`# Addresses for test data and results`
132			`la x10, test_A4_data + 2048`
133			`la x11, test_A4_res`
134
135			`# Test`
136			`lbu x12, 0xFFFFF800(x10)`
137			`lbu x13, 0xFFFFF801(x10)`
138			`lbu x14, 0xFFFFF802(x10)`
139			`lbu x15, 0xFFFFF803(x10)`
140
141			`# Store results`
142			`sw x12, 0(x11)`
143			`sw x13, 4(x11)`
144			`sw x14, 8(x11)`
145			`sw x15, 12(x11)`
146
147			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x000000F8)`
148			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000088)`
149			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000077)`
150			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x000000F7)`
151
152			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
153
154			`# ---------------------------------------------------------------------------------------------`
155			`RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");`
156
157			`# Addresses for test data and results`
158			`la x13, test_A5_data - 2044`
159			`la x14, test_A5_res`
160
161			`# Test`
162			`lbu x15, 0x7FC(x13)`
163			`lbu x16, 0x7FD(x13)`
164			`lbu x17, 0x7FE(x13)`
165			`lbu x18, 0x7FF(x13)`
166
167			`# Store results`
168			`sw x15, 0(x14)`
169			`sw x16, 4(x14)`
170			`sw x17, 8(x14)`
171			`sw x18, 12(x14)`
172
173			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x000000AA)`
174			`RVTEST_IO_ASSERT_GPR_EQ(x16, 0x0000000A)`
175			`RVTEST_IO_ASSERT_GPR_EQ(x17, 0x00000009)`
176			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x00000099)`
177
178			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
179
180			`# ---------------------------------------------------------------------------------------------`
181			`RVTEST_IO_WRITE_STR("# Test part B - test base address + -4,-1, ..., 6, 7\n");`
182
183			`# Addresses for test data and results`
184			`la x16, test_B_data`
185			`la x17, test_B_res`
186
187			`# Test`
188			`lbu x18, -4(x16)`
189			`lbu x19, -3(x16)`
190			`lbu x20, -2(x16)`
191			`lbu x21, -1(x16)`
192			`lbu x22, 0(x16)`
193			`lbu x23, 1(x16)`
194			`lbu x24, 2(x16)`
195			`lbu x25, 3(x16)`
196			`lbu x26, 4(x16)`
197			`lbu x27, 5(x16)`
198			`lbu x28, 6(x16)`
199			`lbu x29, 7(x16)`
200
201			`# Store results`
202			`sw x18, 0(x17)`
203			`sw x19, 4(x17)`
204			`sw x20, 8(x17)`
205			`sw x21, 12(x17)`
206			`sw x22, 16(x17)`
207			`sw x23, 20(x17)`
208			`sw x24, 24(x17)`
209			`sw x25, 28(x17)`
210			`sw x26, 32(x17)`
211			`sw x27, 36(x17)`
212			`sw x28, 40(x17)`
213			`sw x29, 44(x17)`
214
215			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x0000000C)`
216			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x000000CC)`
217			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x000000BB)`
218			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x0000000B)`
219			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0x000000EE)`
220			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x0000000E)`
221			`RVTEST_IO_ASSERT_GPR_EQ(x24, 0x0000000D)`
222			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000DD)`
223			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x000000F0)`
224			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000000)`
225			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x000000FF)`
226			`RVTEST_IO_ASSERT_GPR_EQ(x29, 0x0000000F)`
227
228			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
229
230			`# ---------------------------------------------------------------------------------------------`
231			`RVTEST_IO_WRITE_STR("# Test part C - test load to x0\n");`
232
233			`# Addresses for test data and results`
234			`la x21, test_C_data`
235			`la x22, test_C_res`
236
237			`# Test`
238			`lbu x0, 0(x21)`
239
240			`# Store results`
241			`sw x0, 0(x22)`
242
243			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
244
245			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
246
247			`# ---------------------------------------------------------------------------------------------`
248			`RVTEST_IO_WRITE_STR("# Test part D - test for forwarding\n");`
249
250			`# Addresses for test data and results`
251			`la x21, test_D_data`
252			`la x22, test_D_res`
253
254			`# Test`
255			`lw x23, 0(x21)`
256			`lbu x24, 0(x23)`
257			`mv x25, x24`
258
259			`# Store results`
260			`sw x25, 0(x22)`
261
262			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x000000F0)`
263
264			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
265
266			`# ---------------------------------------------------------------------------------------------`
267			`RVTEST_IO_WRITE_STR("# Test part E1 - test store with same base and destination address\n");`
268
269			`# Addresses for test data and results`
270			`la x25, test_E1_data`
271			`la x26, test_E1_res`
272
273			`# Test`
274			`lbu x25, 0(x25)`
275
276			`# Store results`
277			`sw x25, 0(x26)`
278
279			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000010)`
280
281			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
282
283			`# ---------------------------------------------------------------------------------------------`
284			`RVTEST_IO_WRITE_STR("# Test part E2 - test store with same base and destination address, base with offset\n");`
285
286			`# Addresses for test data and results`
287			`la x27, test_E2_data + 1`
288			`la x28, test_E2_res`
289
290			`# Test`
291			`lbu x27, -1(x27)`
292
293			`# Store results`
294			`sw x27, 0(x28)`
295
296			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000098)`
297
298			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
299
300			`RVTEST_IO_WRITE_STR("# Test End\n")`
301
302			`# ---------------------------------------------------------------------------------------------`
303			`# HALT`
304			`RV_COMPLIANCE_HALT`
305
306			`RV_COMPLIANCE_CODE_END`
307
308			`# Input data section.`
309			`.data`
310			`.align 4`
311
312			`test_A1_data:`
313			`.word 0x11F1F222`
314			`test_A2_data:`
315			`.word 0xF33344F4`
316			`test_A3_data:`
317			`.word 0x55F5F666`
318			`test_A4_data:`
319			`.word 0xF77788F8`
320			`test_A5_data:`
321			`.word 0x99090AAA`
322			`.word 0x0BBBCC0C`
323			`test_B_data:`
324			`.word 0xDD0D0EEE`
325			`.word 0x0FFF00F0`
326			`test_C_data:`
327			`.word 0x12345678`
328			`test_D_data:`
329			`.word test_D_data2_label`
330			`test_D_data2_label:`
331			`.word 0x9ABCDEF0`
332			`test_E1_data:`
333			`.word 0x76543210`
334			`test_E2_data:`
335			`.word 0xFEDCBA98`
336
337
338			`# Output data section.`
339			`RV_COMPLIANCE_DATA_BEGIN`
340			`.align 4`
341
342			`test_A1_res:`
343			`.fill 4, 4, -1`
344			`test_A2_res:`
345			`.fill 4, 4, -1`
346			`test_A3_res:`
347			`.fill 4, 4, -1`
348			`test_A4_res:`
349			`.fill 4, 4, -1`
350			`test_A5_res:`
351			`.fill 4, 4, -1`
352			`test_B_res:`
353			`.fill 12, 4, -1`
354			`test_C_res:`
355			`.fill 1, 4, -1`
356			`test_D_res:`
357			`.fill 1, 4, -1`
358			`test_E1_res:`
359			`.fill 1, 4, -1`
360			`test_E2_res:`
361			`.fill 1, 4, -1`
362
363			`RV_COMPLIANCE_DATA_END`