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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-MISALIGN_LDST-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-MISALIGN_LDST-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing MISALIGNED LOAD/STORE exception.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # Save and set trap handler address
    la x1, _trap_handler
    csrrw x31, mtvec, x1
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test LW\n");
 
    # Addresses for test data and results
    la      x3, test_A1_data
    la      x2, test_A1_res
    la      x1, test_A1_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    lw      x4, 0(x3)
    sw      x4, 0(x2)
 
    lw      x4, 1(x3)
    sw      x4, 4(x2)
 
    lw      x4, 2(x3)
    sw      x4, 8(x2)
 
    lw      x4, 3(x3)
    sw      x4, 12(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x91A1B1C1)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test LH and LHU\n");
 
    # Addresses for test data and results
    la      x3, test_A2_data
    la      x2, test_A2_res
    la      x1, test_A2_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    lh      x4, 0(x3)
    sw      x4, 0(x2)
 
    lh      x4, 1(x3)
    sw      x4, 4(x2)
 
    lh      x4, 2(x3)
    sw      x4, 8(x2)
 
    lh      x4, 3(x3)
    sw      x4, 12(x2)
 
    lhu     x4, 0(x3)
    sw      x4, 16(x2)
 
    lhu     x4, 1(x3)
    sw      x4, 20(x2)
 
    lhu     x4, 2(x3)
    sw      x4, 24(x2)
 
    lhu     x4, 3(x3)
    sw      x4, 28(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x0000D2E2)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B1 - test SW\n");
 
    # Addresses for test data and results
    la      x2, test_B1_res
    la      x1, test_B1_res_exc
 
    # Register initialization
    li      x6, 0x0
    li      x5, 0x99999999
 
    # Init memory
    sw      x5, 0(x2)
    sw      x5, 4(x2)
    sw      x5, 8(x2)
    sw      x5, 12(x2)
 
    # Test
    sw      x6, 0(x2)
    addi    x2, x2, 4
 
    sw      x6, 1(x2)
    addi    x2, x2, 4
 
    sw      x6, 2(x2)
    addi    x2, x2, 4
 
    sw      x6, 3(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x800035D4)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B2 - test SH\n");
 
    # Addresses for test data and results
    la      x2, test_B2_res
    la      x1, test_B2_res_exc
 
    # Register initialization
    li      x6, 0x0
    li      x5, 0x99999999
 
    # Init memory
    sw      x5, 0(x2)
    sw      x5, 4(x2)
    sw      x5, 8(x2)
    sw      x5, 12(x2)
 
    # Test
    sh      x6, 0(x2)
    addi    x2, x2, 4
 
    sh      x6, 1(x2)
    addi    x2, x2, 4
 
    sh      x6, 2(x2)
    addi    x2, x2, 4
 
    sh      x6, 3(x2)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    # restore mtvec and jump to the end
    csrw mtvec, x31
    jal x0, test_end
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    # Exception handler
_trap_handler:
    # increment return address
    csrr    x30, mepc
    addi    x30, x30, 4
    csrw    mepc, x30
 
    # store low bits of MBADADDR
    csrr    x30, mbadaddr
    andi    x30, x30, 3
    sw      x30, 0(x1)
 
    # Store MCAUSE
    csrr    x30, mcause
    sw      x30, 4(x1)
 
    # increment data_exc address
    addi    x1, x1, 8
 
    # return
    mret
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
 
test_end:
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_A1_data:
    .word 0x91A1B1C1
test_A2_data:
    .word 0xD2E2F202
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 4, 4, -1
test_A1_res_exc:
    .fill 6, 4, -1
test_A2_res:
    .fill 8, 4, -1
test_A2_res_exc:
    .fill 8, 4, -1
test_B1_res:
    .fill 4, 4, -1
test_B1_res_exc:
    .fill 6, 4, -1
test_B2_res:
    .fill 4, 4, -1
test_B2_res_exc:
    .fill 4, 4, -1
 
RV_COMPLIANCE_DATA_END

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-MISALIGN_LDST-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-MISALIGN_LDST-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing MISALIGNED LOAD/STORE exception.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# Save and set trap handler address`
47			`la x1, _trap_handler`
48			`csrrw x31, mtvec, x1`
49
50			`# ---------------------------------------------------------------------------------------------`
51			`RVTEST_IO_WRITE_STR("# Test part A1 - test LW\n");`
52
53			`# Addresses for test data and results`
54			`la x3, test_A1_data`
55			`la x2, test_A1_res`
56			`la x1, test_A1_res_exc`
57
58			`# Register initialization`
59			`li x5, 5`
60			`li x6, 6`
61
62			`# Test`
63			`lw x4, 0(x3)`
64			`sw x4, 0(x2)`
65
66			`lw x4, 1(x3)`
67			`sw x4, 4(x2)`
68
69			`lw x4, 2(x3)`
70			`sw x4, 8(x2)`
71
72			`lw x4, 3(x3)`
73			`sw x4, 12(x2)`
74
75			`//`
76			`// Assert`
77			`//`
78			`RVTEST_IO_CHECK()`
79			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x91A1B1C1)`
80
81			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
82
83			`# ---------------------------------------------------------------------------------------------`
84			`RVTEST_IO_WRITE_STR("# Test part A2 - test LH and LHU\n");`
85
86			`# Addresses for test data and results`
87			`la x3, test_A2_data`
88			`la x2, test_A2_res`
89			`la x1, test_A2_res_exc`
90
91			`# Register initialization`
92			`li x5, 5`
93			`li x6, 6`
94
95			`# Test`
96			`lh x4, 0(x3)`
97			`sw x4, 0(x2)`
98
99			`lh x4, 1(x3)`
100			`sw x4, 4(x2)`
101
102			`lh x4, 2(x3)`
103			`sw x4, 8(x2)`
104
105			`lh x4, 3(x3)`
106			`sw x4, 12(x2)`
107
108			`lhu x4, 0(x3)`
109			`sw x4, 16(x2)`
110
111			`lhu x4, 1(x3)`
112			`sw x4, 20(x2)`
113
114			`lhu x4, 2(x3)`
115			`sw x4, 24(x2)`
116
117			`lhu x4, 3(x3)`
118			`sw x4, 28(x2)`
119
120			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x0000D2E2)`
121
122			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
123
124			`# ---------------------------------------------------------------------------------------------`
125			`RVTEST_IO_WRITE_STR("# Test part B1 - test SW\n");`
126
127			`# Addresses for test data and results`
128			`la x2, test_B1_res`
129			`la x1, test_B1_res_exc`
130
131			`# Register initialization`
132			`li x6, 0x0`
133			`li x5, 0x99999999`
134
135			`# Init memory`
136			`sw x5, 0(x2)`
137			`sw x5, 4(x2)`
138			`sw x5, 8(x2)`
139			`sw x5, 12(x2)`
140
141			`# Test`
142			`sw x6, 0(x2)`
143			`addi x2, x2, 4`
144
145			`sw x6, 1(x2)`
146			`addi x2, x2, 4`
147
148			`sw x6, 2(x2)`
149			`addi x2, x2, 4`
150
151			`sw x6, 3(x2)`
152
153			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x800035D4)`
154
155			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
156
157			`# ---------------------------------------------------------------------------------------------`
158			`RVTEST_IO_WRITE_STR("# Test part B2 - test SH\n");`
159
160			`# Addresses for test data and results`
161			`la x2, test_B2_res`
162			`la x1, test_B2_res_exc`
163
164			`# Register initialization`
165			`li x6, 0x0`
166			`li x5, 0x99999999`
167
168			`# Init memory`
169			`sw x5, 0(x2)`
170			`sw x5, 4(x2)`
171			`sw x5, 8(x2)`
172			`sw x5, 12(x2)`
173
174			`# Test`
175			`sh x6, 0(x2)`
176			`addi x2, x2, 4`
177
178			`sh x6, 1(x2)`
179			`addi x2, x2, 4`
180
181			`sh x6, 2(x2)`
182			`addi x2, x2, 4`
183
184			`sh x6, 3(x2)`
185
186			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
187
188			`# ---------------------------------------------------------------------------------------------`
189			`# restore mtvec and jump to the end`
190			`csrw mtvec, x31`
191			`jal x0, test_end`
192
193			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
194
195			`# ---------------------------------------------------------------------------------------------`
196			`# Exception handler`
197			`_trap_handler:`
198			`# increment return address`
199			`csrr x30, mepc`
200			`addi x30, x30, 4`
201			`csrw mepc, x30`
202
203			`# store low bits of MBADADDR`
204			`csrr x30, mbadaddr`
205			`andi x30, x30, 3`
206			`sw x30, 0(x1)`
207
208			`# Store MCAUSE`
209			`csrr x30, mcause`
210			`sw x30, 4(x1)`
211
212			`# increment data_exc address`
213			`addi x1, x1, 8`
214
215			`# return`
216			`mret`
217
218			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
219
220			`# ---------------------------------------------------------------------------------------------`
221
222			`test_end:`
223
224			`RVTEST_IO_WRITE_STR("# Test End\n")`
225
226			`# ---------------------------------------------------------------------------------------------`
227			`# HALT`
228			`RV_COMPLIANCE_HALT`
229
230			`RV_COMPLIANCE_CODE_END`
231
232			`# Input data section.`
233			`.data`
234			`.align 4`
235
236			`test_A1_data:`
237			`.word 0x91A1B1C1`
238			`test_A2_data:`
239			`.word 0xD2E2F202`
240
241			`# Output data section.`
242			`RV_COMPLIANCE_DATA_BEGIN`
243			`.align 4`
244
245			`test_A1_res:`
246			`.fill 4, 4, -1`
247			`test_A1_res_exc:`
248			`.fill 6, 4, -1`
249			`test_A2_res:`
250			`.fill 8, 4, -1`
251			`test_A2_res_exc:`
252			`.fill 8, 4, -1`
253			`test_B1_res:`
254			`.fill 4, 4, -1`
255			`test_B1_res_exc:`
256			`.fill 6, 4, -1`
257			`test_B2_res:`
258			`.fill 4, 4, -1`
259			`test_B2_res_exc:`
260			`.fill 4, 4, -1`
261
262			`RV_COMPLIANCE_DATA_END`