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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SH-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-SH-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction SH.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");
 
    # Address for test results
    la      x1, test_A1_res
 
    # Set memory
    li      x31, 0xAAAABBBB
    sw      x31, 0(x1)
 
    # Test
    li      x2, 0x11F1F222
    sh      x2, 0(x1)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x11F1F222)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0xAAAABBBB)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");
 
    # Address for test results
    la      x5, test_A2_res + 1
 
    # Clear memory
    sw      x0, -1(x5)
 
    # Test
    li      x25, 0xF33344F4
    sh      x25, 0xFFFFFFFF(x5)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0xF33344F4)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");
 
    # Address for test results
    la      x8, test_A3_res - 1
 
    # Clear memory
    sw      x0, 1(x8)
 
    # Test
    li      x31, 0x55F5F666
    sh      x31, +1(x8)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0x55F5F666)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");
 
    # Address for test results
    la      x11, test_A4_res + 2048
 
    # Clear memory
    sw      x0, -2048(x11)
 
    # Test
    li      x12, 0xF77788F8
    sh      x12, 0xFFFFF800(x11)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0xF77788F8)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");
 
    # Address for test results
    la      x14, test_A5_res - 2047
 
    # Clear memory
    sw      x0, 2047(x14)
 
    # Test
    li      x15, 0x99090AAA
    sh      x15, 0x7FF(x14)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x99090AAA)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, -2, ... , 6\n");
 
    # Address for test results
    la      x17, test_B_res
 
    # Test
    li      x18, 0x1111CC0C
    li      x19, 0x22220BBB
    li      x20, 0x33330EEE
    li      x21, 0x4444DD0D
    li      x22, 0x777700F0
    li      x23, 0x66660FFF
 
    # Store results
    sh      x18, -4(x17)
    sh      x19, -2(x17)
    sh      x20, 0(x17)
    sh      x21, 2(x17)
    sh      x22, 4(x17)
    sh      x23, 6(x17)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x1111CC0C)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x22220BBB)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x33330EEE)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x4444DD0D)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0x777700F0)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x66660FFF)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - test store x0\n");
 
    # Address for test results
    la      x22, test_C_res
 
    # Set memory
    li      x1, 0x87654321
    sw      x1, 0(x22)
 
    # Test
    li      x0, 0x12345678
    sh      x0, 0(x22)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x1, 0x87654321)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D1 - test for forwarding (to address register)\n");
 
    # Address for test data
    la      x21, test_D1_data
 
    # Clear memory
    lw      x1, 0(x21)
    sw      x0, 0(x1)
 
    # Test
    li      x19, 0x11223344
    lw      x23, 0(x21)
    sh      x19, 0(x23)
 
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x11223344)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D2 - test for forwarding (to data register)\n");
 
    # Address for test data
    la      x23, test_D2_data
    la      x24, test_D2_res
 
    # Clear memory
    sw      x0, 0(x24)
 
    # Test
    lw      x25, 0(x23)
    sh      x25, 0(x24)
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x9ABCDEF0)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E1 - test war hazard (data register)\n");
 
    # Address for test results
    la      x26, test_E1_res
 
    # Clear memory
    sw      x0, 0(x26)
 
    # Test
    li      x25, 0x76543210
    sh      x25, 0(x26)
    mv      x25, x0
 
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E2 - test war hazard (address register)\n");
 
    # Address for test results
    la      x28, test_E2_res
 
    # Clear memory
    sw      x0, 0(x28)
 
    # Test
    li      x27, 0x89ABCDEF
    sh      x27, 0(x28)
    addi    x28, x28, -4
 
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x89ABCDEF)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x8000403C)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part F - test raw hazard in memory\n");
 
    # Address for test results
    la      x29, test_F_res
 
    # Clear memory
    sw      x0, 0(x29)
    sw      x0, 4(x29)
 
    # Test
    li      x27, 0x14725836
    sh      x27, 0(x29)
    lw      x30, 0(x29)
    sh      x30, 4(x29)
 
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x14725836)
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00005836)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part G - test waw hazard in memory\n");
 
    # Address for test results
    la      x1, test_G_res
 
    # Clear memory
    sw      x0, 0(x1)
 
    # Test
    li      x2, 0x96385201
    li      x3, 0x25814963
    sh      x2, 0(x1)
    sh      x3, 0(x1)
 
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x96385201)
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x25814963)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_D1_data:
    .word test_D1_res
test_D2_data:
    .word 0x9ABCDEF0
 
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 1, 4, -1
test_A2_res:
    .fill 1, 4, -1
test_A3_res:
    .fill 1, 4, -1
test_A4_res:
    .fill 1, 4, -1
test_A5_res:
    .fill 1, 4, -1
    .fill 1, 4, -1
test_B_res:
    .fill 2, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D1_res:
    .fill 1, 4, -1
test_D2_res:
    .fill 1, 4, -1
test_E1_res:
    .fill 1, 4, -1
test_E2_res:
    .fill 1, 4, -1
test_F_res:
    .fill 2, 4, -1
test_G_res:
    .fill 1, 4, -1
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SH-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-SH-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction SH.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - test base address + 0\n");`
48
49			`# Address for test results`
50			`la x1, test_A1_res`
51
52			`# Set memory`
53			`li x31, 0xAAAABBBB`
54			`sw x31, 0(x1)`
55
56			`# Test`
57			`li x2, 0x11F1F222`
58			`sh x2, 0(x1)`
59
60			`//`
61			`// Assert`
62			`//`
63			`RVTEST_IO_CHECK()`
64			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x11F1F222)`
65			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0xAAAABBBB)`
66
67			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
68
69			`# ---------------------------------------------------------------------------------------------`
70			`RVTEST_IO_WRITE_STR("# Test part A2 - test base address - 1\n");`
71
72			`# Address for test results`
73			`la x5, test_A2_res + 1`
74
75			`# Clear memory`
76			`sw x0, -1(x5)`
77
78			`# Test`
79			`li x25, 0xF33344F4`
80			`sh x25, 0xFFFFFFFF(x5)`
81
82			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
83			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0xF33344F4)`
84
85			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
86
87			`# ---------------------------------------------------------------------------------------------`
88			`RVTEST_IO_WRITE_STR("# Test part A3 - test base address + 1\n");`
89
90			`# Address for test results`
91			`la x8, test_A3_res - 1`
92
93			`# Clear memory`
94			`sw x0, 1(x8)`
95
96			`# Test`
97			`li x31, 0x55F5F666`
98			`sh x31, +1(x8)`
99
100			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
101			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0x55F5F666)`
102
103			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
104
105			`# ---------------------------------------------------------------------------------------------`
106			`RVTEST_IO_WRITE_STR("# Test part A4 - test base address - 2048\n");`
107
108			`# Address for test results`
109			`la x11, test_A4_res + 2048`
110
111			`# Clear memory`
112			`sw x0, -2048(x11)`
113
114			`# Test`
115			`li x12, 0xF77788F8`
116			`sh x12, 0xFFFFF800(x11)`
117
118			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
119			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0xF77788F8)`
120
121			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
122
123			`# ---------------------------------------------------------------------------------------------`
124			`RVTEST_IO_WRITE_STR("# Test part A5 - test base address + 2047\n");`
125
126			`# Address for test results`
127			`la x14, test_A5_res - 2047`
128
129			`# Clear memory`
130			`sw x0, 2047(x14)`
131
132			`# Test`
133			`li x15, 0x99090AAA`
134			`sh x15, 0x7FF(x14)`
135
136			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
137			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x99090AAA)`
138
139			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
140
141			`# ---------------------------------------------------------------------------------------------`
142			`RVTEST_IO_WRITE_STR("# Test part B - test base address + -4, -2, ... , 6\n");`
143
144			`# Address for test results`
145			`la x17, test_B_res`
146
147			`# Test`
148			`li x18, 0x1111CC0C`
149			`li x19, 0x22220BBB`
150			`li x20, 0x33330EEE`
151			`li x21, 0x4444DD0D`
152			`li x22, 0x777700F0`
153			`li x23, 0x66660FFF`
154
155			`# Store results`
156			`sh x18, -4(x17)`
157			`sh x19, -2(x17)`
158			`sh x20, 0(x17)`
159			`sh x21, 2(x17)`
160			`sh x22, 4(x17)`
161			`sh x23, 6(x17)`
162
163			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x1111CC0C)`
164			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x22220BBB)`
165			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x33330EEE)`
166			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x4444DD0D)`
167			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0x777700F0)`
168			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x66660FFF)`
169
170			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
171
172			`# ---------------------------------------------------------------------------------------------`
173			`RVTEST_IO_WRITE_STR("# Test part C - test store x0\n");`
174
175			`# Address for test results`
176			`la x22, test_C_res`
177
178			`# Set memory`
179			`li x1, 0x87654321`
180			`sw x1, 0(x22)`
181
182			`# Test`
183			`li x0, 0x12345678`
184			`sh x0, 0(x22)`
185
186			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
187			`RVTEST_IO_ASSERT_GPR_EQ(x1, 0x87654321)`
188
189			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
190
191			`# ---------------------------------------------------------------------------------------------`
192			`RVTEST_IO_WRITE_STR("# Test part D1 - test for forwarding (to address register)\n");`
193
194			`# Address for test data`
195			`la x21, test_D1_data`
196
197			`# Clear memory`
198			`lw x1, 0(x21)`
199			`sw x0, 0(x1)`
200
201			`# Test`
202			`li x19, 0x11223344`
203			`lw x23, 0(x21)`
204			`sh x19, 0(x23)`
205
206			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x11223344)`
207
208			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
209
210			`# ---------------------------------------------------------------------------------------------`
211			`RVTEST_IO_WRITE_STR("# Test part D2 - test for forwarding (to data register)\n");`
212
213			`# Address for test data`
214			`la x23, test_D2_data`
215			`la x24, test_D2_res`
216
217			`# Clear memory`
218			`sw x0, 0(x24)`
219
220			`# Test`
221			`lw x25, 0(x23)`
222			`sh x25, 0(x24)`
223
224			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x9ABCDEF0)`
225
226			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
227
228			`# ---------------------------------------------------------------------------------------------`
229			`RVTEST_IO_WRITE_STR("# Test part E1 - test war hazard (data register)\n");`
230
231			`# Address for test results`
232			`la x26, test_E1_res`
233
234			`# Clear memory`
235			`sw x0, 0(x26)`
236
237			`# Test`
238			`li x25, 0x76543210`
239			`sh x25, 0(x26)`
240			`mv x25, x0`
241
242			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000000)`
243
244			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
245
246			`# ---------------------------------------------------------------------------------------------`
247			`RVTEST_IO_WRITE_STR("# Test part E2 - test war hazard (address register)\n");`
248
249			`# Address for test results`
250			`la x28, test_E2_res`
251
252			`# Clear memory`
253			`sw x0, 0(x28)`
254
255			`# Test`
256			`li x27, 0x89ABCDEF`
257			`sh x27, 0(x28)`
258			`addi x28, x28, -4`
259
260			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x89ABCDEF)`
261			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x8000403C)`
262
263			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
264
265			`# ---------------------------------------------------------------------------------------------`
266			`RVTEST_IO_WRITE_STR("# Test part F - test raw hazard in memory\n");`
267
268			`# Address for test results`
269			`la x29, test_F_res`
270
271			`# Clear memory`
272			`sw x0, 0(x29)`
273			`sw x0, 4(x29)`
274
275			`# Test`
276			`li x27, 0x14725836`
277			`sh x27, 0(x29)`
278			`lw x30, 0(x29)`
279			`sh x30, 4(x29)`
280
281			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x14725836)`
282			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00005836)`
283
284			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
285
286			`# ---------------------------------------------------------------------------------------------`
287			`RVTEST_IO_WRITE_STR("# Test part G - test waw hazard in memory\n");`
288
289			`# Address for test results`
290			`la x1, test_G_res`
291
292			`# Clear memory`
293			`sw x0, 0(x1)`
294
295			`# Test`
296			`li x2, 0x96385201`
297			`li x3, 0x25814963`
298			`sh x2, 0(x1)`
299			`sh x3, 0(x1)`
300
301			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x96385201)`
302			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x25814963)`
303
304			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
305
306			`RVTEST_IO_WRITE_STR("# Test End\n")`
307
308			`# ---------------------------------------------------------------------------------------------`
309			`# HALT`
310			`RV_COMPLIANCE_HALT`
311
312			`RV_COMPLIANCE_CODE_END`
313
314			`# Input data section.`
315			`.data`
316			`.align 4`
317
318			`test_D1_data:`
319			`.word test_D1_res`
320			`test_D2_data:`
321			`.word 0x9ABCDEF0`
322
323
324			`# Output data section.`
325			`RV_COMPLIANCE_DATA_BEGIN`
326			`.align 4`
327
328			`test_A1_res:`
329			`.fill 1, 4, -1`
330			`test_A2_res:`
331			`.fill 1, 4, -1`
332			`test_A3_res:`
333			`.fill 1, 4, -1`
334			`test_A4_res:`
335			`.fill 1, 4, -1`
336			`test_A5_res:`
337			`.fill 1, 4, -1`
338			`.fill 1, 4, -1`
339			`test_B_res:`
340			`.fill 2, 4, -1`
341			`test_C_res:`
342			`.fill 1, 4, -1`
343			`test_D1_res:`
344			`.fill 1, 4, -1`
345			`test_D2_res:`
346			`.fill 1, 4, -1`
347			`test_E1_res:`
348			`.fill 1, 4, -1`
349			`test_E2_res:`
350			`.fill 1, 4, -1`
351			`test_F_res:`
352			`.fill 2, 4, -1`
353			`test_G_res:`
354			`.fill 1, 4, -1`
355
356			`RV_COMPLIANCE_DATA_END`