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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SLTU-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-SLTU-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction SLTU.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A1_data
    la      x2, test_A1_res
 
    # Load testdata
    lw      x3, 0(x1)
 
    # Register initialization
    li      x4, 1
    li      x5, 0x7FFFFFFF
    li      x6, 0xFFFFFFFF
    li      x7, 0
    li      x8, 0x80000000
 
    # Test
    sltu   x4, x3, x4
    sltu   x5, x3, x5
    sltu   x6, x3, x6
    sltu   x7, x3, x7
    sltu   x8, x3, x8
 
    # Store results
    sw      x3, 0(x2)
    sw      x4, 4(x2)
    sw      x5, 8(x2)
    sw      x6, 12(x2)
    sw      x7, 16(x2)
    sw      x8, 20(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A2_data
    la      x2, test_A2_res
 
    # Load testdata
    lw      x8, 0(x1)
 
    # Register initialization
    li      x9, 1
    li      x10, 0x7FFFFFFF
    li      x11, 0xFFFFFFFF
    li      x12, 0
    li      x13, 0x80000000
 
    # Test
    sltu   x9, x8, x9
    sltu   x10, x8, x10
    sltu   x11, x8, x11
    sltu   x12, x8, x12
    sltu   x13, x8, x13
 
    # Store results
    sw      x8, 0(x2)
    sw      x9, 4(x2)
    sw      x10, 8(x2)
    sw      x11, 12(x2)
    sw      x12, 16(x2)
    sw      x13, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)
    #RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000001)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A3_data
    la      x2, test_A3_res
 
    # Load testdata
    lw      x13, 0(x1)
 
    # Register initialization
    li      x14, 1
    li      x15, 0x7FFFFFFF
    li      x16, 0xFFFFFFFF
    li      x17, 0
    li      x18, 0x80000000
 
    # Test
    sltu   x14, x13, x14
    sltu   x15, x13, x15
    sltu   x16, x13, x16
    sltu   x17, x13, x17
    sltu   x18, x13, x18
 
    # Store results
    sw      x13, 0(x2)
    sw      x14, 4(x2)
    sw      x15, 8(x2)
    sw      x16, 12(x2)
    sw      x17, 16(x2)
    sw      x18, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x16, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x17, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A4_data
    la      x2, test_A4_res
 
    # Load testdata
    lw      x18, 0(x1)
 
    # Register initialization
    li      x19, 1
    li      x20, 0x7FFFFFFF
    li      x21, 0xFFFFFFFF
    li      x22, 0
    li      x23, 0x80000000
 
    # Test
    sltu   x19, x18, x19
    sltu   x20, x18, x20
    sltu   x21, x18, x21
    sltu   x22, x18, x22
    sltu   x23, x18, x23
 
    # Store results
    sw      x18, 0(x2)
    sw      x19, 4(x2)
    sw      x20, 8(x2)
    sw      x21, 12(x2)
    sw      x22, 16(x2)
    sw      x23, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x00000001)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A5_data
    la      x2, test_A5_res
 
    # Load testdata
    lw      x23, 0(x1)
 
    # Register initialization
    li      x24, 1
    li      x25, 0x7FFFFFFF
    li      x26, 0xFFFFFFFF
    li      x27, 0
    li      x28, 0x80000000
 
    # Test
    sltu   x24, x23, x24
    sltu   x25, x23, x25
    sltu   x26, x23, x26
    sltu   x27, x23, x27
    sltu   x28, x23, x28
 
    # Store results
    sw      x23, 0(x2)
    sw      x24, 4(x2)
    sw      x25, 8(x2)
    sw      x26, 12(x2)
    sw      x27, 16(x2)
    sw      x28, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x24, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - testing writing to x0\n");
 
    # Addresses for test data and results
    la      x26, test_B_data
    la      x27, test_B_res
 
    # Load testdata
    lw      x1, 0(x26)
 
    # Register initialization
    li      x2, 0xFFFFFFFF
 
    # Test
    sltu    x0, x1, x2
 
    # Store results
    sw      x0, 0(x27)
    sw      x1, 4(x27)
    sw      x2, 8(x27)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0xFFFFFFFF)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - testing compare x0\n");
 
    # Addresses for test data and results
    la      x31, test_C_res
 
    # Register initialization
    li      x1, 1
    li      x2, 0x7FF
    li      x3, 0xFFFFFFFF
    li      x4, 0
    li      x5, 0xFFFFF800
 
    # Test
    sltu   x6, x0, x1
    sltu   x7, x0, x2
    sltu   x8, x0, x3
    sltu   x9, x0, x4
    sltu   x10, x0, x5
    sltu   x11, x1, x0
    sltu   x12, x2, x0
    sltu   x13, x3, x0
    sltu   x14, x4, x0
    sltu   x15, x5, x0
 
    # Store results
    sw      x6, 0(x31)
    sw      x7, 4(x31)
    sw      x8, 8(x31)
    sw      x9, 12(x31)
    sw      x10, 16(x31)
    sw      x11, 20(x31)
    sw      x12, 24(x31)
    sw      x13, 28(x31)
    sw      x14, 32(x31)
    sw      x15, 36(x31)
 
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)
    #RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D - testing forwarding between instructions\n");
 
    # Addresses for test data and results
    la      x31, test_D_res
 
    # Register initialization
    li      x3, 0x1
 
    # Test
    sltu   x1, x0, x3
    sltu   x2, x1, x3
    sltu   x28, x2, x3
    sltu   x29, x28, x3
    sltu   x30, x29, x3
 
    # Store results
    sw      x1, 0(x31)
    sw      x2, 4(x31)
    sw      x28, 8(x31)
    sw      x29, 12(x31)
    sw      x30, 16(x31)
 
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80001E50)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x29, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00000001)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
test_A1_data:
    .word 0
test_A2_data:
    .word 1
test_A3_data:
    .word -1
test_A4_data:
    .word 0x7FFFFFFF
test_A5_data:
    .word 0x80000000
test_B_data:
    .word 1
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
test_A1_res:
    .fill 6, 4, -1
test_A2_res:
    .fill 6, 4, -1
test_A3_res:
    .fill 6, 4, -1
test_A4_res:
    .fill 6, 4, -1
test_A5_res:
    .fill 6, 4, -1
test_B_res:
    .fill 3, 4, -1
test_C_res:
    .fill 10, 4, -1
test_D_res:
    .fill 5, 4, -1
 
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SLTU-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-SLTU-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction SLTU.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");`
48
49			`# Addresses for test data and results`
50			`la x1, test_A1_data`
51			`la x2, test_A1_res`
52
53			`# Load testdata`
54			`lw x3, 0(x1)`
55
56			`# Register initialization`
57			`li x4, 1`
58			`li x5, 0x7FFFFFFF`
59			`li x6, 0xFFFFFFFF`
60			`li x7, 0`
61			`li x8, 0x80000000`
62
63			`# Test`
64			`sltu x4, x3, x4`
65			`sltu x5, x3, x5`
66			`sltu x6, x3, x6`
67			`sltu x7, x3, x7`
68			`sltu x8, x3, x8`
69
70			`# Store results`
71			`sw x3, 0(x2)`
72			`sw x4, 4(x2)`
73			`sw x5, 8(x2)`
74			`sw x6, 12(x2)`
75			`sw x7, 16(x2)`
76			`sw x8, 20(x2)`
77
78			`//`
79			`// Assert`
80			`//`
81			`RVTEST_IO_CHECK()`
82			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)`
83			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000001)`
84			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
85			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000001)`
86			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000000)`
87			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)`
88
89			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
90
91			`# ---------------------------------------------------------------------------------------------`
92			`RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");`
93
94			`# Addresses for test data and results`
95			`la x1, test_A2_data`
96			`la x2, test_A2_res`
97
98			`# Load testdata`
99			`lw x8, 0(x1)`
100
101			`# Register initialization`
102			`li x9, 1`
103			`li x10, 0x7FFFFFFF`
104			`li x11, 0xFFFFFFFF`
105			`li x12, 0`
106			`li x13, 0x80000000`
107
108			`# Test`
109			`sltu x9, x8, x9`
110			`sltu x10, x8, x10`
111			`sltu x11, x8, x11`
112			`sltu x12, x8, x12`
113			`sltu x13, x8, x13`
114
115			`# Store results`
116			`sw x8, 0(x2)`
117			`sw x9, 4(x2)`
118			`sw x10, 8(x2)`
119			`sw x11, 12(x2)`
120			`sw x12, 16(x2)`
121			`sw x13, 20(x2)`
122
123			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)`
124			`RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)`
125			`#RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)`
126			`RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000001)`
127			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000000)`
128			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000001)`
129
130			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
131
132			`# ---------------------------------------------------------------------------------------------`
133			`RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");`
134
135			`# Addresses for test data and results`
136			`la x1, test_A3_data`
137			`la x2, test_A3_res`
138
139			`# Load testdata`
140			`lw x13, 0(x1)`
141
142			`# Register initialization`
143			`li x14, 1`
144			`li x15, 0x7FFFFFFF`
145			`li x16, 0xFFFFFFFF`
146			`li x17, 0`
147			`li x18, 0x80000000`
148
149			`# Test`
150			`sltu x14, x13, x14`
151			`sltu x15, x13, x15`
152			`sltu x16, x13, x16`
153			`sltu x17, x13, x17`
154			`sltu x18, x13, x18`
155
156			`# Store results`
157			`sw x13, 0(x2)`
158			`sw x14, 4(x2)`
159			`sw x15, 8(x2)`
160			`sw x16, 12(x2)`
161			`sw x17, 16(x2)`
162			`sw x18, 20(x2)`
163
164			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)`
165			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000000)`
166			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)`
167			`RVTEST_IO_ASSERT_GPR_EQ(x16, 0x00000000)`
168			`RVTEST_IO_ASSERT_GPR_EQ(x17, 0x00000000)`
169			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x00000000)`
170
171			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
172
173			`# ---------------------------------------------------------------------------------------------`
174			`RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");`
175
176			`# Addresses for test data and results`
177			`la x1, test_A4_data`
178			`la x2, test_A4_res`
179
180			`# Load testdata`
181			`lw x18, 0(x1)`
182
183			`# Register initialization`
184			`li x19, 1`
185			`li x20, 0x7FFFFFFF`
186			`li x21, 0xFFFFFFFF`
187			`li x22, 0`
188			`li x23, 0x80000000`
189
190			`# Test`
191			`sltu x19, x18, x19`
192			`sltu x20, x18, x20`
193			`sltu x21, x18, x21`
194			`sltu x22, x18, x22`
195			`sltu x23, x18, x23`
196
197			`# Store results`
198			`sw x18, 0(x2)`
199			`sw x19, 4(x2)`
200			`sw x20, 8(x2)`
201			`sw x21, 12(x2)`
202			`sw x22, 16(x2)`
203			`sw x23, 20(x2)`
204
205			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)`
206			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x00000000)`
207			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x00000000)`
208			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x00000001)`
209			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0x00000000)`
210			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x00000001)`
211
212			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
213
214			`# ---------------------------------------------------------------------------------------------`
215			`RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");`
216
217			`# Addresses for test data and results`
218			`la x1, test_A5_data`
219			`la x2, test_A5_res`
220
221			`# Load testdata`
222			`lw x23, 0(x1)`
223
224			`# Register initialization`
225			`li x24, 1`
226			`li x25, 0x7FFFFFFF`
227			`li x26, 0xFFFFFFFF`
228			`li x27, 0`
229			`li x28, 0x80000000`
230
231			`# Test`
232			`sltu x24, x23, x24`
233			`sltu x25, x23, x25`
234			`sltu x26, x23, x26`
235			`sltu x27, x23, x27`
236			`sltu x28, x23, x28`
237
238			`# Store results`
239			`sw x23, 0(x2)`
240			`sw x24, 4(x2)`
241			`sw x25, 8(x2)`
242			`sw x26, 12(x2)`
243			`sw x27, 16(x2)`
244			`sw x28, 20(x2)`
245
246			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)`
247			`RVTEST_IO_ASSERT_GPR_EQ(x24, 0x00000000)`
248			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x00000000)`
249			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x00000001)`
250			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000000)`
251			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000000)`
252
253			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
254
255			`# ---------------------------------------------------------------------------------------------`
256			`RVTEST_IO_WRITE_STR("# Test part B - testing writing to x0\n");`
257
258			`# Addresses for test data and results`
259			`la x26, test_B_data`
260			`la x27, test_B_res`
261
262			`# Load testdata`
263			`lw x1, 0(x26)`
264
265			`# Register initialization`
266			`li x2, 0xFFFFFFFF`
267
268			`# Test`
269			`sltu x0, x1, x2`
270
271			`# Store results`
272			`sw x0, 0(x27)`
273			`sw x1, 4(x27)`
274			`sw x2, 8(x27)`
275
276			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
277			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x00000000)`
278			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0xFFFFFFFF)`
279
280			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
281
282			`# ---------------------------------------------------------------------------------------------`
283			`RVTEST_IO_WRITE_STR("# Test part C - testing compare x0\n");`
284
285			`# Addresses for test data and results`
286			`la x31, test_C_res`
287
288			`# Register initialization`
289			`li x1, 1`
290			`li x2, 0x7FF`
291			`li x3, 0xFFFFFFFF`
292			`li x4, 0`
293			`li x5, 0xFFFFF800`
294
295			`# Test`
296			`sltu x6, x0, x1`
297			`sltu x7, x0, x2`
298			`sltu x8, x0, x3`
299			`sltu x9, x0, x4`
300			`sltu x10, x0, x5`
301			`sltu x11, x1, x0`
302			`sltu x12, x2, x0`
303			`sltu x13, x3, x0`
304			`sltu x14, x4, x0`
305			`sltu x15, x5, x0`
306
307			`# Store results`
308			`sw x6, 0(x31)`
309			`sw x7, 4(x31)`
310			`sw x8, 8(x31)`
311			`sw x9, 12(x31)`
312			`sw x10, 16(x31)`
313			`sw x11, 20(x31)`
314			`sw x12, 24(x31)`
315			`sw x13, 28(x31)`
316			`sw x14, 32(x31)`
317			`sw x15, 36(x31)`
318
319			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000001)`
320			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000001)`
321			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)`
322			`RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)`
323			`#RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)`
324			`RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)`
325			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000000)`
326			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000000)`
327			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0x00000000)`
328			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)`
329
330			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
331
332			`# ---------------------------------------------------------------------------------------------`
333			`RVTEST_IO_WRITE_STR("# Test part D - testing forwarding between instructions\n");`
334
335			`# Addresses for test data and results`
336			`la x31, test_D_res`
337
338			`# Register initialization`
339			`li x3, 0x1`
340
341			`# Test`
342			`sltu x1, x0, x3`
343			`sltu x2, x1, x3`
344			`sltu x28, x2, x3`
345			`sltu x29, x28, x3`
346			`sltu x30, x29, x3`
347
348			`# Store results`
349			`sw x1, 0(x31)`
350			`sw x2, 4(x31)`
351			`sw x28, 8(x31)`
352			`sw x29, 12(x31)`
353			`sw x30, 16(x31)`
354
355			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80001E50)`
356			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x00000000)`
357			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000001)`
358			`RVTEST_IO_ASSERT_GPR_EQ(x29, 0x00000000)`
359			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0x00000001)`
360
361			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
362
363			`RVTEST_IO_WRITE_STR("# Test End\n")`
364
365			`# ---------------------------------------------------------------------------------------------`
366			`# HALT`
367			`RV_COMPLIANCE_HALT`
368
369			`RV_COMPLIANCE_CODE_END`
370
371			`# Input data section.`
372			`.data`
373			`.align 4`
374
375			`test_A1_data:`
376			`.word 0`
377			`test_A2_data:`
378			`.word 1`
379			`test_A3_data:`
380			`.word -1`
381			`test_A4_data:`
382			`.word 0x7FFFFFFF`
383			`test_A5_data:`
384			`.word 0x80000000`
385			`test_B_data:`
386			`.word 1`
387
388			`# Output data section.`
389			`RV_COMPLIANCE_DATA_BEGIN`
390			`.align 4`
391			`test_A1_res:`
392			`.fill 6, 4, -1`
393			`test_A2_res:`
394			`.fill 6, 4, -1`
395			`test_A3_res:`
396			`.fill 6, 4, -1`
397			`test_A4_res:`
398			`.fill 6, 4, -1`
399			`test_A5_res:`
400			`.fill 6, 4, -1`
401			`test_B_res:`
402			`.fill 3, 4, -1`
403			`test_C_res:`
404			`.fill 10, 4, -1`
405			`test_D_res:`
406			`.fill 5, 4, -1`
407
408
409			`RV_COMPLIANCE_DATA_END`