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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SRA-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-SRA-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction SRA.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX (5bit) register values\n");
 
    # Addresses for test data and results
    la      x1, test_A1_data
    la      x2, test_A1_res
 
    # Load testdata
    lw      x3, 0(x1)
 
    # Register initialization
    li      x4, 1
    li      x5, 0xF
    li      x6, 0x1F
    li      x7, 0
    li      x8, 0x10
 
    # Test
    sra     x4, x3, x4
    sra     x5, x3, x5
    sra     x6, x3, x6
    sra     x7, x3, x7
    sra     x8, x3, x8
 
    # Store results
    sw      x3, 0(x2)
    sw      x4, 4(x2)
    sw      x5, 8(x2)
    sw      x6, 12(x2)
    sw      x7, 16(x2)
    sw      x8, 20(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX (5bit) register values\n");
 
    # Addresses for test data and results
    la      x1, test_A2_data
    la      x2, test_A2_res
 
    # Load testdata
    lw      x8, 0(x1)
 
    # Register initialization
    li      x9, 1
    li      x10, 0xF
    li      x11, 0x1F
    li      x12, 0
    li      x13, 0x10
 
    # Test
    sra     x9, x8, x9
    sra     x10, x8, x10
    sra     x11, x8, x11
    sra     x12, x8, x12
    sra     x13, x8, x13
 
    # Store results
    sw      x8, 0(x2)
    sw      x9, 4(x2)
    sw      x10, 8(x2)
    sw      x11, 12(x2)
    sw      x12, 16(x2)
    sw      x13, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX (5bit) register values\n");
 
    # Addresses for test data and results
    la      x1, test_A3_data
    la      x2, test_A3_res
 
    # Load testdata
    lw      x13, 0(x1)
 
    # Register initialization
    li      x14, 1
    li      x15, 0xF
    li      x16, 0x1F
    li      x17, 0
    li      x18, 0x10
 
    # Test
    sra     x14, x13, x14
    sra     x15, x13, x15
    sra     x16, x13, x16
    sra     x17, x13, x17
    sra     x18, x13, x18
 
    # Store results
    sw      x13, 0(x2)
    sw      x14, 4(x2)
    sw      x15, 8(x2)
    sw      x16, 12(x2)
    sw      x17, 16(x2)
    sw      x18, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x16, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x17, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0xFFFFFFFF)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX (5bit) register values\n");
 
    # Addresses for test data and results
    la      x12, test_A4_data
    la      x13, test_A4_res
 
    # Load testdata
    lw      x18, 0(x12)
 
    # Register initialization
    li      x19, 1
    li      x20, 0xF
    li      x21, 0x1F
    li      x22, 0
    li      x23, 0x10
 
    # Test
    sra     x19, x18, x19
    sra     x20, x18, x20
    sra     x21, x18, x21
    sra     x22, x18, x22
    sra     x23, x18, x23
 
    # Store results
    sw      x18, 0(x13)
    sw      x19, 4(x13)
    sw      x20, 8(x13)
    sw      x21, 12(x13)
    sw      x22, 16(x13)
    sw      x23, 20(x13)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x3FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0000FFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x00007FFF)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX (5bit) register values\n");
 
    # Addresses for test data and results
    la      x12, test_A5_data
    la      x13, test_A5_res
 
    # Load testdata
    lw      x23, 0(x12)
 
    # Register initialization
    li      x24, 1
    li      x25, 0xF
    li      x26, 0x1F
    li      x27, 0
    li      x28, 0x10
 
    # Test
    sra     x24, x23, x24
    sra     x25, x23, x25
    sra     x26, x23, x26
    sra     x27, x23, x27
    sra     x28, x23, x28
 
    # Store results
    sw      x23, 0(x13)
    sw      x24, 4(x13)
    sw      x25, 8(x13)
    sw      x26, 12(x13)
    sw      x27, 16(x13)
    sw      x28, 20(x13)
 
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x24, 0xC0000000)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0xFFFF0000)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0xFFFF8000)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - testing forwarding between instructions\n");
 
    # Addresses for test data and results
    la      x25, test_B_data
    la      x26, test_B_res
 
    # Load testdata
    lw      x28, 0(x25)
 
    # Register initialization
    li      x27, 0x1
 
    # Test
    sra     x29, x28, x27
    sra     x30, x29, x27
    sra     x31, x30, x27
    sra     x1, x31, x27
    sra     x2, x1, x27
    sra     x3, x2, x27
 
    # Store results
    sw      x28, 0(x26)
    sw      x29, 4(x26)
    sw      x30, 8(x26)
    sw      x31, 12(x26)
    sw      x1, 16(x26)
    sw      x2, 20(x26)
    sw      x3, 24(x26)
 
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0xABCDEF10)
    RVTEST_IO_ASSERT_GPR_EQ(x29, 0xD5E6F788)
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0xEAF37BC4)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0xF579BDE2)
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x800019EC)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0xFD5E6F78)
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0xFEAF37BC)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - testing writing to x0\n");
 
    # Addresses for test data and results
    la      x1, test_C_data
    la      x2, test_C_res
 
    # Load testdata
    lw      x5, 0(x1)
 
    # Register initialization
    li      x27, 1
 
    # Test
    sra     x0, x5, x27
 
    # Store results
    sw      x0, 0(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D - testing forwarding throught x0\n");
 
    # Addresses for test data and results
    la      x1, test_D_data
    la      x2, test_D_res
 
    # Load testdata
    lw      x5, 0(x1)
 
    # Register initialization
    li      x27, 1
 
    # Test
    sra     x0, x5, x27
    sra     x5, x0, x27
 
    # Store results
    sw      x0, 0(x2)
    sw      x5, 4(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E - testing shift by value greater than 31\n");
 
    # Addresses for test data and results
    la      x1, test_E_data
    la      x2, test_E_res
 
    # Load testdata
    lw      x3, 0(x1)
 
    # Register initialization
    li      x4, 0xFFFFFE0
    li      x5, 0xFFFFFE1
    li      x6, 0xFFFFFEF
    li      x7, 0xFFFFFFF
 
    # Test
    sra     x4, x3, x4
    sra     x5, x3, x5
    sra     x6, x3, x6
    sra     x7, x3, x7
 
    # Store results
    sw      x4, 0(x2)
    sw      x5, 4(x2)
    sw      x6, 8(x2)
    sw      x7, 12(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x87654321)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0xFFFF0ECA)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0xFFFFFFFF)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
test_A1_data:
    .word 0
test_A2_data:
    .word 1
test_A3_data:
    .word -1
test_A4_data:
    .word 0x7FFFFFFF
test_A5_data:
    .word 0x80000000
test_B_data:
    .word 0xABCDEF10
test_C_data:
    .word 0x12345678
test_D_data:
    .word 0xFEDCBA98
test_E_data:
    .word 0x87654321
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res:
    .fill 6, 4, -1
test_A2_res:
    .fill 6, 4, -1
test_A3_res:
    .fill 6, 4, -1
test_A4_res:
    .fill 6, 4, -1
test_A5_res:
    .fill 6, 4, -1
test_B_res:
    .fill 7, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D_res:
    .fill 2, 4, -1
test_E_res:
    .fill 4, 4, -1
 
RV_COMPLIANCE_DATA_END

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-SRA-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-SRA-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction SRA.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX (5bit) register values\n");`
48
49			`# Addresses for test data and results`
50			`la x1, test_A1_data`
51			`la x2, test_A1_res`
52
53			`# Load testdata`
54			`lw x3, 0(x1)`
55
56			`# Register initialization`
57			`li x4, 1`
58			`li x5, 0xF`
59			`li x6, 0x1F`
60			`li x7, 0`
61			`li x8, 0x10`
62
63			`# Test`
64			`sra x4, x3, x4`
65			`sra x5, x3, x5`
66			`sra x6, x3, x6`
67			`sra x7, x3, x7`
68			`sra x8, x3, x8`
69
70			`# Store results`
71			`sw x3, 0(x2)`
72			`sw x4, 4(x2)`
73			`sw x5, 8(x2)`
74			`sw x6, 12(x2)`
75			`sw x7, 16(x2)`
76			`sw x8, 20(x2)`
77
78			`//`
79			`// Assert`
80			`//`
81			`RVTEST_IO_CHECK()`
82			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)`
83			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000000)`
84			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
85			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0x00000000)`
86			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0x00000000)`
87			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000000)`
88
89			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
90
91			`# ---------------------------------------------------------------------------------------------`
92			`RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX (5bit) register values\n");`
93
94			`# Addresses for test data and results`
95			`la x1, test_A2_data`
96			`la x2, test_A2_res`
97
98			`# Load testdata`
99			`lw x8, 0(x1)`
100
101			`# Register initialization`
102			`li x9, 1`
103			`li x10, 0xF`
104			`li x11, 0x1F`
105			`li x12, 0`
106			`li x13, 0x10`
107
108			`# Test`
109			`sra x9, x8, x9`
110			`sra x10, x8, x10`
111			`sra x11, x8, x11`
112			`sra x12, x8, x12`
113			`sra x13, x8, x13`
114
115			`# Store results`
116			`sw x8, 0(x2)`
117			`sw x9, 4(x2)`
118			`sw x10, 8(x2)`
119			`sw x11, 12(x2)`
120			`sw x12, 16(x2)`
121			`sw x13, 20(x2)`
122
123			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)`
124			`RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000000)`
125			`RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)`
126			`RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)`
127			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x00000001)`
128			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x00000000)`
129
130			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
131
132			`# ---------------------------------------------------------------------------------------------`
133			`RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX (5bit) register values\n");`
134
135			`# Addresses for test data and results`
136			`la x1, test_A3_data`
137			`la x2, test_A3_res`
138
139			`# Load testdata`
140			`lw x13, 0(x1)`
141
142			`# Register initialization`
143			`li x14, 1`
144			`li x15, 0xF`
145			`li x16, 0x1F`
146			`li x17, 0`
147			`li x18, 0x10`
148
149			`# Test`
150			`sra x14, x13, x14`
151			`sra x15, x13, x15`
152			`sra x16, x13, x16`
153			`sra x17, x13, x17`
154			`sra x18, x13, x18`
155
156			`# Store results`
157			`sw x13, 0(x2)`
158			`sw x14, 4(x2)`
159			`sw x15, 8(x2)`
160			`sw x16, 12(x2)`
161			`sw x17, 16(x2)`
162			`sw x18, 20(x2)`
163
164			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)`
165			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0xFFFFFFFF)`
166			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0xFFFFFFFF)`
167			`RVTEST_IO_ASSERT_GPR_EQ(x16, 0xFFFFFFFF)`
168			`RVTEST_IO_ASSERT_GPR_EQ(x17, 0xFFFFFFFF)`
169			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0xFFFFFFFF)`
170
171			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
172
173			`# ---------------------------------------------------------------------------------------------`
174			`RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX (5bit) register values\n");`
175
176			`# Addresses for test data and results`
177			`la x12, test_A4_data`
178			`la x13, test_A4_res`
179
180			`# Load testdata`
181			`lw x18, 0(x12)`
182
183			`# Register initialization`
184			`li x19, 1`
185			`li x20, 0xF`
186			`li x21, 0x1F`
187			`li x22, 0`
188			`li x23, 0x10`
189
190			`# Test`
191			`sra x19, x18, x19`
192			`sra x20, x18, x20`
193			`sra x21, x18, x21`
194			`sra x22, x18, x22`
195			`sra x23, x18, x23`
196
197			`# Store results`
198			`sw x18, 0(x13)`
199			`sw x19, 4(x13)`
200			`sw x20, 8(x13)`
201			`sw x21, 12(x13)`
202			`sw x22, 16(x13)`
203			`sw x23, 20(x13)`
204
205			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)`
206			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x3FFFFFFF)`
207			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x0000FFFF)`
208			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x00000000)`
209			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0x7FFFFFFF)`
210			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x00007FFF)`
211
212			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
213
214			`# ---------------------------------------------------------------------------------------------`
215			`RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX (5bit) register values\n");`
216
217			`# Addresses for test data and results`
218			`la x12, test_A5_data`
219			`la x13, test_A5_res`
220
221			`# Load testdata`
222			`lw x23, 0(x12)`
223
224			`# Register initialization`
225			`li x24, 1`
226			`li x25, 0xF`
227			`li x26, 0x1F`
228			`li x27, 0`
229			`li x28, 0x10`
230
231			`# Test`
232			`sra x24, x23, x24`
233			`sra x25, x23, x25`
234			`sra x26, x23, x26`
235			`sra x27, x23, x27`
236			`sra x28, x23, x28`
237
238			`# Store results`
239			`sw x23, 0(x13)`
240			`sw x24, 4(x13)`
241			`sw x25, 8(x13)`
242			`sw x26, 12(x13)`
243			`sw x27, 16(x13)`
244			`sw x28, 20(x13)`
245
246			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)`
247			`RVTEST_IO_ASSERT_GPR_EQ(x24, 0xC0000000)`
248			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0xFFFF0000)`
249			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0xFFFFFFFF)`
250			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x80000000)`
251			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0xFFFF8000)`
252
253			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
254
255			`# ---------------------------------------------------------------------------------------------`
256			`RVTEST_IO_WRITE_STR("# Test part B - testing forwarding between instructions\n");`
257
258			`# Addresses for test data and results`
259			`la x25, test_B_data`
260			`la x26, test_B_res`
261
262			`# Load testdata`
263			`lw x28, 0(x25)`
264
265			`# Register initialization`
266			`li x27, 0x1`
267
268			`# Test`
269			`sra x29, x28, x27`
270			`sra x30, x29, x27`
271			`sra x31, x30, x27`
272			`sra x1, x31, x27`
273			`sra x2, x1, x27`
274			`sra x3, x2, x27`
275
276			`# Store results`
277			`sw x28, 0(x26)`
278			`sw x29, 4(x26)`
279			`sw x30, 8(x26)`
280			`sw x31, 12(x26)`
281			`sw x1, 16(x26)`
282			`sw x2, 20(x26)`
283			`sw x3, 24(x26)`
284
285			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0xABCDEF10)`
286			`RVTEST_IO_ASSERT_GPR_EQ(x29, 0xD5E6F788)`
287			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0xEAF37BC4)`
288			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0xF579BDE2)`
289			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x800019EC)`
290			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0xFD5E6F78)`
291			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0xFEAF37BC)`
292
293			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
294
295			`# ---------------------------------------------------------------------------------------------`
296			`RVTEST_IO_WRITE_STR("# Test part C - testing writing to x0\n");`
297
298			`# Addresses for test data and results`
299			`la x1, test_C_data`
300			`la x2, test_C_res`
301
302			`# Load testdata`
303			`lw x5, 0(x1)`
304
305			`# Register initialization`
306			`li x27, 1`
307
308			`# Test`
309			`sra x0, x5, x27`
310
311			`# Store results`
312			`sw x0, 0(x2)`
313
314			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
315
316			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
317
318			`# ---------------------------------------------------------------------------------------------`
319			`RVTEST_IO_WRITE_STR("# Test part D - testing forwarding throught x0\n");`
320
321			`# Addresses for test data and results`
322			`la x1, test_D_data`
323			`la x2, test_D_res`
324
325			`# Load testdata`
326			`lw x5, 0(x1)`
327
328			`# Register initialization`
329			`li x27, 1`
330
331			`# Test`
332			`sra x0, x5, x27`
333			`sra x5, x0, x27`
334
335			`# Store results`
336			`sw x0, 0(x2)`
337			`sw x5, 4(x2)`
338
339			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
340			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
341
342			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
343
344			`# ---------------------------------------------------------------------------------------------`
345			`RVTEST_IO_WRITE_STR("# Test part E - testing shift by value greater than 31\n");`
346
347			`# Addresses for test data and results`
348			`la x1, test_E_data`
349			`la x2, test_E_res`
350
351			`# Load testdata`
352			`lw x3, 0(x1)`
353
354			`# Register initialization`
355			`li x4, 0xFFFFFE0`
356			`li x5, 0xFFFFFE1`
357			`li x6, 0xFFFFFEF`
358			`li x7, 0xFFFFFFF`
359
360			`# Test`
361			`sra x4, x3, x4`
362			`sra x5, x3, x5`
363			`sra x6, x3, x6`
364			`sra x7, x3, x7`
365
366			`# Store results`
367			`sw x4, 0(x2)`
368			`sw x5, 4(x2)`
369			`sw x6, 8(x2)`
370			`sw x7, 12(x2)`
371
372			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x87654321)`
373			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
374			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0xFFFF0ECA)`
375			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0xFFFFFFFF)`
376
377			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
378
379			`RVTEST_IO_WRITE_STR("# Test End\n")`
380
381			`# ---------------------------------------------------------------------------------------------`
382			`# HALT`
383			`RV_COMPLIANCE_HALT`
384
385			`RV_COMPLIANCE_CODE_END`
386
387			`# Input data section.`
388			`.data`
389			`.align 4`
390			`test_A1_data:`
391			`.word 0`
392			`test_A2_data:`
393			`.word 1`
394			`test_A3_data:`
395			`.word -1`
396			`test_A4_data:`
397			`.word 0x7FFFFFFF`
398			`test_A5_data:`
399			`.word 0x80000000`
400			`test_B_data:`
401			`.word 0xABCDEF10`
402			`test_C_data:`
403			`.word 0x12345678`
404			`test_D_data:`
405			`.word 0xFEDCBA98`
406			`test_E_data:`
407			`.word 0x87654321`
408
409			`# Output data section.`
410			`RV_COMPLIANCE_DATA_BEGIN`
411			`.align 4`
412
413			`test_A1_res:`
414			`.fill 6, 4, -1`
415			`test_A2_res:`
416			`.fill 6, 4, -1`
417			`test_A3_res:`
418			`.fill 6, 4, -1`
419			`test_A4_res:`
420			`.fill 6, 4, -1`
421			`test_A5_res:`
422			`.fill 6, 4, -1`
423			`test_B_res:`
424			`.fill 7, 4, -1`
425			`test_C_res:`
426			`.fill 1, 4, -1`
427			`test_D_res:`
428			`.fill 2, 4, -1`
429			`test_E_res:`
430			`.fill 4, 4, -1`
431
432			`RV_COMPLIANCE_DATA_END`