URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [Makefrag] - Blame information for rev 2

Details | Compare with Previous | View Log


rv32mi_sc_tests =    \
        breakpoint \
        ma_fetch \
        ma_addr \
        scall \
        sbreak \
        shamt \
        csr \
        mcsr \
        illegal
 
ifeq ($(RISCV_TARGET),riscvOVPsim)
    rv32mi_sc_tests := $(subst breakpoint,,$(rv32mi_sc_tests))
endif
 
rv32mi_tests = $(addsuffix .elf, $(rv32mi_sc_tests))
 
target32_tests += $(rv32mi_tests)

Line No.	Rev	Author	Line
1	2	mballance	`rv32mi_sc_tests = \`
2			`breakpoint \`
3			`ma_fetch \`
4			`ma_addr \`
5			`scall \`
6			`sbreak \`
7			`shamt \`
8			`csr \`
9			`mcsr \`
10			`illegal`
11
12			`ifeq ($(RISCV_TARGET),riscvOVPsim)`
13			`rv32mi_sc_tests := $(subst breakpoint,,$(rv32mi_sc_tests))`
14			`endif`
15
16			`rv32mi_tests = $(addsuffix .elf, $(rv32mi_sc_tests))`
17
18			`target32_tests += $(rv32mi_tests)`

Browse

Tools

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [Makefrag] - Blame information for rev 2