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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [breakpoint.S] - Blame information for rev 2

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# See LICENSE for license details.
 
#*****************************************************************************
# breakpoint.S
#-----------------------------------------------------------------------------
#
# Test breakpoints, if they are implemented.
#
 
#include "riscv_test.h"
#include "compliance_test.h"
#include "compliance_io.h"
#include "aw_test_macros.h"
 
RVTEST_RV64M
RVTEST_CODE_BEGIN
 
  # Set up breakpoint to trap on M-mode fetches.
  li TESTNUM, 2
  SWSIG(2, TESTNUM)
 
  # Skip tselect if hard-wired.
  csrw tselect, x0
  csrr a1, tselect
  bne x0, a1, pass
 
  # Make sure there's a breakpoint there.
  csrr a0, tdata1
  srli a0, a0, __riscv_xlen - 4
  li a1, 2
  bne a0, a1, pass
 
  la a2, 1f
  csrw tdata2, a2
  li a0, MCONTROL_M | MCONTROL_EXECUTE
  csrw tdata1, a0
  # Skip if breakpoint type is unsupported.
  csrr a1, tdata1
  andi a1, a1, 0x7ff
  bne a0, a1, 2f
  .align 2
1:
  # Trap handler should skip this instruction.
  beqz x0, fail
 
  # Make sure reads don't trap.
  li TESTNUM, 3
  SWSIG(3, TESTNUM)
  lw a0, (a2)
 
2:
  # Set up breakpoint to trap on M-mode reads.
  li TESTNUM, 4
  SWSIG(4, TESTNUM)
  li a0, MCONTROL_M | MCONTROL_LOAD
  csrw tdata1, a0
  # Skip if breakpoint type is unsupported.
  csrr a1, tdata1
  andi a1, a1, 0x7ff
  bne a0, a1, 2f
  la a2, data1
  csrw tdata2, a2
 
  # Trap handler should skip this instruction.
  lw a2, (a2)
  beqz a2, fail
 
  # Make sure writes don't trap.
  li TESTNUM, 5
  SWSIG(5, TESTNUM)
  sw x0, (a2)
 
2:
  # Set up breakpoint to trap on M-mode stores.
  li TESTNUM, 6
  SWSIG(6, TESTNUM)
  li a0, MCONTROL_M | MCONTROL_STORE
  csrw tdata1, a0
  # Skip if breakpoint type is unsupported.
  csrr a1, tdata1
  andi a1, a1, 0x7ff
  bne a0, a1, 2f
 
  # Trap handler should skip this instruction.
  sw a2, (a2)
 
  # Make sure store didn't succeed.
  li TESTNUM, 7
  SWSIG(7, TESTNUM)
  lw a2, (a2)
  bnez a2, fail
 
  # Try to set up a second breakpoint.
  li a0, 1
  csrw tselect, a0
  csrr a1, tselect
  bne a0, a1, pass
 
  # Make sure there's a breakpoint there.
  csrr a0, tdata1
  srli a0, a0, __riscv_xlen - 4
  li a1, 2
  bne a0, a1, pass
 
  li a0, MCONTROL_M | MCONTROL_LOAD
  csrw tdata1, a0
  la a3, data2
  csrw tdata2, a3
 
  # Make sure the second breakpoint triggers.
  li TESTNUM, 8
  SWSIG(8, TESTNUM)
  lw a3, (a3)
  beqz a3, fail
 
  # Make sure the first breakpoint still triggers.
  li TESTNUM, 10
  SWSIG(10, TESTNUM)
  la a2, data1
  sw a2, (a2)
  li TESTNUM, 11
  SWSIG(11, TESTNUM)
  lw a2, (a2)
  bnez a2, fail
 
2:
  TEST_PASSFAIL
 
  .align 2
  .global mtvec_handler
mtvec_handler:
  # Only even-numbered tests should trap.
  andi t0, TESTNUM, 1
  bnez t0, fail
 
  li t0, CAUSE_BREAKPOINT
  csrr t1, mcause
  bne t0, t1, fail
 
  csrr t0, mepc
  addi t0, t0, 4
  csrw mepc, t0
  mret
 
RVTEST_CODE_END
 
  .data
data1: .word 0
data2: .word 0
 
RV_COMPLIANCE_DATA_BEGIN
test_res:
    .fill 32, 4, -1
RV_COMPLIANCE_DATA_END
 

Line No.	Rev	Author	Line
1	2	mballance	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# breakpoint.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test breakpoints, if they are implemented.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "compliance_test.h"`
12			`#include "compliance_io.h"`
13			`#include "aw_test_macros.h"`
14
15			`RVTEST_RV64M`
16			`RVTEST_CODE_BEGIN`
17
18			`# Set up breakpoint to trap on M-mode fetches.`
19			`li TESTNUM, 2`
20			`SWSIG(2, TESTNUM)`
21
22			`# Skip tselect if hard-wired.`
23			`csrw tselect, x0`
24			`csrr a1, tselect`
25			`bne x0, a1, pass`
26
27			`# Make sure there's a breakpoint there.`
28			`csrr a0, tdata1`
29			`srli a0, a0, __riscv_xlen - 4`
30			`li a1, 2`
31			`bne a0, a1, pass`
32
33			`la a2, 1f`
34			`csrw tdata2, a2`
35			`li a0, MCONTROL_M \| MCONTROL_EXECUTE`
36			`csrw tdata1, a0`
37			`# Skip if breakpoint type is unsupported.`
38			`csrr a1, tdata1`
39			`andi a1, a1, 0x7ff`
40			`bne a0, a1, 2f`
41			`.align 2`
42			`1:`
43			`# Trap handler should skip this instruction.`
44			`beqz x0, fail`
45
46			`# Make sure reads don't trap.`
47			`li TESTNUM, 3`
48			`SWSIG(3, TESTNUM)`
49			`lw a0, (a2)`
50
51			`2:`
52			`# Set up breakpoint to trap on M-mode reads.`
53			`li TESTNUM, 4`
54			`SWSIG(4, TESTNUM)`
55			`li a0, MCONTROL_M \| MCONTROL_LOAD`
56			`csrw tdata1, a0`
57			`# Skip if breakpoint type is unsupported.`
58			`csrr a1, tdata1`
59			`andi a1, a1, 0x7ff`
60			`bne a0, a1, 2f`
61			`la a2, data1`
62			`csrw tdata2, a2`
63
64			`# Trap handler should skip this instruction.`
65			`lw a2, (a2)`
66			`beqz a2, fail`
67
68			`# Make sure writes don't trap.`
69			`li TESTNUM, 5`
70			`SWSIG(5, TESTNUM)`
71			`sw x0, (a2)`
72
73			`2:`
74			`# Set up breakpoint to trap on M-mode stores.`
75			`li TESTNUM, 6`
76			`SWSIG(6, TESTNUM)`
77			`li a0, MCONTROL_M \| MCONTROL_STORE`
78			`csrw tdata1, a0`
79			`# Skip if breakpoint type is unsupported.`
80			`csrr a1, tdata1`
81			`andi a1, a1, 0x7ff`
82			`bne a0, a1, 2f`
83
84			`# Trap handler should skip this instruction.`
85			`sw a2, (a2)`
86
87			`# Make sure store didn't succeed.`
88			`li TESTNUM, 7`
89			`SWSIG(7, TESTNUM)`
90			`lw a2, (a2)`
91			`bnez a2, fail`
92
93			`# Try to set up a second breakpoint.`
94			`li a0, 1`
95			`csrw tselect, a0`
96			`csrr a1, tselect`
97			`bne a0, a1, pass`
98
99			`# Make sure there's a breakpoint there.`
100			`csrr a0, tdata1`
101			`srli a0, a0, __riscv_xlen - 4`
102			`li a1, 2`
103			`bne a0, a1, pass`
104
105			`li a0, MCONTROL_M \| MCONTROL_LOAD`
106			`csrw tdata1, a0`
107			`la a3, data2`
108			`csrw tdata2, a3`
109
110			`# Make sure the second breakpoint triggers.`
111			`li TESTNUM, 8`
112			`SWSIG(8, TESTNUM)`
113			`lw a3, (a3)`
114			`beqz a3, fail`
115
116			`# Make sure the first breakpoint still triggers.`
117			`li TESTNUM, 10`
118			`SWSIG(10, TESTNUM)`
119			`la a2, data1`
120			`sw a2, (a2)`
121			`li TESTNUM, 11`
122			`SWSIG(11, TESTNUM)`
123			`lw a2, (a2)`
124			`bnez a2, fail`
125
126			`2:`
127			`TEST_PASSFAIL`
128
129			`.align 2`
130			`.global mtvec_handler`
131			`mtvec_handler:`
132			`# Only even-numbered tests should trap.`
133			`andi t0, TESTNUM, 1`
134			`bnez t0, fail`
135
136			`li t0, CAUSE_BREAKPOINT`
137			`csrr t1, mcause`
138			`bne t0, t1, fail`
139
140			`csrr t0, mepc`
141			`addi t0, t0, 4`
142			`csrw mepc, t0`
143			`mret`
144
145			`RVTEST_CODE_END`
146
147			`.data`
148			`data1: .word 0`
149			`data2: .word 0`
150
151			`RV_COMPLIANCE_DATA_BEGIN`
152			`test_res:`
153			`.fill 32, 4, -1`
154			`RV_COMPLIANCE_DATA_END`
155

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [breakpoint.S] - Blame information for rev 2