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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32si/] [rv64si/] [ma_fetch.S] - Blame information for rev 2

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1 2 mballance
# See LICENSE for license details.
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#*****************************************************************************
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# ma_fetch.S
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#-----------------------------------------------------------------------------
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#
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# Test misaligned fetch trap.
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#
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#include "riscv_test.h"
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#include "compliance_test.h"
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#include "compliance_io.h"
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#include "aw_test_macros.h"
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RVTEST_RV64S
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RVTEST_CODE_BEGIN
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#ifdef __MACHINE_MODE
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  #define sscratch mscratch
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  #define sstatus mstatus
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  #define scause mcause
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  #define sbadaddr mbadaddr
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  #define sepc mepc
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  #define sret mret
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  #define stvec_handler mtvec_handler
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#endif
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  .align 2
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  .option norvc
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  # Without RVC, the jalr should trap, and the handler will skip ahead.
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  # With RVC, the jalr should not trap, and "j fail" should get skipped.
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  li TESTNUM, 2
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  SWSIG(2, TESTNUM)
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  li t1, 0
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  la t0, 1f
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  jalr t1, t0, 2
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1:
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  .option rvc
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  c.j 1f
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  c.j 2f
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  .option norvc
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1:
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  j fail
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2:
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  // This test should pass, since JALR ignores the target LSB
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  li TESTNUM, 3
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  SWSIG(3, TESTNUM)
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  la t0, 1f
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  jalr t1, t0, 1
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1:
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  j 1f
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  j fail
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1:
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  li TESTNUM, 4
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  SWSIG(4, TESTNUM)
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  li t1, 0
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  la t0, 1f
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  jalr t1, t0, 3
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1:
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  .option rvc
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  c.j 1f
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  c.j 2f
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  .option norvc
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1:
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  j fail
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2:
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  # Like test 2, but with jal instead of jalr.
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  li TESTNUM, 5
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  SWSIG(5, TESTNUM)
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  li t1, 0
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  la t0, 1f
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  jal t1, 2f
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1:
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  .option rvc
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  c.j 1f
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2:
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  c.j 2f
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  .option norvc
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1:
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  j fail
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2:
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  # Like test 2, but with a taken branch instead of jalr.
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  li TESTNUM, 6
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  SWSIG(6, TESTNUM)
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  li t1, 0
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  la t0, 1f
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  beqz x0, 2f
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  .option rvc
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  c.j 1f
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2:
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  c.j 2f
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  .option norvc
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1:
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  j fail
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2:
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  # Not-taken branches should not trap, even without RVC.
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  li TESTNUM, 7
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  SWSIG(7, TESTNUM)
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  bnez x0, 1f
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  j 2f
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  .option rvc
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  c.j 1f
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1:
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  c.j 1f
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  .option norvc
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1:
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  j fail
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2:
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#ifdef __MACHINE_MODE
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  # RVC cannot be disabled if doing so would cause a misaligned instruction
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  # exception on the next instruction fetch. (This test assumes no other
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  # extensions that support misalignment are present.)
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  li TESTNUM, 8
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  SWSIG(8, TESTNUM)
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  csrr t2, misa
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  andi t2, t2, 1 << ('c' - 'a')
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  beqz t2, 2f
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  .option rvc
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  c.nop
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  csrci misa, 1 << ('c' - 'a')
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1:
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  c.nop
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  .option norvc
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  csrr t2, misa
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  andi t2, t2, 1 << ('c' - 'a')
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  beqz t2, fail
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  # When RVC is disabled, mret to a misaligned mepc should succeed,
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  # masking off mepc[1].
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  la t0, 1f
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  addi t0, t0, -2
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  csrw mepc, t0
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  # Try to disable RVC; if it can't be disabled, skip the test.
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  csrci misa, 1 << ('c' - 'a')
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  csrr t2, misa
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  andi t2, t2, 1 << ('c' - 'a')
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  bnez t2, 2f
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  li t2, MSTATUS_MPP
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  csrs mstatus, t2
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  mret
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  # mret should transfer control to this branch.  Otherwise, it will
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  # transfer control two bytes into the branch, which happens to be the
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  # illegal instruction c.unimp.
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  beqz x0, 1f
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  csrsi misa, 1 << ('c' - 'a')
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2:
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#endif
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  j pass
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  TEST_PASSFAIL
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  .align 2
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  .global stvec_handler
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stvec_handler:
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  # tests 2, 4, 5, 6, and 8 should trap
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  li a0, 2
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  beq TESTNUM, a0, 1f
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  li a0, 4
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  beq TESTNUM, a0, 1f
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  li a0, 5
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  beq TESTNUM, a0, 1f
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  li a0, 6
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  beq TESTNUM, a0, 1f
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  j fail
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1:
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  # verify that return address was not written
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  bnez t1, fail
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  # verify trap cause
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  li a1, CAUSE_MISALIGNED_FETCH
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  csrr a0, scause
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  bne a0, a1, fail
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  # verify that epc == &jalr (== t0 - 4)
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  csrr a1, sepc
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  addi a1, a1, 4
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  bne t0, a1, fail
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  # verify that badaddr == 0 or badaddr == t0+2.
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  csrr a0, sbadaddr
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  beqz a0, 1f
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  addi a0, a0, -2
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  bne a0, t0, fail
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1:
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  addi a1, a1, 12
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  csrw sepc, a1
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  sret
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RVTEST_CODE_END
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  .data
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RV_COMPLIANCE_DATA_BEGIN
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test_res:
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    .fill 40, 4, -1
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RV_COMPLIANCE_DATA_END
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